5 /* The ATU offsets can change based on the strapping */
6 extern u32 iop13xx_atux_pmmr_offset;
7 extern u32 iop13xx_atue_pmmr_offset;
8 void iop13xx_init_irq(void);
9 void iop13xx_map_io(void);
10 void iop13xx_platform_init(void);
11 void iop13xx_add_tpmi_devices(void);
12 void iop13xx_init_irq(void);
14 /* CPUID CP6 R0 Page 0 */
15 static inline int iop13xx_cpu_id(void)
18 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
25 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
27 #define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
28 #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
31 * bus range cpu phys cpu virt note
32 * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
33 * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
34 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
37 * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window
38 * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window
40 #define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
41 #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
42 #define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
43 #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
44 #define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
45 #define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
46 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
47 #define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
48 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
49 #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
50 (IOP13XX_PCIX_LOWER_IO_PA\
51 - IOP13XX_PCIX_LOWER_IO_VA))
53 #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
54 #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
55 #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
56 #define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
57 IOP13XX_PCIX_LOWER_MEM_BA)
58 #define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
59 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
60 #define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
61 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
63 #define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
64 #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
65 #define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
66 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
67 #define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
68 IOP13XX_PCIX_LOWER_MEM_BA)
71 #define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
72 #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
73 #define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
74 #define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
75 #define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
76 #define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
77 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
78 #define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
79 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
80 #define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
81 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
82 #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
83 (IOP13XX_PCIE_LOWER_IO_PA\
84 - IOP13XX_PCIE_LOWER_IO_VA))
86 #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
87 #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
88 #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
89 #define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
90 IOP13XX_PCIE_LOWER_MEM_BA)
91 #define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
92 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
93 #define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
94 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
96 /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
97 #define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
98 #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
99 #define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
100 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
101 #define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
102 IOP13XX_PCIE_LOWER_MEM_BA)
105 #define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
106 #define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
107 #define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
108 #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
109 #define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
110 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
113 * IOP13XX chipset registers
115 #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
116 #define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
117 #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
118 #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
119 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
120 #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
121 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
122 #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
123 (IOP13XX_PMMR_PHYS_MEM_BASE\
124 - IOP13XX_PMMR_VIRT_MEM_BASE))
125 #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
126 (IOP13XX_PMMR_PHYS_MEM_BASE\
127 - IOP13XX_PMMR_VIRT_MEM_BASE))
128 #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
129 #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
130 #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
131 #define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
132 #define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
133 #define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
134 #define IOP13XX_PMMR_SIZE 0x00080000
136 /*=================== Defines for Platform Devices =====================*/
137 #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
138 #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
139 #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
140 #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
142 #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
143 #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
144 #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
145 #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
146 #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
147 #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
149 /* ATU selection flags */
150 /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
151 #define IOP13XX_INIT_ATU_DEFAULT (0)
152 #define IOP13XX_INIT_ATU_ATUX (1 << 0)
153 #define IOP13XX_INIT_ATU_ATUE (1 << 1)
154 #define IOP13XX_INIT_ATU_NONE (1 << 2)
156 /* UART selection flags */
157 /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
158 #define IOP13XX_INIT_UART_DEFAULT (0)
159 #define IOP13XX_INIT_UART_0 (1 << 0)
160 #define IOP13XX_INIT_UART_1 (1 << 1)
162 /* I2C selection flags */
163 /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
164 #define IOP13XX_INIT_I2C_DEFAULT (0)
165 #define IOP13XX_INIT_I2C_0 (1 << 0)
166 #define IOP13XX_INIT_I2C_1 (1 << 1)
167 #define IOP13XX_INIT_I2C_2 (1 << 2)
169 /* ADMA selection flags */
170 /* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
171 #define IOP13XX_INIT_ADMA_DEFAULT (0)
172 #define IOP13XX_INIT_ADMA_0 (1 << 0)
173 #define IOP13XX_INIT_ADMA_1 (1 << 1)
174 #define IOP13XX_INIT_ADMA_2 (1 << 2)
176 /* Platform devices */
177 #define IQ81340_NUM_UART 2
178 #define IQ81340_NUM_I2C 3
179 #define IQ81340_NUM_PHYS_MAP_FLASH 1
180 #define IQ81340_NUM_ADMA 3
181 #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
183 IQ81340_NUM_PHYS_MAP_FLASH + \
186 /*========================== PMMR offsets for key registers ============*/
187 #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
188 #define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
189 #define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
190 #define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
191 #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
192 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
193 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580
194 #define IOP13XX_MU_PMMR_OFFSET 0x00004000
195 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
196 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
198 #define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
199 #define IOP13XX_CONTROLLER_ONLY (1 << 14)
200 #define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
202 #define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
203 #define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
204 IOP13XX_PMON_PMMR_OFFSET)
205 #define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
206 IOP13XX_PMON_PMMR_OFFSET)
208 #define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
209 #define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
210 #define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
211 #define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
213 #define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
214 #define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
215 #define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
216 #define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
218 #define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
219 #define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
220 #define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
221 #define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
223 #define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
224 #define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
226 /*================================ATU===================================*/
227 #define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
228 iop13xx_atux_pmmr_offset + (ofs))
230 #define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
231 iop13xx_atux_pmmr_offset + 0x2)
233 #define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
234 iop13xx_atux_pmmr_offset + 0x4)
235 #define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
236 iop13xx_atux_pmmr_offset + 0x6)
238 #define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
239 #define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
240 #define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
241 #define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
242 #define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
243 #define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
244 #define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
245 #define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
246 #define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
247 #define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
248 #define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
249 #define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
250 #define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
251 #define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
252 #define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
253 #define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
254 #define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
255 #define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
256 #define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
257 #define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
258 #define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
259 #define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
260 #define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
261 #define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
263 #define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
264 #define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
265 #define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
266 #define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
267 #define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
268 #define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
269 #define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
270 #define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
271 #define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
272 #define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
273 #define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
274 #define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
275 #define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
276 #define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
278 #define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
279 #define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
280 #define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
281 #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
282 #define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
283 #define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
285 #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
286 #define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
287 #define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
288 #define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
289 #define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
290 #define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
291 #define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
292 #define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
293 #define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
294 #define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
295 #define IOP13XX_ATUX_STAT_BIST (1 << 8 )
296 #define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
297 #define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
298 #define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
299 #define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
300 #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
301 #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
303 #define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
304 #define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
305 #define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
307 #define IOP13XX_ATUX_IALR_DISABLE 0x00000001
308 #define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
310 #define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
311 iop13xx_atue_pmmr_offset + (ofs))
313 #define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
314 iop13xx_atue_pmmr_offset + 0x2)
315 #define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
316 iop13xx_atue_pmmr_offset + 0x4)
317 #define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
318 iop13xx_atue_pmmr_offset + 0x6)
320 #define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
321 #define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
322 #define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
323 #define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
324 #define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
325 #define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
326 #define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
327 #define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
328 #define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
329 #define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
330 #define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
331 #define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
332 #define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
333 #define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
334 #define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
335 #define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
336 iop13xx_atue_pmmr_offset + 0xe2)
337 #define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
338 #define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
339 #define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
340 #define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
341 #define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
342 #define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
343 #define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
344 #define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
345 #define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
347 #define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
348 #define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
349 #define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
350 #define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
351 #define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
352 #define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
354 #define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
355 #define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
357 #define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
358 #define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
359 #define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
360 #define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
361 #define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
362 #define IOP13XX_ATUE_OCCAR_EXT_REG (8)
363 #define IOP13XX_ATUE_OCCAR_REG (2)
365 #define IOP13XX_ATUE_PCSR_BUS_NUM (24)
366 #define IOP13XX_ATUE_PCSR_DEV_NUM (19)
367 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
368 #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
369 #define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
370 #define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
371 #define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
373 #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
374 #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
375 #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
377 #define IOP13XX_ATUE_PCSR_CORE_RESET (8)
378 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
380 #define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
381 #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
382 #define IOP13XX_ATUE_STAT_PME (1 << 27)
383 #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
384 #define IOP13XX_ATUE_STAT_IVM (1 << 25)
385 #define IOP13XX_ATUE_STAT_BIST (1 << 24)
386 #define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
387 #define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
388 #define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
389 #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
390 #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
391 #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
392 #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
393 #define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
394 #define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
395 #define IOP13XX_ATUE_STAT_CRS (1 << 7 )
396 #define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
397 #define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
398 #define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
399 #define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
400 #define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
401 #define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
402 #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
404 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
405 #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
406 #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
407 #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
408 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
409 #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
410 #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
411 #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
412 #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
413 #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
414 #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
415 #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
416 #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
417 #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
418 #define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
420 #define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
421 #define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
422 #define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
423 #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
424 /*=======================================================================*/
426 /*============================MESSAGING UNIT=============================*/
427 #define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
430 #define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
431 #define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
432 #define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
433 #define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
434 #define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
435 #define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
436 #define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
437 #define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
438 #define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
439 #define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
440 #define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
441 #define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
442 #define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
443 #define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
444 #define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
445 #define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
447 #define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
448 #define IOP13XX_MU_BASE_PHYS (0xff000000)
449 #define IOP13XX_MU_BASE_PCI (0xff000000)
450 #define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
451 #define IOP13XX_MU_MIMR_CORE_SELECT (15)
452 /*=======================================================================*/
454 /*==============================ADMA UNITS===============================*/
455 #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
456 #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
458 /*==============================XSI BRIDGE===============================*/
459 #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
460 #define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
461 #define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
462 #define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
463 IOP13XX_PMMR_VIRT_TO_PHYS(\
464 IOP13XX_ATUE_OCCDR))\
465 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
466 #define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
467 IOP13XX_PMMR_VIRT_TO_PHYS(\
468 IOP13XX_ATUX_OCCDR))\
469 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
470 /*=======================================================================*/
472 #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
475 #define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
476 #define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
477 #define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
478 #define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
479 #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
480 #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
482 #define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
483 #endif /* _IOP13XX_HW_H_ */