drivers/video/sh_mobile_hdmi.c

   1 /*
   2  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
   3  * for SLISHDMI13T and SLIPHDMIT IP cores
   4  *
   5  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/soc-dapm.h>
  26 #include <sound/initval.h>
  27
  28 #include <video/sh_mobile_hdmi.h>
  29 #include <video/sh_mobile_lcdc.h>
  30
  31 #define HDMI_SYSTEM_CTRL                        0x00 /* System control */
  32 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT            0x01 /* L/R data swap control,
  33                                                         bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  34 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8       0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  35 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0        0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  36 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS          0x04 /* SPDIF audio sampling frequency,
  37                                                         bits 19..16 of Internal CTS */
  38 #define HDMI_INTERNAL_CTS_15_8                  0x05 /* bits 15..8 of Internal CTS */
  39 #define HDMI_INTERNAL_CTS_7_0                   0x06 /* bits 7..0 of Internal CTS */
  40 #define HDMI_EXTERNAL_CTS_19_16                 0x07 /* External CTS */
  41 #define HDMI_EXTERNAL_CTS_15_8                  0x08 /* External CTS */
  42 #define HDMI_EXTERNAL_CTS_7_0                   0x09 /* External CTS */
  43 #define HDMI_AUDIO_SETTING_1                    0x0A /* Audio setting.1 */
  44 #define HDMI_AUDIO_SETTING_2                    0x0B /* Audio setting.2 */
  45 #define HDMI_I2S_AUDIO_SET                      0x0C /* I2S audio setting */
  46 #define HDMI_DSD_AUDIO_SET                      0x0D /* DSD audio setting */
  47 #define HDMI_DEBUG_MONITOR_1                    0x0E /* Debug monitor.1 */
  48 #define HDMI_DEBUG_MONITOR_2                    0x0F /* Debug monitor.2 */
  49 #define HDMI_I2S_INPUT_PIN_SWAP                 0x10 /* I2S input pin swap */
  50 #define HDMI_AUDIO_STATUS_BITS_SETTING_1        0x11 /* Audio status bits setting.1 */
  51 #define HDMI_AUDIO_STATUS_BITS_SETTING_2        0x12 /* Audio status bits setting.2 */
  52 #define HDMI_CATEGORY_CODE                      0x13 /* Category code */
  53 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN          0x14 /* Source number/Audio word length */
  54 #define HDMI_AUDIO_VIDEO_SETTING_1              0x15 /* Audio/Video setting.1 */
  55 #define HDMI_VIDEO_SETTING_1                    0x16 /* Video setting.1 */
  56 #define HDMI_DEEP_COLOR_MODES                   0x17 /* Deep Color Modes */
  57
  58 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  59 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS  0x18
  60
  61 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS      0x30 /* External video parameter settings */
  62 #define HDMI_EXTERNAL_H_TOTAL_7_0               0x31 /* External horizontal total (LSB) */
  63 #define HDMI_EXTERNAL_H_TOTAL_11_8              0x32 /* External horizontal total (MSB) */
  64 #define HDMI_EXTERNAL_H_BLANK_7_0               0x33 /* External horizontal blank (LSB) */
  65 #define HDMI_EXTERNAL_H_BLANK_9_8               0x34 /* External horizontal blank (MSB) */
  66 #define HDMI_EXTERNAL_H_DELAY_7_0               0x35 /* External horizontal delay (LSB) */
  67 #define HDMI_EXTERNAL_H_DELAY_9_8               0x36 /* External horizontal delay (MSB) */
  68 #define HDMI_EXTERNAL_H_DURATION_7_0            0x37 /* External horizontal duration (LSB) */
  69 #define HDMI_EXTERNAL_H_DURATION_9_8            0x38 /* External horizontal duration (MSB) */
  70 #define HDMI_EXTERNAL_V_TOTAL_7_0               0x39 /* External vertical total (LSB) */
  71 #define HDMI_EXTERNAL_V_TOTAL_9_8               0x3A /* External vertical total (MSB) */
  72 #define HDMI_AUDIO_VIDEO_SETTING_2              0x3B /* Audio/Video setting.2 */
  73 #define HDMI_EXTERNAL_V_BLANK                   0x3D /* External vertical blank */
  74 #define HDMI_EXTERNAL_V_DELAY                   0x3E /* External vertical delay */
  75 #define HDMI_EXTERNAL_V_DURATION                0x3F /* External vertical duration */
  76 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL       0x40 /* Control packet manual send control */
  77 #define HDMI_CTRL_PKT_AUTO_SEND                 0x41 /* Control packet auto send with VSYNC control */
  78 #define HDMI_AUTO_CHECKSUM_OPTION               0x42 /* Auto checksum option */
  79 #define HDMI_VIDEO_SETTING_2                    0x45 /* Video setting.2 */
  80 #define HDMI_OUTPUT_OPTION                      0x46 /* Output option */
  81 #define HDMI_SLIPHDMIT_PARAM_OPTION             0x51 /* SLIPHDMIT parameter option */
  82 #define HDMI_HSYNC_PMENT_AT_EMB_7_0             0x52 /* HSYNC placement at embedded sync (LSB) */
  83 #define HDMI_HSYNC_PMENT_AT_EMB_15_8            0x53 /* HSYNC placement at embedded sync (MSB) */
  84 #define HDMI_VSYNC_PMENT_AT_EMB_7_0             0x54 /* VSYNC placement at embedded sync (LSB) */
  85 #define HDMI_VSYNC_PMENT_AT_EMB_14_8            0x55 /* VSYNC placement at embedded sync (MSB) */
  86 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1         0x56 /* SLIPHDMIT parameter settings.1 */
  87 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2         0x57 /* SLIPHDMIT parameter settings.2 */
  88 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3         0x58 /* SLIPHDMIT parameter settings.3 */
  89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5         0x59 /* SLIPHDMIT parameter settings.5 */
  90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6         0x5A /* SLIPHDMIT parameter settings.6 */
  91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7         0x5B /* SLIPHDMIT parameter settings.7 */
  92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8         0x5C /* SLIPHDMIT parameter settings.8 */
  93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9         0x5D /* SLIPHDMIT parameter settings.9 */
  94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10        0x5E /* SLIPHDMIT parameter settings.10 */
  95 #define HDMI_CTRL_PKT_BUF_INDEX                 0x5F /* Control packet buffer index */
  96 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0            0x60 /* Control packet data buffer access window - HB0 */
  97 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1            0x61 /* Control packet data buffer access window - HB1 */
  98 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2            0x62 /* Control packet data buffer access window - HB2 */
  99 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0            0x63 /* Control packet data buffer access window - PB0 */
 100 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1            0x64 /* Control packet data buffer access window - PB1 */
 101 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2            0x65 /* Control packet data buffer access window - PB2 */
 102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3            0x66 /* Control packet data buffer access window - PB3 */
 103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4            0x67 /* Control packet data buffer access window - PB4 */
 104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5            0x68 /* Control packet data buffer access window - PB5 */
 105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6            0x69 /* Control packet data buffer access window - PB6 */
 106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7            0x6A /* Control packet data buffer access window - PB7 */
 107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8            0x6B /* Control packet data buffer access window - PB8 */
 108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9            0x6C /* Control packet data buffer access window - PB9 */
 109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10           0x6D /* Control packet data buffer access window - PB10 */
 110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11           0x6E /* Control packet data buffer access window - PB11 */
 111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12           0x6F /* Control packet data buffer access window - PB12 */
 112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13           0x70 /* Control packet data buffer access window - PB13 */
 113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14           0x71 /* Control packet data buffer access window - PB14 */
 114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15           0x72 /* Control packet data buffer access window - PB15 */
 115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16           0x73 /* Control packet data buffer access window - PB16 */
 116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17           0x74 /* Control packet data buffer access window - PB17 */
 117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18           0x75 /* Control packet data buffer access window - PB18 */
 118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19           0x76 /* Control packet data buffer access window - PB19 */
 119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20           0x77 /* Control packet data buffer access window - PB20 */
 120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21           0x78 /* Control packet data buffer access window - PB21 */
 121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22           0x79 /* Control packet data buffer access window - PB22 */
 122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23           0x7A /* Control packet data buffer access window - PB23 */
 123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24           0x7B /* Control packet data buffer access window - PB24 */
 124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25           0x7C /* Control packet data buffer access window - PB25 */
 125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26           0x7D /* Control packet data buffer access window - PB26 */
 126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27           0x7E /* Control packet data buffer access window - PB27 */
 127 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW        0x80 /* EDID/KSV FIFO access window */
 128 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0       0x81 /* DDC bus access frequency control (LSB) */
 129 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8      0x82 /* DDC bus access frequency control (MSB) */
 130 #define HDMI_INTERRUPT_MASK_1                   0x92 /* Interrupt mask.1 */
 131 #define HDMI_INTERRUPT_MASK_2                   0x93 /* Interrupt mask.2 */
 132 #define HDMI_INTERRUPT_STATUS_1                 0x94 /* Interrupt status.1 */
 133 #define HDMI_INTERRUPT_STATUS_2                 0x95 /* Interrupt status.2 */
 134 #define HDMI_INTERRUPT_MASK_3                   0x96 /* Interrupt mask.3 */
 135 #define HDMI_INTERRUPT_MASK_4                   0x97 /* Interrupt mask.4 */
 136 #define HDMI_INTERRUPT_STATUS_3                 0x98 /* Interrupt status.3 */
 137 #define HDMI_INTERRUPT_STATUS_4                 0x99 /* Interrupt status.4 */
 138 #define HDMI_SOFTWARE_HDCP_CONTROL_1            0x9A /* Software HDCP control.1 */
 139 #define HDMI_FRAME_COUNTER                      0x9C /* Frame counter */
 140 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK         0x9D /* Frame counter for Ri check */
 141 #define HDMI_HDCP_CONTROL                       0xAF /* HDCP control */
 142 #define HDMI_RI_FRAME_COUNT_REGISTER            0xB2 /* Ri frame count register */
 143 #define HDMI_DDC_BUS_CONTROL                    0xB7 /* DDC bus control */
 144 #define HDMI_HDCP_STATUS                        0xB8 /* HDCP status */
 145 #define HDMI_SHA0                               0xB9 /* sha0 */
 146 #define HDMI_SHA1                               0xBA /* sha1 */
 147 #define HDMI_SHA2                               0xBB /* sha2 */
 148 #define HDMI_SHA3                               0xBC /* sha3 */
 149 #define HDMI_SHA4                               0xBD /* sha4 */
 150 #define HDMI_BCAPS_READ                         0xBE /* BCAPS read / debug */
 151 #define HDMI_AKSV_BKSV_7_0_MONITOR              0xBF /* AKSV/BKSV[7:0] monitor */
 152 #define HDMI_AKSV_BKSV_15_8_MONITOR             0xC0 /* AKSV/BKSV[15:8] monitor */
 153 #define HDMI_AKSV_BKSV_23_16_MONITOR            0xC1 /* AKSV/BKSV[23:16] monitor */
 154 #define HDMI_AKSV_BKSV_31_24_MONITOR            0xC2 /* AKSV/BKSV[31:24] monitor */
 155 #define HDMI_AKSV_BKSV_39_32_MONITOR            0xC3 /* AKSV/BKSV[39:32] monitor */
 156 #define HDMI_EDID_SEGMENT_POINTER               0xC4 /* EDID segment pointer */
 157 #define HDMI_EDID_WORD_ADDRESS                  0xC5 /* EDID word address */
 158 #define HDMI_EDID_DATA_FIFO_ADDRESS             0xC6 /* EDID data FIFO address */
 159 #define HDMI_NUM_OF_HDMI_DEVICES                0xC7 /* Number of HDMI devices */
 160 #define HDMI_HDCP_ERROR_CODE                    0xC8 /* HDCP error code */
 161 #define HDMI_100MS_TIMER_SET                    0xC9 /* 100ms timer setting */
 162 #define HDMI_5SEC_TIMER_SET                     0xCA /* 5sec timer setting */
 163 #define HDMI_RI_READ_COUNT                      0xCB /* Ri read count */
 164 #define HDMI_AN_SEED                            0xCC /* An seed */
 165 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED          0xCD /* Maximum number of receivers allowed */
 166 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1       0xCE /* HDCP memory access control.1 */
 167 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2       0xCF /* HDCP memory access control.2 */
 168 #define HDMI_HDCP_CONTROL_2                     0xD0 /* HDCP Control 2 */
 169 #define HDMI_HDCP_KEY_MEMORY_CONTROL            0xD2 /* HDCP Key Memory Control */
 170 #define HDMI_COLOR_SPACE_CONV_CONFIG_1          0xD3 /* Color space conversion configuration.1 */
 171 #define HDMI_VIDEO_SETTING_3                    0xD4 /* Video setting.3 */
 172 #define HDMI_RI_7_0                             0xD5 /* Ri[7:0] */
 173 #define HDMI_RI_15_8                            0xD6 /* Ri[15:8] */
 174 #define HDMI_PJ                                 0xD7 /* Pj */
 175 #define HDMI_SHA_RD                             0xD8 /* sha_rd */
 176 #define HDMI_RI_7_0_SAVED                       0xD9 /* Ri[7:0] saved */
 177 #define HDMI_RI_15_8_SAVED                      0xDA /* Ri[15:8] saved */
 178 #define HDMI_PJ_SAVED                           0xDB /* Pj saved */
 179 #define HDMI_NUM_OF_DEVICES                     0xDC /* Number of devices */
 180 #define HDMI_HOT_PLUG_MSENS_STATUS              0xDF /* Hot plug/MSENS status */
 181 #define HDMI_BCAPS_WRITE                        0xE0 /* bcaps */
 182 #define HDMI_BSTAT_7_0                          0xE1 /* bstat[7:0] */
 183 #define HDMI_BSTAT_15_8                         0xE2 /* bstat[15:8] */
 184 #define HDMI_BKSV_7_0                           0xE3 /* bksv[7:0] */
 185 #define HDMI_BKSV_15_8                          0xE4 /* bksv[15:8] */
 186 #define HDMI_BKSV_23_16                         0xE5 /* bksv[23:16] */
 187 #define HDMI_BKSV_31_24                         0xE6 /* bksv[31:24] */
 188 #define HDMI_BKSV_39_32                         0xE7 /* bksv[39:32] */
 189 #define HDMI_AN_7_0                             0xE8 /* An[7:0] */
 190 #define HDMI_AN_15_8                            0xE9 /* An [15:8] */
 191 #define HDMI_AN_23_16                           0xEA /* An [23:16] */
 192 #define HDMI_AN_31_24                           0xEB /* An [31:24] */
 193 #define HDMI_AN_39_32                           0xEC /* An [39:32] */
 194 #define HDMI_AN_47_40                           0xED /* An [47:40] */
 195 #define HDMI_AN_55_48                           0xEE /* An [55:48] */
 196 #define HDMI_AN_63_56                           0xEF /* An [63:56] */
 197 #define HDMI_PRODUCT_ID                         0xF0 /* Product ID */
 198 #define HDMI_REVISION_ID                        0xF1 /* Revision ID */
 199 #define HDMI_TEST_MODE                          0xFE /* Test mode */
 200
 201 enum hotplug_state {
 202         HDMI_HOTPLUG_DISCONNECTED,
 203         HDMI_HOTPLUG_CONNECTED,
 204         HDMI_HOTPLUG_EDID_DONE,
 205 };
 206
 207 struct sh_hdmi {
 208         void __iomem *base;
 209         enum hotplug_state hp_state;
 210         struct clk *hdmi_clk;
 211         struct device *dev;
 212         struct fb_info *info;
 213         struct delayed_work edid_work;
 214         struct fb_var_screeninfo var;
 215 };
 216
 217 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
 218 {
 219         iowrite8(data, hdmi->base + reg);
 220 }
 221
 222 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
 223 {
 224         return ioread8(hdmi->base + reg);
 225 }
 226
 227 /************************************************************************
 228
 229
 230                         HDMI sound
 231
 232
 233 ************************************************************************/
 234 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
 235                                      unsigned int reg)
 236 {
 237         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 238
 239         return hdmi_read(hdmi, reg);
 240 }
 241
 242 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
 243                              unsigned int reg,
 244                              unsigned int value)
 245 {
 246         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 247
 248         hdmi_write(hdmi, value, reg);
 249         return 0;
 250 }
 251
 252 static struct snd_soc_dai_driver sh_hdmi_dai = {
 253         .name = "sh_mobile_hdmi-hifi",
 254         .playback = {
 255                 .stream_name = "Playback",
 256                 .channels_min = 1,
 257                 .channels_max = 2,
 258                 .rates = SNDRV_PCM_RATE_8000_48000,
 259                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 260         },
 261 };
 262
 263 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
 264 {
 265         dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
 266
 267         return 0;
 268 }
 269
 270 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
 271         .probe          = sh_hdmi_snd_probe,
 272         .read           = sh_hdmi_snd_read,
 273         .write          = sh_hdmi_snd_write,
 274 };
 275
 276 /************************************************************************
 277
 278
 279                         HDMI video
 280
 281
 282 ************************************************************************/
 283 /* External video parameter settings */
 284 static void hdmi_external_video_param(struct sh_hdmi *hdmi)
 285 {
 286         struct fb_var_screeninfo *var = &hdmi->var;
 287         u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
 288         u8 sync = 0;
 289
 290         htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
 291
 292         hdelay = var->hsync_len + var->left_margin;
 293         hblank = var->right_margin + hdelay;
 294
 295         /*
 296          * Vertical timing looks a bit different in Figure 18,
 297          * but let's try the same first by setting offset = 0
 298          */
 299         vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
 300
 301         vdelay = var->vsync_len + var->upper_margin;
 302         vblank = var->lower_margin + vdelay;
 303         voffset = min(var->upper_margin / 2, 6U);
 304
 305         /*
 306          * [3]: VSYNC polarity: Positive
 307          * [2]: HSYNC polarity: Positive
 308          * [1]: Interlace/Progressive: Progressive
 309          * [0]: External video settings enable: used.
 310          */
 311         if (var->sync & FB_SYNC_HOR_HIGH_ACT)
 312                 sync |= 4;
 313         if (var->sync & FB_SYNC_VERT_HIGH_ACT)
 314                 sync |= 8;
 315
 316         pr_debug("H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
 317                  htotal, hblank, hdelay, var->hsync_len,
 318                  vtotal, vblank, vdelay, var->vsync_len, sync);
 319
 320         hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 321
 322         hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
 323         hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
 324
 325         hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
 326         hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
 327
 328         hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
 329         hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
 330
 331         hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
 332         hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
 333
 334         hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
 335         hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
 336
 337         hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
 338
 339         hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
 340
 341         hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
 342
 343         /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for manual mode */
 344 }
 345
 346 /**
 347  * sh_hdmi_video_config()
 348  */
 349 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
 350 {
 351         /*
 352          * [7:4]: Audio sampling frequency: 48kHz
 353          * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
 354          * [0]: Internal/External DE select: internal
 355          */
 356         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 357
 358         /*
 359          * [7:6]: Video output format: RGB 4:4:4
 360          * [5:4]: Input video data width: 8 bit
 361          * [3:1]: EAV/SAV location: channel 1
 362          * [0]: Video input color space: RGB
 363          */
 364         hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
 365
 366         /*
 367          * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
 368          * left at 0 by default, this configures 24bpp and sets the Color Depth
 369          * (CD) field in the General Control Packet
 370          */
 371         hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
 372 }
 373
 374 /**
 375  * sh_hdmi_audio_config()
 376  */
 377 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
 378 {
 379         u8 data;
 380         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 381
 382         /*
 383          * [7:4] L/R data swap control
 384          * [3:0] appropriate N[19:16]
 385          */
 386         hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
 387         /* appropriate N[15:8] */
 388         hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
 389         /* appropriate N[7:0] */
 390         hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
 391
 392         /* [7:4] 48 kHz SPDIF not used */
 393         hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
 394
 395         /*
 396          * [6:5] set required down sampling rate if required
 397          * [4:3] set required audio source
 398          */
 399         switch (pdata->flags & HDMI_SRC_MASK) {
 400         default:
 401                 /* FALL THROUGH */
 402         case HDMI_SRC_I2S:
 403                 data = (0x0 << 3);
 404                 break;
 405         case HDMI_SRC_SPDIF:
 406                 data = (0x1 << 3);
 407                 break;
 408         case HDMI_SRC_DSD:
 409                 data = (0x2 << 3);
 410                 break;
 411         case HDMI_SRC_HBR:
 412                 data = (0x3 << 3);
 413                 break;
 414         }
 415         hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
 416
 417         /* [3:0] set sending channel number for channel status */
 418         hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
 419
 420         /*
 421          * [5:2] set valid I2S source input pin
 422          * [1:0] set input I2S source mode
 423          */
 424         hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
 425
 426         /* [7:4] set valid DSD source input pin */
 427         hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
 428
 429         /* [7:0] set appropriate I2S input pin swap settings if required */
 430         hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
 431
 432         /*
 433          * [7] set validity bit for channel status
 434          * [3:0] set original sample frequency for channel status
 435          */
 436         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
 437
 438         /*
 439          * [7] set value for channel status
 440          * [6] set value for channel status
 441          * [5] set copyright bit for channel status
 442          * [4:2] set additional information for channel status
 443          * [1:0] set clock accuracy for channel status
 444          */
 445         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
 446
 447         /* [7:0] set category code for channel status */
 448         hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
 449
 450         /*
 451          * [7:4] set source number for channel status
 452          * [3:0] set word length for channel status
 453          */
 454         hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
 455
 456         /* [7:4] set sample frequency for channel status */
 457         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 458 }
 459
 460 /**
 461  * sh_hdmi_phy_config()
 462  */
 463 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
 464 {
 465         /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
 466         hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 467         hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 468         hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 469         /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
 470         hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 471         hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 472         hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 473         hdmi_write(hdmi, 0x0E, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 474         hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 475         hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 476 }
 477
 478 /**
 479  * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
 480  */
 481 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
 482 {
 483         /* AVI InfoFrame */
 484         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
 485
 486         /* Packet Type = 0x82 */
 487         hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 488
 489         /* Version = 0x02 */
 490         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 491
 492         /* Length = 13 (0x0D) */
 493         hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 494
 495         /* N. A. Checksum */
 496         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 497
 498         /*
 499          * Y = RGB
 500          * A0 = No Data
 501          * B = Bar Data not valid
 502          * S = No Data
 503          */
 504         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 505
 506         /*
 507          * C = No Data
 508          * M = 16:9 Picture Aspect Ratio
 509          * R = Same as picture aspect ratio
 510          */
 511         hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 512
 513         /*
 514          * ITC = No Data
 515          * EC = xvYCC601
 516          * Q = Default (depends on video format)
 517          * SC = No Known non_uniform Scaling
 518          */
 519         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 520
 521         /*
 522          * VIC = 1280 x 720p: ignored if external config is used
 523          * Send 2 for 720 x 480p, 16 for 1080p
 524          */
 525         hdmi_write(hdmi, 4, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 526
 527         /* PR = No Repetition */
 528         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 529
 530         /* Line Number of End of Top Bar (lower 8 bits) */
 531         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 532
 533         /* Line Number of End of Top Bar (upper 8 bits) */
 534         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 535
 536         /* Line Number of Start of Bottom Bar (lower 8 bits) */
 537         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 538
 539         /* Line Number of Start of Bottom Bar (upper 8 bits) */
 540         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 541
 542         /* Pixel Number of End of Left Bar (lower 8 bits) */
 543         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 544
 545         /* Pixel Number of End of Left Bar (upper 8 bits) */
 546         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
 547
 548         /* Pixel Number of Start of Right Bar (lower 8 bits) */
 549         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
 550
 551         /* Pixel Number of Start of Right Bar (upper 8 bits) */
 552         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
 553 }
 554
 555 /**
 556  * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
 557  */
 558 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
 559 {
 560         /* Audio InfoFrame */
 561         hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
 562
 563         /* Packet Type = 0x84 */
 564         hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 565
 566         /* Version Number = 0x01 */
 567         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 568
 569         /* 0 Length = 10 (0x0A) */
 570         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 571
 572         /* n. a. Checksum */
 573         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 574
 575         /* Audio Channel Count = Refer to Stream Header */
 576         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 577
 578         /* Refer to Stream Header */
 579         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 580
 581         /* Format depends on coding type (i.e. CT0...CT3) */
 582         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 583
 584         /* Speaker Channel Allocation = Front Right + Front Left */
 585         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 586
 587         /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
 588         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 589
 590         /* Reserved (0) */
 591         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 592         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 593         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 594         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 595         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 596 }
 597
 598 /**
 599  * sh_hdmi_gamut_metadata_setup() - Gamut Metadata Packet of CONTROL PACKET
 600  */
 601 static void sh_hdmi_gamut_metadata_setup(struct sh_hdmi *hdmi)
 602 {
 603         int i;
 604
 605         /* Gamut Metadata Packet */
 606         hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_INDEX);
 607
 608         /* Packet Type = 0x0A */
 609         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 610         /* Gamut Packet is not used, so default value */
 611         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 612         /* Gamut Packet is not used, so default value */
 613         hdmi_write(hdmi, 0x10, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 614
 615         /* GBD bytes 0 through 27 */
 616         for (i = 0; i <= 27; i++)
 617                 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0_63H - PB27_7EH */
 618                 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
 619 }
 620
 621 /**
 622  * sh_hdmi_acp_setup() - Audio Content Protection Packet (ACP)
 623  */
 624 static void sh_hdmi_acp_setup(struct sh_hdmi *hdmi)
 625 {
 626         int i;
 627
 628         /* Audio Content Protection Packet (ACP) */
 629         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_INDEX);
 630
 631         /* Packet Type = 0x04 */
 632         hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 633         /* ACP_Type */
 634         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 635         /* Reserved (0) */
 636         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 637
 638         /* GBD bytes 0 through 27 */
 639         for (i = 0; i <= 27; i++)
 640                 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
 641                 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
 642 }
 643
 644 /**
 645  * sh_hdmi_isrc1_setup() - ISRC1 Packet
 646  */
 647 static void sh_hdmi_isrc1_setup(struct sh_hdmi *hdmi)
 648 {
 649         int i;
 650
 651         /* ISRC1 Packet */
 652         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_INDEX);
 653
 654         /* Packet Type = 0x05 */
 655         hdmi_write(hdmi, 0x05, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 656         /* ISRC_Cont, ISRC_Valid, Reserved (0), ISRC_Status */
 657         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 658         /* Reserved (0) */
 659         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 660
 661         /* PB0 UPC_EAN_ISRC_0-15 */
 662         /* Bytes PB16-PB27 shall be set to a value of 0. */
 663         for (i = 0; i <= 27; i++)
 664                 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
 665                 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
 666 }
 667
 668 /**
 669  * sh_hdmi_isrc2_setup() - ISRC2 Packet
 670  */
 671 static void sh_hdmi_isrc2_setup(struct sh_hdmi *hdmi)
 672 {
 673         int i;
 674
 675         /* ISRC2 Packet */
 676         hdmi_write(hdmi, 0x03, HDMI_CTRL_PKT_BUF_INDEX);
 677
 678         /* HB0 Packet Type = 0x06 */
 679         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 680         /* Reserved (0) */
 681         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 682         /* Reserved (0) */
 683         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 684
 685         /* PB0 UPC_EAN_ISRC_16-31 */
 686         /* Bytes PB16-PB27 shall be set to a value of 0. */
 687         for (i = 0; i <= 27; i++)
 688                 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
 689                 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
 690 }
 691
 692 /**
 693  * sh_hdmi_configure() - Initialise HDMI for output
 694  */
 695 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
 696 {
 697         /* Configure video format */
 698         sh_hdmi_video_config(hdmi);
 699
 700         /* Configure audio format */
 701         sh_hdmi_audio_config(hdmi);
 702
 703         /* Configure PHY */
 704         sh_hdmi_phy_config(hdmi);
 705
 706         /* Auxiliary Video Information (AVI) InfoFrame */
 707         sh_hdmi_avi_infoframe_setup(hdmi);
 708
 709         /* Audio InfoFrame */
 710         sh_hdmi_audio_infoframe_setup(hdmi);
 711
 712         /* Gamut Metadata packet */
 713         sh_hdmi_gamut_metadata_setup(hdmi);
 714
 715         /* Audio Content Protection (ACP) Packet */
 716         sh_hdmi_acp_setup(hdmi);
 717
 718         /* ISRC1 Packet */
 719         sh_hdmi_isrc1_setup(hdmi);
 720
 721         /* ISRC2 Packet */
 722         sh_hdmi_isrc2_setup(hdmi);
 723
 724         /*
 725          * Control packet auto send with VSYNC control: auto send
 726          * General control, Gamut metadata, ISRC, and ACP packets
 727          */
 728         hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
 729
 730         /* FIXME */
 731         msleep(10);
 732
 733         /* PS mode b->d, reset PLLA and PLLB */
 734         hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
 735
 736         udelay(10);
 737
 738         hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
 739 }
 740
 741 static void sh_hdmi_read_edid(struct sh_hdmi *hdmi)
 742 {
 743         struct fb_var_screeninfo *var = &hdmi->var;
 744         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 745         struct fb_videomode *lcd_cfg = &pdata->lcd_chan->lcd_cfg;
 746         unsigned long height = var->height, width = var->width;
 747         int i;
 748         u8 edid[128];
 749
 750         /* Read EDID */
 751         pr_debug("Read back EDID code:");
 752         for (i = 0; i < 128; i++) {
 753                 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
 754 #ifdef DEBUG
 755                 if ((i % 16) == 0) {
 756                         printk(KERN_CONT "\n");
 757                         printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
 758                 } else {
 759                         printk(KERN_CONT " %02X", edid[i]);
 760                 }
 761 #endif
 762         }
 763 #ifdef DEBUG
 764         printk(KERN_CONT "\n");
 765 #endif
 766         fb_parse_edid(edid, var);
 767         pr_debug("%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n",
 768                  var->left_margin, var->xres, var->right_margin, var->hsync_len,
 769                  var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
 770                  PICOS2KHZ(var->pixclock));
 771
 772         /* FIXME: Use user-provided configuration instead of EDID */
 773         var->width              = width;
 774         var->xres               = lcd_cfg->xres;
 775         var->xres_virtual       = lcd_cfg->xres;
 776         var->left_margin        = lcd_cfg->left_margin;
 777         var->right_margin       = lcd_cfg->right_margin;
 778         var->hsync_len          = lcd_cfg->hsync_len;
 779         var->height             = height;
 780         var->yres               = lcd_cfg->yres;
 781         var->yres_virtual       = lcd_cfg->yres * 2;
 782         var->upper_margin       = lcd_cfg->upper_margin;
 783         var->lower_margin       = lcd_cfg->lower_margin;
 784         var->vsync_len          = lcd_cfg->vsync_len;
 785         var->sync               = lcd_cfg->sync;
 786         var->pixclock           = lcd_cfg->pixclock;
 787
 788         hdmi_external_video_param(hdmi);
 789 }
 790
 791 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
 792 {
 793         struct sh_hdmi *hdmi = dev_id;
 794         u8 status1, status2, mask1, mask2;
 795
 796         /* mode_b and PLLA and PLLB reset */
 797         hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
 798
 799         /* How long shall reset be held? */
 800         udelay(10);
 801
 802         /* mode_b and PLLA and PLLB reset release */
 803         hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
 804
 805         status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
 806         status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
 807
 808         mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
 809         mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
 810
 811         /* Correct would be to ack only set bits, but the datasheet requires 0xff */
 812         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
 813         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
 814
 815         if (printk_ratelimit())
 816                 pr_debug("IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
 817                          irq, status1, mask1, status2, mask2);
 818
 819         if (!((status1 & mask1) | (status2 & mask2))) {
 820                 return IRQ_NONE;
 821         } else if (status1 & 0xc0) {
 822                 u8 msens;
 823
 824                 /* Datasheet specifies 10ms... */
 825                 udelay(500);
 826
 827                 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
 828                 pr_debug("MSENS 0x%x\n", msens);
 829                 /* Check, if hot plug & MSENS pin status are both high */
 830                 if ((msens & 0xC0) == 0xC0) {
 831                         /* Display plug in */
 832                         hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
 833
 834                         /* Set EDID word address  */
 835                         hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 836                         /* Set EDID segment pointer */
 837                         hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 838                         /* Enable EDID interrupt */
 839                         hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 840                 } else if (!(status1 & 0x80)) {
 841                         /* Display unplug, beware multiple interrupts */
 842                         if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
 843                                 schedule_delayed_work(&hdmi->edid_work, 0);
 844
 845                         hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
 846                         /* display_off will switch back to mode_a */
 847                 }
 848         } else if (status1 & 2) {
 849                 /* EDID error interrupt: retry */
 850                 /* Set EDID word address  */
 851                 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 852                 /* Set EDID segment pointer */
 853                 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 854         } else if (status1 & 4) {
 855                 /* Disable EDID interrupt */
 856                 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
 857                 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
 858                 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
 859         }
 860
 861         return IRQ_HANDLED;
 862 }
 863
 864 static void hdmi_display_on(void *arg, struct fb_info *info)
 865 {
 866         struct sh_hdmi *hdmi = arg;
 867         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 868
 869         if (info->var.xres != 1280 || info->var.yres != 720) {
 870                 dev_warn(info->device, "Unsupported framebuffer geometry %ux%u\n",
 871                          info->var.xres, info->var.yres);
 872                 return;
 873         }
 874
 875         pr_debug("%s(%p): state %x\n", __func__, pdata->lcd_dev, info->state);
 876         /*
 877          * FIXME: not a good place to store fb_info. And we cannot nullify it
 878          * even on monitor disconnect. What should the lifecycle be?
 879          */
 880         hdmi->info = info;
 881         switch (hdmi->hp_state) {
 882         case HDMI_HOTPLUG_EDID_DONE:
 883                 /* PS mode d->e. All functions are active */
 884                 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
 885                 pr_debug("HDMI running\n");
 886                 break;
 887         case HDMI_HOTPLUG_DISCONNECTED:
 888                 info->state = FBINFO_STATE_SUSPENDED;
 889         default:
 890                 hdmi->var = info->var;
 891         }
 892 }
 893
 894 static void hdmi_display_off(void *arg)
 895 {
 896         struct sh_hdmi *hdmi = arg;
 897         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 898
 899         pr_debug("%s(%p)\n", __func__, pdata->lcd_dev);
 900         /* PS mode e->a */
 901         hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
 902 }
 903
 904 /* Hotplug interrupt occurred, read EDID */
 905 static void edid_work_fn(struct work_struct *work)
 906 {
 907         struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
 908         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 909
 910         pr_debug("%s(%p): begin, hotplug status %d\n", __func__,
 911                  pdata->lcd_dev, hdmi->hp_state);
 912
 913         if (!pdata->lcd_dev)
 914                 return;
 915
 916         if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
 917                 pm_runtime_get_sync(hdmi->dev);
 918                 /* A device has been plugged in */
 919                 sh_hdmi_read_edid(hdmi);
 920                 msleep(10);
 921                 sh_hdmi_configure(hdmi);
 922                 /* Switched to another (d) power-save mode */
 923                 msleep(10);
 924
 925                 if (!hdmi->info)
 926                         return;
 927
 928                 acquire_console_sem();
 929
 930                 /* HDMI plug in */
 931                 hdmi->info->var = hdmi->var;
 932                 if (hdmi->info->state != FBINFO_STATE_RUNNING)
 933                         fb_set_suspend(hdmi->info, 0);
 934                 else
 935                         hdmi_display_on(hdmi, hdmi->info);
 936
 937                 release_console_sem();
 938         } else {
 939                 if (!hdmi->info)
 940                         return;
 941
 942                 acquire_console_sem();
 943
 944                 /* HDMI disconnect */
 945                 fb_set_suspend(hdmi->info, 1);
 946
 947                 release_console_sem();
 948                 pm_runtime_put(hdmi->dev);
 949         }
 950
 951         pr_debug("%s(%p): end\n", __func__, pdata->lcd_dev);
 952 }
 953
 954 static int __init sh_hdmi_probe(struct platform_device *pdev)
 955 {
 956         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
 957         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 958         int irq = platform_get_irq(pdev, 0), ret;
 959         struct sh_hdmi *hdmi;
 960         long rate;
 961
 962         if (!res || !pdata || irq < 0)
 963                 return -ENODEV;
 964
 965         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
 966         if (!hdmi) {
 967                 dev_err(&pdev->dev, "Cannot allocate device data\n");
 968                 return -ENOMEM;
 969         }
 970
 971         ret =  snd_soc_register_codec(&pdev->dev,
 972                         &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
 973         if (ret < 0)
 974                 goto egetclk;
 975
 976         hdmi->dev = &pdev->dev;
 977
 978         hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
 979         if (IS_ERR(hdmi->hdmi_clk)) {
 980                 ret = PTR_ERR(hdmi->hdmi_clk);
 981                 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
 982                 goto egetclk;
 983         }
 984
 985         rate = PICOS2KHZ(pdata->lcd_chan->lcd_cfg.pixclock) * 1000;
 986
 987         rate = clk_round_rate(hdmi->hdmi_clk, rate);
 988         if (rate < 0) {
 989                 ret = rate;
 990                 dev_err(&pdev->dev, "Cannot get suitable rate: %ld\n", rate);
 991                 goto erate;
 992         }
 993
 994         ret = clk_set_rate(hdmi->hdmi_clk, rate);
 995         if (ret < 0) {
 996                 dev_err(&pdev->dev, "Cannot set rate %ld: %d\n", rate, ret);
 997                 goto erate;
 998         }
 999
1000         pr_debug("HDMI set frequency %lu\n", rate);
1001
1002         ret = clk_enable(hdmi->hdmi_clk);
1003         if (ret < 0) {
1004                 dev_err(&pdev->dev, "Cannot enable clock: %d\n", ret);
1005                 goto eclkenable;
1006         }
1007
1008         dev_info(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1009
1010         if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1011                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1012                 ret = -EBUSY;
1013                 goto ereqreg;
1014         }
1015
1016         hdmi->base = ioremap(res->start, resource_size(res));
1017         if (!hdmi->base) {
1018                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1019                 ret = -ENOMEM;
1020                 goto emap;
1021         }
1022
1023         platform_set_drvdata(pdev, hdmi);
1024
1025 #if 1
1026         /* Product and revision IDs are 0 in sh-mobile version */
1027         dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1028                  hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1029 #endif
1030
1031         /* Set up LCDC callbacks */
1032         pdata->lcd_chan->board_cfg.board_data = hdmi;
1033         pdata->lcd_chan->board_cfg.display_on = hdmi_display_on;
1034         pdata->lcd_chan->board_cfg.display_off = hdmi_display_off;
1035
1036         INIT_DELAYED_WORK(&hdmi->edid_work, edid_work_fn);
1037
1038         pm_runtime_enable(&pdev->dev);
1039         pm_runtime_resume(&pdev->dev);
1040
1041         ret = request_irq(irq, sh_hdmi_hotplug, 0,
1042                           dev_name(&pdev->dev), hdmi);
1043         if (ret < 0) {
1044                 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1045                 goto ereqirq;
1046         }
1047
1048         return 0;
1049
1050 ereqirq:
1051         pm_runtime_disable(&pdev->dev);
1052         iounmap(hdmi->base);
1053 emap:
1054         release_mem_region(res->start, resource_size(res));
1055 ereqreg:
1056         clk_disable(hdmi->hdmi_clk);
1057 eclkenable:
1058 erate:
1059         clk_put(hdmi->hdmi_clk);
1060 egetclk:
1061         kfree(hdmi);
1062
1063         return ret;
1064 }
1065
1066 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1067 {
1068         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1069         struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1070         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1071         int irq = platform_get_irq(pdev, 0);
1072
1073         snd_soc_unregister_codec(&pdev->dev);
1074
1075         pdata->lcd_chan->board_cfg.display_on = NULL;
1076         pdata->lcd_chan->board_cfg.display_off = NULL;
1077         pdata->lcd_chan->board_cfg.board_data = NULL;
1078
1079         free_irq(irq, hdmi);
1080         pm_runtime_disable(&pdev->dev);
1081         cancel_delayed_work_sync(&hdmi->edid_work);
1082         clk_disable(hdmi->hdmi_clk);
1083         clk_put(hdmi->hdmi_clk);
1084         iounmap(hdmi->base);
1085         release_mem_region(res->start, resource_size(res));
1086         kfree(hdmi);
1087
1088         return 0;
1089 }
1090
1091 static struct platform_driver sh_hdmi_driver = {
1092         .remove         = __exit_p(sh_hdmi_remove),
1093         .driver = {
1094                 .name   = "sh-mobile-hdmi",
1095         },
1096 };
1097
1098 static int __init sh_hdmi_init(void)
1099 {
1100         return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1101 }
1102 module_init(sh_hdmi_init);
1103
1104 static void __exit sh_hdmi_exit(void)
1105 {
1106         platform_driver_unregister(&sh_hdmi_driver);
1107 }
1108 module_exit(sh_hdmi_exit);
1109
1110 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1111 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1112 MODULE_LICENSE("GPL v2");