2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
44 #include <plat/clock.h>
47 #include "dss_features.h"
49 /*#define VERBOSE_IRQ*/
50 #define DSI_CATCH_MISSING_TE
52 struct dsi_reg { u16 idx; };
54 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
56 #define DSI_SZ_REGS SZ_1K
57 /* DSI Protocol Engine */
59 #define DSI_REVISION DSI_REG(0x0000)
60 #define DSI_SYSCONFIG DSI_REG(0x0010)
61 #define DSI_SYSSTATUS DSI_REG(0x0014)
62 #define DSI_IRQSTATUS DSI_REG(0x0018)
63 #define DSI_IRQENABLE DSI_REG(0x001C)
64 #define DSI_CTRL DSI_REG(0x0040)
65 #define DSI_GNQ DSI_REG(0x0044)
66 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
67 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
68 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
69 #define DSI_CLK_CTRL DSI_REG(0x0054)
70 #define DSI_TIMING1 DSI_REG(0x0058)
71 #define DSI_TIMING2 DSI_REG(0x005C)
72 #define DSI_VM_TIMING1 DSI_REG(0x0060)
73 #define DSI_VM_TIMING2 DSI_REG(0x0064)
74 #define DSI_VM_TIMING3 DSI_REG(0x0068)
75 #define DSI_CLK_TIMING DSI_REG(0x006C)
76 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
77 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
78 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
79 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
80 #define DSI_VM_TIMING4 DSI_REG(0x0080)
81 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
82 #define DSI_VM_TIMING5 DSI_REG(0x0088)
83 #define DSI_VM_TIMING6 DSI_REG(0x008C)
84 #define DSI_VM_TIMING7 DSI_REG(0x0090)
85 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
86 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
87 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
89 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
90 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
91 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
92 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
96 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
97 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
98 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
99 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
100 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
102 /* DSI_PLL_CTRL_SCP */
104 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
105 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
106 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
107 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
108 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
110 #define REG_GET(dsidev, idx, start, end) \
111 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
114 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
116 /* Global interrupts */
117 #define DSI_IRQ_VC0 (1 << 0)
118 #define DSI_IRQ_VC1 (1 << 1)
119 #define DSI_IRQ_VC2 (1 << 2)
120 #define DSI_IRQ_VC3 (1 << 3)
121 #define DSI_IRQ_WAKEUP (1 << 4)
122 #define DSI_IRQ_RESYNC (1 << 5)
123 #define DSI_IRQ_PLL_LOCK (1 << 7)
124 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
125 #define DSI_IRQ_PLL_RECALL (1 << 9)
126 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
127 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
128 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
129 #define DSI_IRQ_TE_TRIGGER (1 << 16)
130 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
131 #define DSI_IRQ_SYNC_LOST (1 << 18)
132 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
133 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
134 #define DSI_IRQ_ERROR_MASK \
135 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
137 #define DSI_IRQ_CHANNEL_MASK 0xf
139 /* Virtual channel interrupts */
140 #define DSI_VC_IRQ_CS (1 << 0)
141 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
142 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
143 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
144 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
145 #define DSI_VC_IRQ_BTA (1 << 5)
146 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
147 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
149 #define DSI_VC_IRQ_ERROR_MASK \
150 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
151 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
152 DSI_VC_IRQ_FIFO_TX_UDF)
154 /* ComplexIO interrupts */
155 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
156 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
157 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
158 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
159 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
160 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
161 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
162 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
163 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
164 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
165 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
166 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
167 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
168 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
169 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
170 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
171 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
172 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
173 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
174 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
187 #define DSI_CIO_IRQ_ERROR_MASK \
188 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
189 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
190 DSI_CIO_IRQ_ERRSYNCESC5 | \
191 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
192 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
193 DSI_CIO_IRQ_ERRESC5 | \
194 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
195 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
196 DSI_CIO_IRQ_ERRCONTROL5 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
205 #define DSI_MAX_NR_ISRS 2
207 struct dsi_isr_data {
215 DSI_FIFO_SIZE_32 = 1,
216 DSI_FIFO_SIZE_64 = 2,
217 DSI_FIFO_SIZE_96 = 3,
218 DSI_FIFO_SIZE_128 = 4,
222 DSI_VC_SOURCE_L4 = 0,
229 DSI_DATA1_P = 1 << 2,
230 DSI_DATA1_N = 1 << 3,
231 DSI_DATA2_P = 1 << 4,
232 DSI_DATA2_N = 1 << 5,
233 DSI_DATA3_P = 1 << 6,
234 DSI_DATA3_N = 1 << 7,
235 DSI_DATA4_P = 1 << 8,
236 DSI_DATA4_N = 1 << 9,
239 struct dsi_update_region {
241 struct omap_dss_device *device;
244 struct dsi_irq_stats {
245 unsigned long last_reset;
247 unsigned dsi_irqs[32];
248 unsigned vc_irqs[4][32];
249 unsigned cio_irqs[32];
252 struct dsi_isr_tables {
253 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
254 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
255 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
259 struct platform_device *pdev;
267 int (*enable_pads)(int dsi_id, unsigned lane_mask);
268 void (*disable_pads)(int dsi_id, unsigned lane_mask);
270 struct dsi_clock_info current_cinfo;
272 bool vdds_dsi_enabled;
273 struct regulator *vdds_dsi_reg;
276 enum dsi_vc_source source;
277 struct omap_dss_device *dssdev;
278 enum fifo_size fifo_size;
283 struct semaphore bus_lock;
288 struct dsi_isr_tables isr_tables;
289 /* space for a copy used by the interrupt handler */
290 struct dsi_isr_tables isr_tables_copy;
293 struct dsi_update_region update_region;
298 void (*framedone_callback)(int, void *);
299 void *framedone_data;
301 struct delayed_work framedone_timeout_work;
303 #ifdef DSI_CATCH_MISSING_TE
304 struct timer_list te_timer;
307 unsigned long cache_req_pck;
308 unsigned long cache_clk_freq;
309 struct dsi_clock_info cache_cinfo;
312 spinlock_t errors_lock;
314 ktime_t perf_setup_time;
315 ktime_t perf_start_time;
320 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
321 spinlock_t irq_stats_lock;
322 struct dsi_irq_stats irq_stats;
324 /* DSI PLL Parameter Ranges */
325 unsigned long regm_max, regn_max;
326 unsigned long regm_dispc_max, regm_dsi_max;
327 unsigned long fint_min, fint_max;
328 unsigned long lpdiv_max;
332 unsigned scp_clk_refcount;
335 struct dsi_packet_sent_handler_data {
336 struct platform_device *dsidev;
337 struct completion *completion;
340 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
343 static unsigned int dsi_perf;
344 module_param_named(dsi_perf, dsi_perf, bool, 0644);
347 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
349 return dev_get_drvdata(&dsidev->dev);
352 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
354 return dsi_pdev_map[dssdev->phy.dsi.module];
357 struct platform_device *dsi_get_dsidev_from_id(int module)
359 return dsi_pdev_map[module];
362 static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
367 static inline void dsi_write_reg(struct platform_device *dsidev,
368 const struct dsi_reg idx, u32 val)
370 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
372 __raw_writel(val, dsi->base + idx.idx);
375 static inline u32 dsi_read_reg(struct platform_device *dsidev,
376 const struct dsi_reg idx)
378 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
380 return __raw_readl(dsi->base + idx.idx);
383 void dsi_bus_lock(struct omap_dss_device *dssdev)
385 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
386 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
388 down(&dsi->bus_lock);
390 EXPORT_SYMBOL(dsi_bus_lock);
392 void dsi_bus_unlock(struct omap_dss_device *dssdev)
394 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
395 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
399 EXPORT_SYMBOL(dsi_bus_unlock);
401 static bool dsi_bus_is_locked(struct platform_device *dsidev)
403 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
405 return dsi->bus_lock.count == 0;
408 static void dsi_completion_handler(void *data, u32 mask)
410 complete((struct completion *)data);
413 static inline int wait_for_bit_change(struct platform_device *dsidev,
414 const struct dsi_reg idx, int bitnum, int value)
418 while (REG_GET(dsidev, idx, bitnum, bitnum) != value) {
426 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
429 case OMAP_DSS_DSI_FMT_RGB888:
430 case OMAP_DSS_DSI_FMT_RGB666:
432 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
434 case OMAP_DSS_DSI_FMT_RGB565:
442 static void dsi_perf_mark_setup(struct platform_device *dsidev)
444 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
445 dsi->perf_setup_time = ktime_get();
448 static void dsi_perf_mark_start(struct platform_device *dsidev)
450 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
451 dsi->perf_start_time = ktime_get();
454 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
456 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
457 struct omap_dss_device *dssdev = dsi->update_region.device;
458 ktime_t t, setup_time, trans_time;
460 u32 setup_us, trans_us, total_us;
467 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
468 setup_us = (u32)ktime_to_us(setup_time);
472 trans_time = ktime_sub(t, dsi->perf_start_time);
473 trans_us = (u32)ktime_to_us(trans_time);
477 total_us = setup_us + trans_us;
479 total_bytes = dsi->update_region.w *
480 dsi->update_region.h *
481 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
483 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
484 "%u bytes, %u kbytes/sec\n",
489 1000*1000 / total_us,
491 total_bytes * 1000 / total_us);
494 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
498 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
502 static inline void dsi_perf_show(struct platform_device *dsidev,
508 static void print_irq_status(u32 status)
514 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
517 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
520 if (status & DSI_IRQ_##x) \
546 static void print_irq_status_vc(int channel, u32 status)
552 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
555 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
558 if (status & DSI_VC_IRQ_##x) \
575 static void print_irq_status_cio(u32 status)
580 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
583 if (status & DSI_CIO_IRQ_##x) \
597 PIS(ERRCONTENTIONLP0_1);
598 PIS(ERRCONTENTIONLP1_1);
599 PIS(ERRCONTENTIONLP0_2);
600 PIS(ERRCONTENTIONLP1_2);
601 PIS(ERRCONTENTIONLP0_3);
602 PIS(ERRCONTENTIONLP1_3);
603 PIS(ULPSACTIVENOT_ALL0);
604 PIS(ULPSACTIVENOT_ALL1);
610 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
611 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
612 u32 *vcstatus, u32 ciostatus)
614 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
617 spin_lock(&dsi->irq_stats_lock);
619 dsi->irq_stats.irq_count++;
620 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
622 for (i = 0; i < 4; ++i)
623 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
625 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
627 spin_unlock(&dsi->irq_stats_lock);
630 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
633 static int debug_irq;
635 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
636 u32 *vcstatus, u32 ciostatus)
638 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
641 if (irqstatus & DSI_IRQ_ERROR_MASK) {
642 DSSERR("DSI error, irqstatus %x\n", irqstatus);
643 print_irq_status(irqstatus);
644 spin_lock(&dsi->errors_lock);
645 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
646 spin_unlock(&dsi->errors_lock);
647 } else if (debug_irq) {
648 print_irq_status(irqstatus);
651 for (i = 0; i < 4; ++i) {
652 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
653 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
655 print_irq_status_vc(i, vcstatus[i]);
656 } else if (debug_irq) {
657 print_irq_status_vc(i, vcstatus[i]);
661 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
662 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
663 print_irq_status_cio(ciostatus);
664 } else if (debug_irq) {
665 print_irq_status_cio(ciostatus);
669 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
670 unsigned isr_array_size, u32 irqstatus)
672 struct dsi_isr_data *isr_data;
675 for (i = 0; i < isr_array_size; i++) {
676 isr_data = &isr_array[i];
677 if (isr_data->isr && isr_data->mask & irqstatus)
678 isr_data->isr(isr_data->arg, irqstatus);
682 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
683 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
687 dsi_call_isrs(isr_tables->isr_table,
688 ARRAY_SIZE(isr_tables->isr_table),
691 for (i = 0; i < 4; ++i) {
692 if (vcstatus[i] == 0)
694 dsi_call_isrs(isr_tables->isr_table_vc[i],
695 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
700 dsi_call_isrs(isr_tables->isr_table_cio,
701 ARRAY_SIZE(isr_tables->isr_table_cio),
705 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
707 struct platform_device *dsidev;
708 struct dsi_data *dsi;
709 u32 irqstatus, vcstatus[4], ciostatus;
712 dsidev = (struct platform_device *) arg;
713 dsi = dsi_get_dsidrv_data(dsidev);
715 spin_lock(&dsi->irq_lock);
717 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
719 /* IRQ is not for us */
721 spin_unlock(&dsi->irq_lock);
725 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
726 /* flush posted write */
727 dsi_read_reg(dsidev, DSI_IRQSTATUS);
729 for (i = 0; i < 4; ++i) {
730 if ((irqstatus & (1 << i)) == 0) {
735 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
737 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
738 /* flush posted write */
739 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
742 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
743 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
745 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
746 /* flush posted write */
747 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
752 #ifdef DSI_CATCH_MISSING_TE
753 if (irqstatus & DSI_IRQ_TE_TRIGGER)
754 del_timer(&dsi->te_timer);
757 /* make a copy and unlock, so that isrs can unregister
759 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
760 sizeof(dsi->isr_tables));
762 spin_unlock(&dsi->irq_lock);
764 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
766 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
768 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
773 /* dsi->irq_lock has to be locked by the caller */
774 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
775 struct dsi_isr_data *isr_array,
776 unsigned isr_array_size, u32 default_mask,
777 const struct dsi_reg enable_reg,
778 const struct dsi_reg status_reg)
780 struct dsi_isr_data *isr_data;
787 for (i = 0; i < isr_array_size; i++) {
788 isr_data = &isr_array[i];
790 if (isr_data->isr == NULL)
793 mask |= isr_data->mask;
796 old_mask = dsi_read_reg(dsidev, enable_reg);
797 /* clear the irqstatus for newly enabled irqs */
798 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
799 dsi_write_reg(dsidev, enable_reg, mask);
801 /* flush posted writes */
802 dsi_read_reg(dsidev, enable_reg);
803 dsi_read_reg(dsidev, status_reg);
806 /* dsi->irq_lock has to be locked by the caller */
807 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
809 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
810 u32 mask = DSI_IRQ_ERROR_MASK;
811 #ifdef DSI_CATCH_MISSING_TE
812 mask |= DSI_IRQ_TE_TRIGGER;
814 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
815 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
816 DSI_IRQENABLE, DSI_IRQSTATUS);
819 /* dsi->irq_lock has to be locked by the caller */
820 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
822 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
824 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
825 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
826 DSI_VC_IRQ_ERROR_MASK,
827 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
830 /* dsi->irq_lock has to be locked by the caller */
831 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
833 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
835 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
836 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
837 DSI_CIO_IRQ_ERROR_MASK,
838 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
841 static void _dsi_initialize_irq(struct platform_device *dsidev)
843 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
847 spin_lock_irqsave(&dsi->irq_lock, flags);
849 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
851 _omap_dsi_set_irqs(dsidev);
852 for (vc = 0; vc < 4; ++vc)
853 _omap_dsi_set_irqs_vc(dsidev, vc);
854 _omap_dsi_set_irqs_cio(dsidev);
856 spin_unlock_irqrestore(&dsi->irq_lock, flags);
859 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
860 struct dsi_isr_data *isr_array, unsigned isr_array_size)
862 struct dsi_isr_data *isr_data;
868 /* check for duplicate entry and find a free slot */
870 for (i = 0; i < isr_array_size; i++) {
871 isr_data = &isr_array[i];
873 if (isr_data->isr == isr && isr_data->arg == arg &&
874 isr_data->mask == mask) {
878 if (isr_data->isr == NULL && free_idx == -1)
885 isr_data = &isr_array[free_idx];
888 isr_data->mask = mask;
893 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
894 struct dsi_isr_data *isr_array, unsigned isr_array_size)
896 struct dsi_isr_data *isr_data;
899 for (i = 0; i < isr_array_size; i++) {
900 isr_data = &isr_array[i];
901 if (isr_data->isr != isr || isr_data->arg != arg ||
902 isr_data->mask != mask)
905 isr_data->isr = NULL;
906 isr_data->arg = NULL;
915 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
918 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
922 spin_lock_irqsave(&dsi->irq_lock, flags);
924 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
925 ARRAY_SIZE(dsi->isr_tables.isr_table));
928 _omap_dsi_set_irqs(dsidev);
930 spin_unlock_irqrestore(&dsi->irq_lock, flags);
935 static int dsi_unregister_isr(struct platform_device *dsidev,
936 omap_dsi_isr_t isr, void *arg, u32 mask)
938 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
942 spin_lock_irqsave(&dsi->irq_lock, flags);
944 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
945 ARRAY_SIZE(dsi->isr_tables.isr_table));
948 _omap_dsi_set_irqs(dsidev);
950 spin_unlock_irqrestore(&dsi->irq_lock, flags);
955 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
956 omap_dsi_isr_t isr, void *arg, u32 mask)
958 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
962 spin_lock_irqsave(&dsi->irq_lock, flags);
964 r = _dsi_register_isr(isr, arg, mask,
965 dsi->isr_tables.isr_table_vc[channel],
966 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
969 _omap_dsi_set_irqs_vc(dsidev, channel);
971 spin_unlock_irqrestore(&dsi->irq_lock, flags);
976 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
977 omap_dsi_isr_t isr, void *arg, u32 mask)
979 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
983 spin_lock_irqsave(&dsi->irq_lock, flags);
985 r = _dsi_unregister_isr(isr, arg, mask,
986 dsi->isr_tables.isr_table_vc[channel],
987 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
990 _omap_dsi_set_irqs_vc(dsidev, channel);
992 spin_unlock_irqrestore(&dsi->irq_lock, flags);
997 static int dsi_register_isr_cio(struct platform_device *dsidev,
998 omap_dsi_isr_t isr, void *arg, u32 mask)
1000 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1001 unsigned long flags;
1004 spin_lock_irqsave(&dsi->irq_lock, flags);
1006 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1007 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1010 _omap_dsi_set_irqs_cio(dsidev);
1012 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1017 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1018 omap_dsi_isr_t isr, void *arg, u32 mask)
1020 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1021 unsigned long flags;
1024 spin_lock_irqsave(&dsi->irq_lock, flags);
1026 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1027 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1030 _omap_dsi_set_irqs_cio(dsidev);
1032 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1037 static u32 dsi_get_errors(struct platform_device *dsidev)
1039 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1040 unsigned long flags;
1042 spin_lock_irqsave(&dsi->errors_lock, flags);
1045 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1049 int dsi_runtime_get(struct platform_device *dsidev)
1052 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1054 DSSDBG("dsi_runtime_get\n");
1056 r = pm_runtime_get_sync(&dsi->pdev->dev);
1058 return r < 0 ? r : 0;
1061 void dsi_runtime_put(struct platform_device *dsidev)
1063 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1066 DSSDBG("dsi_runtime_put\n");
1068 r = pm_runtime_put_sync(&dsi->pdev->dev);
1072 /* source clock for DSI PLL. this could also be PCLKFREE */
1073 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1076 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1079 clk_enable(dsi->sys_clk);
1081 clk_disable(dsi->sys_clk);
1083 if (enable && dsi->pll_locked) {
1084 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1085 DSSERR("cannot lock PLL when enabling clocks\n");
1090 static void _dsi_print_reset_status(struct platform_device *dsidev)
1098 /* A dummy read using the SCP interface to any DSIPHY register is
1099 * required after DSIPHY reset to complete the reset of the DSI complex
1101 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1103 printk(KERN_DEBUG "DSI resets: ");
1105 l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1106 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1108 l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1109 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1111 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1121 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1122 printk("PHY (%x%x%x, %d, %d, %d)\n",
1128 FLD_GET(l, 31, 31));
1131 #define _dsi_print_reset_status(x)
1134 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1136 DSSDBG("dsi_if_enable(%d)\n", enable);
1138 enable = enable ? 1 : 0;
1139 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1141 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1142 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1149 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1151 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1153 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1156 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1158 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1160 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1163 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1165 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1167 return dsi->current_cinfo.clkin4ddr / 16;
1170 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1173 int dsi_module = dsi_get_dsidev_id(dsidev);
1174 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1176 if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1177 /* DSI FCLK source is DSS_CLK_FCK */
1178 r = clk_get_rate(dsi->dss_clk);
1180 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1181 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1187 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1189 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1190 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1191 unsigned long dsi_fclk;
1192 unsigned lp_clk_div;
1193 unsigned long lp_clk;
1195 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1197 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1200 dsi_fclk = dsi_fclk_rate(dsidev);
1202 lp_clk = dsi_fclk / 2 / lp_clk_div;
1204 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1205 dsi->current_cinfo.lp_clk = lp_clk;
1206 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1208 /* LP_CLK_DIVISOR */
1209 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1211 /* LP_RX_SYNCHRO_ENABLE */
1212 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1217 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1219 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1221 if (dsi->scp_clk_refcount++ == 0)
1222 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1225 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1227 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1229 WARN_ON(dsi->scp_clk_refcount == 0);
1230 if (--dsi->scp_clk_refcount == 0)
1231 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1234 enum dsi_pll_power_state {
1235 DSI_PLL_POWER_OFF = 0x0,
1236 DSI_PLL_POWER_ON_HSCLK = 0x1,
1237 DSI_PLL_POWER_ON_ALL = 0x2,
1238 DSI_PLL_POWER_ON_DIV = 0x3,
1241 static int dsi_pll_power(struct platform_device *dsidev,
1242 enum dsi_pll_power_state state)
1246 /* DSI-PLL power command 0x3 is not working */
1247 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1248 state == DSI_PLL_POWER_ON_DIV)
1249 state = DSI_PLL_POWER_ON_ALL;
1252 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1254 /* PLL_PWR_STATUS */
1255 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1257 DSSERR("Failed to set DSI PLL power mode to %d\n",
1267 /* calculate clock rates using dividers in cinfo */
1268 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1269 struct dsi_clock_info *cinfo)
1271 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1272 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1274 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1277 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1280 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1283 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1286 if (cinfo->use_sys_clk) {
1287 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1288 /* XXX it is unclear if highfreq should be used
1289 * with DSS_SYS_CLK source also */
1290 cinfo->highfreq = 0;
1292 cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id);
1294 if (cinfo->clkin < 32000000)
1295 cinfo->highfreq = 0;
1297 cinfo->highfreq = 1;
1300 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1302 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1305 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1307 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1310 if (cinfo->regm_dispc > 0)
1311 cinfo->dsi_pll_hsdiv_dispc_clk =
1312 cinfo->clkin4ddr / cinfo->regm_dispc;
1314 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1316 if (cinfo->regm_dsi > 0)
1317 cinfo->dsi_pll_hsdiv_dsi_clk =
1318 cinfo->clkin4ddr / cinfo->regm_dsi;
1320 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1325 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1326 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1327 struct dispc_clock_info *dispc_cinfo)
1329 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1330 struct dsi_clock_info cur, best;
1331 struct dispc_clock_info best_dispc;
1332 int min_fck_per_pck;
1334 unsigned long dss_sys_clk, max_dss_fck;
1336 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1338 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1340 if (req_pck == dsi->cache_req_pck &&
1341 dsi->cache_cinfo.clkin == dss_sys_clk) {
1342 DSSDBG("DSI clock info found from cache\n");
1343 *dsi_cinfo = dsi->cache_cinfo;
1344 dispc_find_clk_divs(is_tft, req_pck,
1345 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1349 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1351 if (min_fck_per_pck &&
1352 req_pck * min_fck_per_pck > max_dss_fck) {
1353 DSSERR("Requested pixel clock not possible with the current "
1354 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1355 "the constraint off.\n");
1356 min_fck_per_pck = 0;
1359 DSSDBG("dsi_pll_calc\n");
1362 memset(&best, 0, sizeof(best));
1363 memset(&best_dispc, 0, sizeof(best_dispc));
1365 memset(&cur, 0, sizeof(cur));
1366 cur.clkin = dss_sys_clk;
1367 cur.use_sys_clk = 1;
1370 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1371 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1372 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1373 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1374 if (cur.highfreq == 0)
1375 cur.fint = cur.clkin / cur.regn;
1377 cur.fint = cur.clkin / (2 * cur.regn);
1379 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1382 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1383 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1386 a = 2 * cur.regm * (cur.clkin/1000);
1387 b = cur.regn * (cur.highfreq + 1);
1388 cur.clkin4ddr = a / b * 1000;
1390 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1393 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1394 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1395 for (cur.regm_dispc = 1; cur.regm_dispc <
1396 dsi->regm_dispc_max; ++cur.regm_dispc) {
1397 struct dispc_clock_info cur_dispc;
1398 cur.dsi_pll_hsdiv_dispc_clk =
1399 cur.clkin4ddr / cur.regm_dispc;
1401 /* this will narrow down the search a bit,
1402 * but still give pixclocks below what was
1404 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1407 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1410 if (min_fck_per_pck &&
1411 cur.dsi_pll_hsdiv_dispc_clk <
1412 req_pck * min_fck_per_pck)
1417 dispc_find_clk_divs(is_tft, req_pck,
1418 cur.dsi_pll_hsdiv_dispc_clk,
1421 if (abs(cur_dispc.pck - req_pck) <
1422 abs(best_dispc.pck - req_pck)) {
1424 best_dispc = cur_dispc;
1426 if (cur_dispc.pck == req_pck)
1434 if (min_fck_per_pck) {
1435 DSSERR("Could not find suitable clock settings.\n"
1436 "Turning FCK/PCK constraint off and"
1438 min_fck_per_pck = 0;
1442 DSSERR("Could not find suitable clock settings.\n");
1447 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1449 best.dsi_pll_hsdiv_dsi_clk = 0;
1454 *dispc_cinfo = best_dispc;
1456 dsi->cache_req_pck = req_pck;
1457 dsi->cache_clk_freq = 0;
1458 dsi->cache_cinfo = best;
1463 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1464 struct dsi_clock_info *cinfo)
1466 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1470 u8 regn_start, regn_end, regm_start, regm_end;
1471 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1475 dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1476 dsi->current_cinfo.highfreq = cinfo->highfreq;
1478 dsi->current_cinfo.fint = cinfo->fint;
1479 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1480 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1481 cinfo->dsi_pll_hsdiv_dispc_clk;
1482 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1483 cinfo->dsi_pll_hsdiv_dsi_clk;
1485 dsi->current_cinfo.regn = cinfo->regn;
1486 dsi->current_cinfo.regm = cinfo->regm;
1487 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1488 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1490 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1492 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1493 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1497 /* DSIPHY == CLKIN4DDR */
1498 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1502 cinfo->highfreq + 1,
1505 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1506 cinfo->clkin4ddr / 1000 / 1000 / 2);
1508 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1510 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1511 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1512 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1513 cinfo->dsi_pll_hsdiv_dispc_clk);
1514 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1515 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1516 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1517 cinfo->dsi_pll_hsdiv_dsi_clk);
1519 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
1520 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
1521 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
1523 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
1526 /* DSI_PLL_AUTOMODE = manual */
1527 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1529 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1530 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1532 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1534 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1536 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1537 regm_dispc_start, regm_dispc_end);
1538 /* DSIPROTO_CLOCK_DIV */
1539 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1540 regm_dsi_start, regm_dsi_end);
1541 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1543 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1545 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1546 f = cinfo->fint < 1000000 ? 0x3 :
1547 cinfo->fint < 1250000 ? 0x4 :
1548 cinfo->fint < 1500000 ? 0x5 :
1549 cinfo->fint < 1750000 ? 0x6 :
1553 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1555 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1556 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1557 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1558 11, 11); /* DSI_PLL_CLKSEL */
1559 l = FLD_MOD(l, cinfo->highfreq,
1560 12, 12); /* DSI_PLL_HIGHFREQ */
1561 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1562 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1563 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1564 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1566 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1568 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1569 DSSERR("dsi pll go bit not going down.\n");
1574 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1575 DSSERR("cannot lock PLL\n");
1580 dsi->pll_locked = 1;
1582 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1583 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1584 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1585 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1586 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1587 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1588 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1589 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1590 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1591 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1592 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1593 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1594 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1595 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1596 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1597 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1599 DSSDBG("PLL config done\n");
1604 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1607 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1609 enum dsi_pll_power_state pwstate;
1611 DSSDBG("PLL init\n");
1613 if (dsi->vdds_dsi_reg == NULL) {
1614 struct regulator *vdds_dsi;
1616 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1618 if (IS_ERR(vdds_dsi)) {
1619 DSSERR("can't get VDDS_DSI regulator\n");
1620 return PTR_ERR(vdds_dsi);
1623 dsi->vdds_dsi_reg = vdds_dsi;
1626 dsi_enable_pll_clock(dsidev, 1);
1628 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1630 dsi_enable_scp_clk(dsidev);
1632 if (!dsi->vdds_dsi_enabled) {
1633 r = regulator_enable(dsi->vdds_dsi_reg);
1636 dsi->vdds_dsi_enabled = true;
1639 /* XXX PLL does not come out of reset without this... */
1640 dispc_pck_free_enable(1);
1642 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1643 DSSERR("PLL not coming out of reset.\n");
1645 dispc_pck_free_enable(0);
1649 /* XXX ... but if left on, we get problems when planes do not
1650 * fill the whole display. No idea about this */
1651 dispc_pck_free_enable(0);
1653 if (enable_hsclk && enable_hsdiv)
1654 pwstate = DSI_PLL_POWER_ON_ALL;
1655 else if (enable_hsclk)
1656 pwstate = DSI_PLL_POWER_ON_HSCLK;
1657 else if (enable_hsdiv)
1658 pwstate = DSI_PLL_POWER_ON_DIV;
1660 pwstate = DSI_PLL_POWER_OFF;
1662 r = dsi_pll_power(dsidev, pwstate);
1667 DSSDBG("PLL init done\n");
1671 if (dsi->vdds_dsi_enabled) {
1672 regulator_disable(dsi->vdds_dsi_reg);
1673 dsi->vdds_dsi_enabled = false;
1676 dsi_disable_scp_clk(dsidev);
1677 dsi_enable_pll_clock(dsidev, 0);
1681 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1683 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1685 dsi->pll_locked = 0;
1686 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1687 if (disconnect_lanes) {
1688 WARN_ON(!dsi->vdds_dsi_enabled);
1689 regulator_disable(dsi->vdds_dsi_reg);
1690 dsi->vdds_dsi_enabled = false;
1693 dsi_disable_scp_clk(dsidev);
1694 dsi_enable_pll_clock(dsidev, 0);
1696 DSSDBG("PLL uninit done\n");
1699 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1702 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1703 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1704 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1705 int dsi_module = dsi_get_dsidev_id(dsidev);
1707 dispc_clk_src = dss_get_dispc_clk_source();
1708 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1710 if (dsi_runtime_get(dsidev))
1713 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1715 seq_printf(s, "dsi pll source = %s\n",
1716 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1718 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1720 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1721 cinfo->clkin4ddr, cinfo->regm);
1723 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1724 dss_get_generic_clk_source_name(dispc_clk_src),
1725 dss_feat_get_clk_source_name(dispc_clk_src),
1726 cinfo->dsi_pll_hsdiv_dispc_clk,
1728 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1731 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1732 dss_get_generic_clk_source_name(dsi_clk_src),
1733 dss_feat_get_clk_source_name(dsi_clk_src),
1734 cinfo->dsi_pll_hsdiv_dsi_clk,
1736 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1739 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1741 seq_printf(s, "dsi fclk source = %s (%s)\n",
1742 dss_get_generic_clk_source_name(dsi_clk_src),
1743 dss_feat_get_clk_source_name(dsi_clk_src));
1745 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1747 seq_printf(s, "DDR_CLK\t\t%lu\n",
1748 cinfo->clkin4ddr / 4);
1750 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1752 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1754 dsi_runtime_put(dsidev);
1757 void dsi_dump_clocks(struct seq_file *s)
1759 struct platform_device *dsidev;
1762 for (i = 0; i < MAX_NUM_DSI; i++) {
1763 dsidev = dsi_get_dsidev_from_id(i);
1765 dsi_dump_dsidev_clocks(dsidev, s);
1769 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1770 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1773 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1774 unsigned long flags;
1775 struct dsi_irq_stats stats;
1776 int dsi_module = dsi_get_dsidev_id(dsidev);
1778 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1780 stats = dsi->irq_stats;
1781 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1782 dsi->irq_stats.last_reset = jiffies;
1784 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1786 seq_printf(s, "period %u ms\n",
1787 jiffies_to_msecs(jiffies - stats.last_reset));
1789 seq_printf(s, "irqs %d\n", stats.irq_count);
1791 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1793 seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1809 PIS(LDO_POWER_GOOD);
1814 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1815 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1816 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1817 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1818 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1820 seq_printf(s, "-- VC interrupts --\n");
1829 PIS(PP_BUSY_CHANGE);
1833 seq_printf(s, "%-20s %10d\n", #x, \
1834 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1836 seq_printf(s, "-- CIO interrupts --\n");
1849 PIS(ERRCONTENTIONLP0_1);
1850 PIS(ERRCONTENTIONLP1_1);
1851 PIS(ERRCONTENTIONLP0_2);
1852 PIS(ERRCONTENTIONLP1_2);
1853 PIS(ERRCONTENTIONLP0_3);
1854 PIS(ERRCONTENTIONLP1_3);
1855 PIS(ULPSACTIVENOT_ALL0);
1856 PIS(ULPSACTIVENOT_ALL1);
1860 static void dsi1_dump_irqs(struct seq_file *s)
1862 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1864 dsi_dump_dsidev_irqs(dsidev, s);
1867 static void dsi2_dump_irqs(struct seq_file *s)
1869 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1871 dsi_dump_dsidev_irqs(dsidev, s);
1874 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1875 const struct file_operations *debug_fops)
1877 struct platform_device *dsidev;
1879 dsidev = dsi_get_dsidev_from_id(0);
1881 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1882 &dsi1_dump_irqs, debug_fops);
1884 dsidev = dsi_get_dsidev_from_id(1);
1886 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1887 &dsi2_dump_irqs, debug_fops);
1891 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1894 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1896 if (dsi_runtime_get(dsidev))
1898 dsi_enable_scp_clk(dsidev);
1900 DUMPREG(DSI_REVISION);
1901 DUMPREG(DSI_SYSCONFIG);
1902 DUMPREG(DSI_SYSSTATUS);
1903 DUMPREG(DSI_IRQSTATUS);
1904 DUMPREG(DSI_IRQENABLE);
1906 DUMPREG(DSI_COMPLEXIO_CFG1);
1907 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1908 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1909 DUMPREG(DSI_CLK_CTRL);
1910 DUMPREG(DSI_TIMING1);
1911 DUMPREG(DSI_TIMING2);
1912 DUMPREG(DSI_VM_TIMING1);
1913 DUMPREG(DSI_VM_TIMING2);
1914 DUMPREG(DSI_VM_TIMING3);
1915 DUMPREG(DSI_CLK_TIMING);
1916 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1917 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1918 DUMPREG(DSI_COMPLEXIO_CFG2);
1919 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1920 DUMPREG(DSI_VM_TIMING4);
1921 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1922 DUMPREG(DSI_VM_TIMING5);
1923 DUMPREG(DSI_VM_TIMING6);
1924 DUMPREG(DSI_VM_TIMING7);
1925 DUMPREG(DSI_STOPCLK_TIMING);
1927 DUMPREG(DSI_VC_CTRL(0));
1928 DUMPREG(DSI_VC_TE(0));
1929 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1930 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1931 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1932 DUMPREG(DSI_VC_IRQSTATUS(0));
1933 DUMPREG(DSI_VC_IRQENABLE(0));
1935 DUMPREG(DSI_VC_CTRL(1));
1936 DUMPREG(DSI_VC_TE(1));
1937 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1938 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1939 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1940 DUMPREG(DSI_VC_IRQSTATUS(1));
1941 DUMPREG(DSI_VC_IRQENABLE(1));
1943 DUMPREG(DSI_VC_CTRL(2));
1944 DUMPREG(DSI_VC_TE(2));
1945 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1946 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1947 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1948 DUMPREG(DSI_VC_IRQSTATUS(2));
1949 DUMPREG(DSI_VC_IRQENABLE(2));
1951 DUMPREG(DSI_VC_CTRL(3));
1952 DUMPREG(DSI_VC_TE(3));
1953 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1954 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1955 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1956 DUMPREG(DSI_VC_IRQSTATUS(3));
1957 DUMPREG(DSI_VC_IRQENABLE(3));
1959 DUMPREG(DSI_DSIPHY_CFG0);
1960 DUMPREG(DSI_DSIPHY_CFG1);
1961 DUMPREG(DSI_DSIPHY_CFG2);
1962 DUMPREG(DSI_DSIPHY_CFG5);
1964 DUMPREG(DSI_PLL_CONTROL);
1965 DUMPREG(DSI_PLL_STATUS);
1966 DUMPREG(DSI_PLL_GO);
1967 DUMPREG(DSI_PLL_CONFIGURATION1);
1968 DUMPREG(DSI_PLL_CONFIGURATION2);
1970 dsi_disable_scp_clk(dsidev);
1971 dsi_runtime_put(dsidev);
1975 static void dsi1_dump_regs(struct seq_file *s)
1977 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1979 dsi_dump_dsidev_regs(dsidev, s);
1982 static void dsi2_dump_regs(struct seq_file *s)
1984 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1986 dsi_dump_dsidev_regs(dsidev, s);
1989 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
1990 const struct file_operations *debug_fops)
1992 struct platform_device *dsidev;
1994 dsidev = dsi_get_dsidev_from_id(0);
1996 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
1997 &dsi1_dump_regs, debug_fops);
1999 dsidev = dsi_get_dsidev_from_id(1);
2001 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
2002 &dsi2_dump_regs, debug_fops);
2004 enum dsi_cio_power_state {
2005 DSI_COMPLEXIO_POWER_OFF = 0x0,
2006 DSI_COMPLEXIO_POWER_ON = 0x1,
2007 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2010 static int dsi_cio_power(struct platform_device *dsidev,
2011 enum dsi_cio_power_state state)
2016 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2019 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2022 DSSERR("failed to set complexio power state to "
2032 /* Number of data lanes present on DSI interface */
2033 static inline int dsi_get_num_data_lanes(struct platform_device *dsidev)
2035 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
2036 * of data lanes as 2 by default */
2037 if (dss_has_feature(FEAT_DSI_GNQ))
2038 return REG_GET(dsidev, DSI_GNQ, 11, 9); /* NB_DATA_LANES */
2043 /* Number of data lanes used by the dss device */
2044 static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev)
2046 int num_data_lanes = 0;
2048 if (dssdev->phy.dsi.data1_lane != 0)
2050 if (dssdev->phy.dsi.data2_lane != 0)
2052 if (dssdev->phy.dsi.data3_lane != 0)
2054 if (dssdev->phy.dsi.data4_lane != 0)
2057 return num_data_lanes;
2060 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2064 /* line buffer on OMAP3 is 1024 x 24bits */
2065 /* XXX: for some reason using full buffer size causes
2066 * considerable TX slowdown with update sizes that fill the
2068 if (!dss_has_feature(FEAT_DSI_GNQ))
2071 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2075 return 512 * 3; /* 512x24 bits */
2077 return 682 * 3; /* 682x24 bits */
2079 return 853 * 3; /* 853x24 bits */
2081 return 1024 * 3; /* 1024x24 bits */
2083 return 1194 * 3; /* 1194x24 bits */
2085 return 1365 * 3; /* 1365x24 bits */
2091 static void dsi_set_lane_config(struct omap_dss_device *dssdev)
2093 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2095 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2097 int clk_lane = dssdev->phy.dsi.clk_lane;
2098 int data1_lane = dssdev->phy.dsi.data1_lane;
2099 int data2_lane = dssdev->phy.dsi.data2_lane;
2100 int clk_pol = dssdev->phy.dsi.clk_pol;
2101 int data1_pol = dssdev->phy.dsi.data1_pol;
2102 int data2_pol = dssdev->phy.dsi.data2_pol;
2104 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2105 r = FLD_MOD(r, clk_lane, 2, 0);
2106 r = FLD_MOD(r, clk_pol, 3, 3);
2107 r = FLD_MOD(r, data1_lane, 6, 4);
2108 r = FLD_MOD(r, data1_pol, 7, 7);
2109 r = FLD_MOD(r, data2_lane, 10, 8);
2110 r = FLD_MOD(r, data2_pol, 11, 11);
2111 if (num_data_lanes_dssdev > 2) {
2112 int data3_lane = dssdev->phy.dsi.data3_lane;
2113 int data3_pol = dssdev->phy.dsi.data3_pol;
2115 r = FLD_MOD(r, data3_lane, 14, 12);
2116 r = FLD_MOD(r, data3_pol, 15, 15);
2118 if (num_data_lanes_dssdev > 3) {
2119 int data4_lane = dssdev->phy.dsi.data4_lane;
2120 int data4_pol = dssdev->phy.dsi.data4_pol;
2122 r = FLD_MOD(r, data4_lane, 18, 16);
2123 r = FLD_MOD(r, data4_pol, 19, 19);
2125 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2127 /* The configuration of the DSI complex I/O (number of data lanes,
2128 position, differential order) should not be changed while
2129 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
2130 the hardware to take into account a new configuration of the complex
2131 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
2132 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
2133 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
2134 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
2135 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
2136 DSI complex I/O configuration is unknown. */
2139 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2140 REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0);
2141 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20);
2142 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2146 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2148 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2150 /* convert time in ns to ddr ticks, rounding up */
2151 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2152 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2155 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2159 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2160 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2163 static void dsi_cio_timings(struct platform_device *dsidev)
2166 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2167 u32 tlpx_half, tclk_trail, tclk_zero;
2170 /* calculate timings */
2172 /* 1 * DDR_CLK = 2 * UI */
2174 /* min 40ns + 4*UI max 85ns + 6*UI */
2175 ths_prepare = ns2ddr(dsidev, 70) + 2;
2177 /* min 145ns + 10*UI */
2178 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2180 /* min max(8*UI, 60ns+4*UI) */
2181 ths_trail = ns2ddr(dsidev, 60) + 5;
2184 ths_exit = ns2ddr(dsidev, 145);
2187 tlpx_half = ns2ddr(dsidev, 25);
2190 tclk_trail = ns2ddr(dsidev, 60) + 2;
2192 /* min 38ns, max 95ns */
2193 tclk_prepare = ns2ddr(dsidev, 65);
2195 /* min tclk-prepare + tclk-zero = 300ns */
2196 tclk_zero = ns2ddr(dsidev, 260);
2198 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2199 ths_prepare, ddr2ns(dsidev, ths_prepare),
2200 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2201 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2202 ths_trail, ddr2ns(dsidev, ths_trail),
2203 ths_exit, ddr2ns(dsidev, ths_exit));
2205 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2206 "tclk_zero %u (%uns)\n",
2207 tlpx_half, ddr2ns(dsidev, tlpx_half),
2208 tclk_trail, ddr2ns(dsidev, tclk_trail),
2209 tclk_zero, ddr2ns(dsidev, tclk_zero));
2210 DSSDBG("tclk_prepare %u (%uns)\n",
2211 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2213 /* program timings */
2215 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2216 r = FLD_MOD(r, ths_prepare, 31, 24);
2217 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2218 r = FLD_MOD(r, ths_trail, 15, 8);
2219 r = FLD_MOD(r, ths_exit, 7, 0);
2220 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2222 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2223 r = FLD_MOD(r, tlpx_half, 22, 16);
2224 r = FLD_MOD(r, tclk_trail, 15, 8);
2225 r = FLD_MOD(r, tclk_zero, 7, 0);
2226 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2228 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2229 r = FLD_MOD(r, tclk_prepare, 7, 0);
2230 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2233 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2234 enum dsi_lane lanes)
2236 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2237 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2238 int clk_lane = dssdev->phy.dsi.clk_lane;
2239 int data1_lane = dssdev->phy.dsi.data1_lane;
2240 int data2_lane = dssdev->phy.dsi.data2_lane;
2241 int data3_lane = dssdev->phy.dsi.data3_lane;
2242 int data4_lane = dssdev->phy.dsi.data4_lane;
2243 int clk_pol = dssdev->phy.dsi.clk_pol;
2244 int data1_pol = dssdev->phy.dsi.data1_pol;
2245 int data2_pol = dssdev->phy.dsi.data2_pol;
2246 int data3_pol = dssdev->phy.dsi.data3_pol;
2247 int data4_pol = dssdev->phy.dsi.data4_pol;
2250 u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26;
2252 if (lanes & DSI_CLK_P)
2253 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
2254 if (lanes & DSI_CLK_N)
2255 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0));
2257 if (lanes & DSI_DATA1_P)
2258 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1));
2259 if (lanes & DSI_DATA1_N)
2260 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0));
2262 if (lanes & DSI_DATA2_P)
2263 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1));
2264 if (lanes & DSI_DATA2_N)
2265 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));
2267 if (lanes & DSI_DATA3_P)
2268 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1));
2269 if (lanes & DSI_DATA3_N)
2270 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0));
2272 if (lanes & DSI_DATA4_P)
2273 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1));
2274 if (lanes & DSI_DATA4_N)
2275 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0));
2277 * Bits in REGLPTXSCPDAT4TO0DXDY:
2285 /* Set the lane override configuration */
2287 /* REGLPTXSCPDAT4TO0DXDY */
2288 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2290 /* Enable lane override */
2293 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2296 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2298 /* Disable lane override */
2299 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2300 /* Reset the lane override configuration */
2301 /* REGLPTXSCPDAT4TO0DXDY */
2302 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2305 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2307 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2312 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
2326 if (dssdev->phy.dsi.clk_lane != 0)
2327 in_use[dssdev->phy.dsi.clk_lane - 1] = true;
2328 if (dssdev->phy.dsi.data1_lane != 0)
2329 in_use[dssdev->phy.dsi.data1_lane - 1] = true;
2330 if (dssdev->phy.dsi.data2_lane != 0)
2331 in_use[dssdev->phy.dsi.data2_lane - 1] = true;
2339 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2342 for (i = 0; i < 3; ++i) {
2343 if (!in_use[i] || (l & (1 << bits[i])))
2351 for (i = 0; i < 3; ++i) {
2352 if (!in_use[i] || (l & (1 << bits[i])))
2355 DSSERR("CIO TXCLKESC%d domain not coming " \
2356 "out of reset\n", i);
2365 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2369 if (dssdev->phy.dsi.clk_lane != 0)
2370 lanes |= 1 << (dssdev->phy.dsi.clk_lane - 1);
2371 if (dssdev->phy.dsi.data1_lane != 0)
2372 lanes |= 1 << (dssdev->phy.dsi.data1_lane - 1);
2373 if (dssdev->phy.dsi.data2_lane != 0)
2374 lanes |= 1 << (dssdev->phy.dsi.data2_lane - 1);
2375 if (dssdev->phy.dsi.data3_lane != 0)
2376 lanes |= 1 << (dssdev->phy.dsi.data3_lane - 1);
2377 if (dssdev->phy.dsi.data4_lane != 0)
2378 lanes |= 1 << (dssdev->phy.dsi.data4_lane - 1);
2383 static int dsi_cio_init(struct omap_dss_device *dssdev)
2385 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2386 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2388 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2393 r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2397 dsi_enable_scp_clk(dsidev);
2399 /* A dummy read using the SCP interface to any DSIPHY register is
2400 * required after DSIPHY reset to complete the reset of the DSI complex
2402 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2404 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2405 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2407 goto err_scp_clk_dom;
2410 dsi_set_lane_config(dssdev);
2412 /* set TX STOP MODE timer to maximum for this operation */
2413 l = dsi_read_reg(dsidev, DSI_TIMING1);
2414 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2415 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2416 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2417 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2418 dsi_write_reg(dsidev, DSI_TIMING1, l);
2420 if (dsi->ulps_enabled) {
2421 u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P;
2423 DSSDBG("manual ulps exit\n");
2425 /* ULPS is exited by Mark-1 state for 1ms, followed by
2426 * stop state. DSS HW cannot do this via the normal
2427 * ULPS exit sequence, as after reset the DSS HW thinks
2428 * that we are not in ULPS mode, and refuses to send the
2429 * sequence. So we need to send the ULPS exit sequence
2433 if (num_data_lanes_dssdev > 2)
2434 lane_mask |= DSI_DATA3_P;
2436 if (num_data_lanes_dssdev > 3)
2437 lane_mask |= DSI_DATA4_P;
2439 dsi_cio_enable_lane_override(dssdev, lane_mask);
2442 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2446 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2447 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2449 goto err_cio_pwr_dom;
2452 dsi_if_enable(dsidev, true);
2453 dsi_if_enable(dsidev, false);
2454 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2456 r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2458 goto err_tx_clk_esc_rst;
2460 if (dsi->ulps_enabled) {
2461 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2462 ktime_t wait = ns_to_ktime(1000 * 1000);
2463 set_current_state(TASK_UNINTERRUPTIBLE);
2464 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2466 /* Disable the override. The lanes should be set to Mark-11
2467 * state by the HW */
2468 dsi_cio_disable_lane_override(dsidev);
2471 /* FORCE_TX_STOP_MODE_IO */
2472 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2474 dsi_cio_timings(dsidev);
2476 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2477 /* DDR_CLK_ALWAYS_ON */
2478 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2479 dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2482 dsi->ulps_enabled = false;
2484 DSSDBG("CIO init done\n");
2489 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2491 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2493 if (dsi->ulps_enabled)
2494 dsi_cio_disable_lane_override(dsidev);
2496 dsi_disable_scp_clk(dsidev);
2497 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2501 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2503 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2504 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2506 /* DDR_CLK_ALWAYS_ON */
2507 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2509 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2510 dsi_disable_scp_clk(dsidev);
2511 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2514 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2515 enum fifo_size size1, enum fifo_size size2,
2516 enum fifo_size size3, enum fifo_size size4)
2518 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2523 dsi->vc[0].fifo_size = size1;
2524 dsi->vc[1].fifo_size = size2;
2525 dsi->vc[2].fifo_size = size3;
2526 dsi->vc[3].fifo_size = size4;
2528 for (i = 0; i < 4; i++) {
2530 int size = dsi->vc[i].fifo_size;
2532 if (add + size > 4) {
2533 DSSERR("Illegal FIFO configuration\n");
2537 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2539 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2543 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2546 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2547 enum fifo_size size1, enum fifo_size size2,
2548 enum fifo_size size3, enum fifo_size size4)
2550 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2555 dsi->vc[0].fifo_size = size1;
2556 dsi->vc[1].fifo_size = size2;
2557 dsi->vc[2].fifo_size = size3;
2558 dsi->vc[3].fifo_size = size4;
2560 for (i = 0; i < 4; i++) {
2562 int size = dsi->vc[i].fifo_size;
2564 if (add + size > 4) {
2565 DSSERR("Illegal FIFO configuration\n");
2569 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2571 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2575 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2578 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2582 r = dsi_read_reg(dsidev, DSI_TIMING1);
2583 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2584 dsi_write_reg(dsidev, DSI_TIMING1, r);
2586 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2587 DSSERR("TX_STOP bit not going down\n");
2594 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2596 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2599 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2601 struct dsi_packet_sent_handler_data *vp_data =
2602 (struct dsi_packet_sent_handler_data *) data;
2603 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2604 const int channel = dsi->update_channel;
2605 u8 bit = dsi->te_enabled ? 30 : 31;
2607 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2608 complete(vp_data->completion);
2611 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2613 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2614 DECLARE_COMPLETION_ONSTACK(completion);
2615 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2619 bit = dsi->te_enabled ? 30 : 31;
2621 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2622 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2626 /* Wait for completion only if TE_EN/TE_START is still set */
2627 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2628 if (wait_for_completion_timeout(&completion,
2629 msecs_to_jiffies(10)) == 0) {
2630 DSSERR("Failed to complete previous frame transfer\n");
2636 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2637 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2641 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2642 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2647 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2649 struct dsi_packet_sent_handler_data *l4_data =
2650 (struct dsi_packet_sent_handler_data *) data;
2651 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2652 const int channel = dsi->update_channel;
2654 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2655 complete(l4_data->completion);
2658 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2660 DECLARE_COMPLETION_ONSTACK(completion);
2661 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2664 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2665 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2669 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2670 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2671 if (wait_for_completion_timeout(&completion,
2672 msecs_to_jiffies(10)) == 0) {
2673 DSSERR("Failed to complete previous l4 transfer\n");
2679 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2680 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2684 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2685 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2690 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2692 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2694 WARN_ON(!dsi_bus_is_locked(dsidev));
2696 WARN_ON(in_interrupt());
2698 if (!dsi_vc_is_enabled(dsidev, channel))
2701 switch (dsi->vc[channel].source) {
2702 case DSI_VC_SOURCE_VP:
2703 return dsi_sync_vc_vp(dsidev, channel);
2704 case DSI_VC_SOURCE_L4:
2705 return dsi_sync_vc_l4(dsidev, channel);
2711 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2714 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2717 enable = enable ? 1 : 0;
2719 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2721 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2722 0, enable) != enable) {
2723 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2730 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2734 DSSDBGF("%d", channel);
2736 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2738 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2739 DSSERR("VC(%d) busy when trying to configure it!\n",
2742 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2743 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2744 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2745 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2746 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2747 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2748 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2749 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2750 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2752 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2753 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2755 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2758 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2759 enum dsi_vc_source source)
2761 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2763 if (dsi->vc[channel].source == source)
2766 DSSDBGF("%d", channel);
2768 dsi_sync_vc(dsidev, channel);
2770 dsi_vc_enable(dsidev, channel, 0);
2773 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2774 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2778 /* SOURCE, 0 = L4, 1 = video port */
2779 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2781 /* DCS_CMD_ENABLE */
2782 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2783 bool enable = source == DSI_VC_SOURCE_VP;
2784 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2787 dsi_vc_enable(dsidev, channel, 1);
2789 dsi->vc[channel].source = source;
2794 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2797 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2799 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2801 WARN_ON(!dsi_bus_is_locked(dsidev));
2803 dsi_vc_enable(dsidev, channel, 0);
2804 dsi_if_enable(dsidev, 0);
2806 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2808 dsi_vc_enable(dsidev, channel, 1);
2809 dsi_if_enable(dsidev, 1);
2811 dsi_force_tx_stop_mode_io(dsidev);
2813 /* start the DDR clock by sending a NULL packet */
2814 if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2815 dsi_vc_send_null(dssdev, channel);
2817 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2819 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2821 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2823 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2824 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2828 (val >> 24) & 0xff);
2832 static void dsi_show_rx_ack_with_err(u16 err)
2834 DSSERR("\tACK with ERROR (%#x):\n", err);
2836 DSSERR("\t\tSoT Error\n");
2838 DSSERR("\t\tSoT Sync Error\n");
2840 DSSERR("\t\tEoT Sync Error\n");
2842 DSSERR("\t\tEscape Mode Entry Command Error\n");
2844 DSSERR("\t\tLP Transmit Sync Error\n");
2846 DSSERR("\t\tHS Receive Timeout Error\n");
2848 DSSERR("\t\tFalse Control Error\n");
2850 DSSERR("\t\t(reserved7)\n");
2852 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2854 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2855 if (err & (1 << 10))
2856 DSSERR("\t\tChecksum Error\n");
2857 if (err & (1 << 11))
2858 DSSERR("\t\tData type not recognized\n");
2859 if (err & (1 << 12))
2860 DSSERR("\t\tInvalid VC ID\n");
2861 if (err & (1 << 13))
2862 DSSERR("\t\tInvalid Transmission Length\n");
2863 if (err & (1 << 14))
2864 DSSERR("\t\t(reserved14)\n");
2865 if (err & (1 << 15))
2866 DSSERR("\t\tDSI Protocol Violation\n");
2869 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2872 /* RX_FIFO_NOT_EMPTY */
2873 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2876 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2877 DSSERR("\trawval %#08x\n", val);
2878 dt = FLD_GET(val, 5, 0);
2879 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2880 u16 err = FLD_GET(val, 23, 8);
2881 dsi_show_rx_ack_with_err(err);
2882 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2883 DSSERR("\tDCS short response, 1 byte: %#x\n",
2884 FLD_GET(val, 23, 8));
2885 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2886 DSSERR("\tDCS short response, 2 byte: %#x\n",
2887 FLD_GET(val, 23, 8));
2888 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2889 DSSERR("\tDCS long response, len %d\n",
2890 FLD_GET(val, 23, 8));
2891 dsi_vc_flush_long_data(dsidev, channel);
2893 DSSERR("\tunknown datatype 0x%02x\n", dt);
2899 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2901 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2903 if (dsi->debug_write || dsi->debug_read)
2904 DSSDBG("dsi_vc_send_bta %d\n", channel);
2906 WARN_ON(!dsi_bus_is_locked(dsidev));
2908 /* RX_FIFO_NOT_EMPTY */
2909 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2910 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2911 dsi_vc_flush_receive_data(dsidev, channel);
2914 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2919 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2921 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2922 DECLARE_COMPLETION_ONSTACK(completion);
2926 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2927 &completion, DSI_VC_IRQ_BTA);
2931 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2932 DSI_IRQ_ERROR_MASK);
2936 r = dsi_vc_send_bta(dsidev, channel);
2940 if (wait_for_completion_timeout(&completion,
2941 msecs_to_jiffies(500)) == 0) {
2942 DSSERR("Failed to receive BTA\n");
2947 err = dsi_get_errors(dsidev);
2949 DSSERR("Error while sending BTA: %x\n", err);
2954 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2955 DSI_IRQ_ERROR_MASK);
2957 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2958 &completion, DSI_VC_IRQ_BTA);
2962 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2964 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2965 int channel, u8 data_type, u16 len, u8 ecc)
2967 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2971 WARN_ON(!dsi_bus_is_locked(dsidev));
2973 data_id = data_type | dsi->vc[channel].vc_id << 6;
2975 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2976 FLD_VAL(ecc, 31, 24);
2978 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2981 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2982 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2986 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2988 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2989 b1, b2, b3, b4, val); */
2991 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2994 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2995 u8 data_type, u8 *data, u16 len, u8 ecc)
2998 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3004 if (dsi->debug_write)
3005 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3008 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3009 DSSERR("unable to send long packet: packet too long.\n");
3013 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3015 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3018 for (i = 0; i < len >> 2; i++) {
3019 if (dsi->debug_write)
3020 DSSDBG("\tsending full packet %d\n", i);
3027 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3032 b1 = 0; b2 = 0; b3 = 0;
3034 if (dsi->debug_write)
3035 DSSDBG("\tsending remainder bytes %d\n", i);
3052 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3058 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3059 u8 data_type, u16 data, u8 ecc)
3061 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3065 WARN_ON(!dsi_bus_is_locked(dsidev));
3067 if (dsi->debug_write)
3068 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3070 data_type, data & 0xff, (data >> 8) & 0xff);
3072 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3074 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3075 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3079 data_id = data_type | dsi->vc[channel].vc_id << 6;
3081 r = (data_id << 0) | (data << 8) | (ecc << 24);
3083 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3088 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3090 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3092 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3095 EXPORT_SYMBOL(dsi_vc_send_null);
3097 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
3098 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3100 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3104 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3105 r = dsi_vc_send_short(dsidev, channel,
3106 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3107 } else if (len == 1) {
3108 r = dsi_vc_send_short(dsidev, channel,
3109 type == DSS_DSI_CONTENT_GENERIC ?
3110 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3111 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3112 } else if (len == 2) {
3113 r = dsi_vc_send_short(dsidev, channel,
3114 type == DSS_DSI_CONTENT_GENERIC ?
3115 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3116 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3117 data[0] | (data[1] << 8), 0);
3119 r = dsi_vc_send_long(dsidev, channel,
3120 type == DSS_DSI_CONTENT_GENERIC ?
3121 MIPI_DSI_GENERIC_LONG_WRITE :
3122 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3128 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3131 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3132 DSS_DSI_CONTENT_DCS);
3134 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3136 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3139 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3140 DSS_DSI_CONTENT_GENERIC);
3142 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3144 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3145 u8 *data, int len, enum dss_dsi_content_type type)
3147 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3150 r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3154 r = dsi_vc_send_bta_sync(dssdev, channel);
3158 /* RX_FIFO_NOT_EMPTY */
3159 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3160 DSSERR("rx fifo not empty after write, dumping data:\n");
3161 dsi_vc_flush_receive_data(dsidev, channel);
3168 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3169 channel, data[0], len);
3173 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3176 return dsi_vc_write_common(dssdev, channel, data, len,
3177 DSS_DSI_CONTENT_DCS);
3179 EXPORT_SYMBOL(dsi_vc_dcs_write);
3181 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3184 return dsi_vc_write_common(dssdev, channel, data, len,
3185 DSS_DSI_CONTENT_GENERIC);
3187 EXPORT_SYMBOL(dsi_vc_generic_write);
3189 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3191 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3193 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3195 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3197 return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3199 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3201 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3207 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3209 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3211 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3214 return dsi_vc_generic_write(dssdev, channel, ¶m, 1);
3216 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3218 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3219 u8 param1, u8 param2)
3224 return dsi_vc_generic_write(dssdev, channel, buf, 2);
3226 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3228 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3229 int channel, u8 dcs_cmd)
3231 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3232 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3235 if (dsi->debug_read)
3236 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3239 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3241 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3242 " failed\n", channel, dcs_cmd);
3249 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3250 int channel, u8 *reqdata, int reqlen)
3252 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3253 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3258 if (dsi->debug_read)
3259 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3263 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3265 } else if (reqlen == 1) {
3266 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3268 } else if (reqlen == 2) {
3269 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3270 data = reqdata[0] | (reqdata[1] << 8);
3275 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3277 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3278 " failed\n", channel, reqlen);
3285 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3286 u8 *buf, int buflen, enum dss_dsi_content_type type)
3288 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3293 /* RX_FIFO_NOT_EMPTY */
3294 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3295 DSSERR("RX fifo empty when trying to read.\n");
3300 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3301 if (dsi->debug_read)
3302 DSSDBG("\theader: %08x\n", val);
3303 dt = FLD_GET(val, 5, 0);
3304 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3305 u16 err = FLD_GET(val, 23, 8);
3306 dsi_show_rx_ack_with_err(err);
3310 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3311 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3312 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3313 u8 data = FLD_GET(val, 15, 8);
3314 if (dsi->debug_read)
3315 DSSDBG("\t%s short response, 1 byte: %02x\n",
3316 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3327 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3328 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3329 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3330 u16 data = FLD_GET(val, 23, 8);
3331 if (dsi->debug_read)
3332 DSSDBG("\t%s short response, 2 byte: %04x\n",
3333 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3341 buf[0] = data & 0xff;
3342 buf[1] = (data >> 8) & 0xff;
3345 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3346 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3347 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3349 int len = FLD_GET(val, 23, 8);
3350 if (dsi->debug_read)
3351 DSSDBG("\t%s long response, len %d\n",
3352 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3360 /* two byte checksum ends the packet, not included in len */
3361 for (w = 0; w < len + 2;) {
3363 val = dsi_read_reg(dsidev,
3364 DSI_VC_SHORT_PACKET_HEADER(channel));
3365 if (dsi->debug_read)
3366 DSSDBG("\t\t%02x %02x %02x %02x\n",
3370 (val >> 24) & 0xff);
3372 for (b = 0; b < 4; ++b) {
3374 buf[w] = (val >> (b * 8)) & 0xff;
3375 /* we discard the 2 byte checksum */
3382 DSSERR("\tunknown datatype 0x%02x\n", dt);
3389 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3390 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3395 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3396 u8 *buf, int buflen)
3398 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3401 r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3405 r = dsi_vc_send_bta_sync(dssdev, channel);
3409 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3410 DSS_DSI_CONTENT_DCS);
3421 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3424 EXPORT_SYMBOL(dsi_vc_dcs_read);
3426 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3427 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3429 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3432 r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3436 r = dsi_vc_send_bta_sync(dssdev, channel);
3440 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3441 DSS_DSI_CONTENT_GENERIC);
3453 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3458 r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3460 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3466 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3468 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3469 u8 *buf, int buflen)
3473 r = dsi_vc_generic_read(dssdev, channel, ¶m, 1, buf, buflen);
3475 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3481 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3483 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3484 u8 param1, u8 param2, u8 *buf, int buflen)
3489 reqdata[0] = param1;
3490 reqdata[1] = param2;
3492 r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3494 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3500 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3502 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3505 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3507 return dsi_vc_send_short(dsidev, channel,
3508 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3510 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3512 static int dsi_enter_ulps(struct platform_device *dsidev)
3514 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3515 DECLARE_COMPLETION_ONSTACK(completion);
3520 WARN_ON(!dsi_bus_is_locked(dsidev));
3522 WARN_ON(dsi->ulps_enabled);
3524 if (dsi->ulps_enabled)
3527 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3528 DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
3532 dsi_sync_vc(dsidev, 0);
3533 dsi_sync_vc(dsidev, 1);
3534 dsi_sync_vc(dsidev, 2);
3535 dsi_sync_vc(dsidev, 3);
3537 dsi_force_tx_stop_mode_io(dsidev);
3539 dsi_vc_enable(dsidev, 0, false);
3540 dsi_vc_enable(dsidev, 1, false);
3541 dsi_vc_enable(dsidev, 2, false);
3542 dsi_vc_enable(dsidev, 3, false);
3544 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3545 DSSERR("HS busy when enabling ULPS\n");
3549 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3550 DSSERR("LP busy when enabling ULPS\n");
3554 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3555 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3559 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3560 /* LANEx_ULPS_SIG2 */
3561 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
3564 if (wait_for_completion_timeout(&completion,
3565 msecs_to_jiffies(1000)) == 0) {
3566 DSSERR("ULPS enable timeout\n");
3571 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3572 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3574 /* Reset LANEx_ULPS_SIG2 */
3575 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2),
3578 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3580 dsi_if_enable(dsidev, false);
3582 dsi->ulps_enabled = true;
3587 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3588 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3592 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3593 unsigned ticks, bool x4, bool x16)
3596 unsigned long total_ticks;
3599 BUG_ON(ticks > 0x1fff);
3601 /* ticks in DSI_FCK */
3602 fck = dsi_fclk_rate(dsidev);
3604 r = dsi_read_reg(dsidev, DSI_TIMING2);
3605 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3606 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3607 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3608 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3609 dsi_write_reg(dsidev, DSI_TIMING2, r);
3611 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3613 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3615 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3616 (total_ticks * 1000) / (fck / 1000 / 1000));
3619 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3623 unsigned long total_ticks;
3626 BUG_ON(ticks > 0x1fff);
3628 /* ticks in DSI_FCK */
3629 fck = dsi_fclk_rate(dsidev);
3631 r = dsi_read_reg(dsidev, DSI_TIMING1);
3632 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3633 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3634 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3635 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3636 dsi_write_reg(dsidev, DSI_TIMING1, r);
3638 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3640 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3642 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3643 (total_ticks * 1000) / (fck / 1000 / 1000));
3646 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3647 unsigned ticks, bool x4, bool x16)
3650 unsigned long total_ticks;
3653 BUG_ON(ticks > 0x1fff);
3655 /* ticks in DSI_FCK */
3656 fck = dsi_fclk_rate(dsidev);
3658 r = dsi_read_reg(dsidev, DSI_TIMING1);
3659 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3660 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3661 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3662 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3663 dsi_write_reg(dsidev, DSI_TIMING1, r);
3665 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3667 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3669 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3670 (total_ticks * 1000) / (fck / 1000 / 1000));
3673 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3674 unsigned ticks, bool x4, bool x16)
3677 unsigned long total_ticks;
3680 BUG_ON(ticks > 0x1fff);
3682 /* ticks in TxByteClkHS */
3683 fck = dsi_get_txbyteclkhs(dsidev);
3685 r = dsi_read_reg(dsidev, DSI_TIMING2);
3686 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3687 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3688 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3689 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3690 dsi_write_reg(dsidev, DSI_TIMING2, r);
3692 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3694 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3696 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3697 (total_ticks * 1000) / (fck / 1000 / 1000));
3700 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3702 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3703 int num_line_buffers;
3705 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3706 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3707 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3708 struct omap_video_timings *timings = &dssdev->panel.timings;
3710 * Don't use line buffers if width is greater than the video
3711 * port's line buffer size
3713 if (line_buf_size <= timings->x_res * bpp / 8)
3714 num_line_buffers = 0;
3716 num_line_buffers = 2;
3718 /* Use maximum number of line buffers in command mode */
3719 num_line_buffers = 2;
3723 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3726 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3728 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3729 int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3730 int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3731 int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3732 bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3733 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3736 r = dsi_read_reg(dsidev, DSI_CTRL);
3737 r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */
3738 r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */
3739 r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */
3740 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3741 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
3742 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3743 r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */
3744 dsi_write_reg(dsidev, DSI_CTRL, r);
3747 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3749 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3750 int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3751 int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3752 int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3753 int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3757 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3758 * 1 = Long blanking packets are sent in corresponding blanking periods
3760 r = dsi_read_reg(dsidev, DSI_CTRL);
3761 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3762 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3763 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3764 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3765 dsi_write_reg(dsidev, DSI_CTRL, r);
3768 static int dsi_proto_config(struct omap_dss_device *dssdev)
3770 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3774 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3779 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3784 /* XXX what values for the timeouts? */
3785 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3786 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3787 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3788 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3790 switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3804 r = dsi_read_reg(dsidev, DSI_CTRL);
3805 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3806 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3807 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3808 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3809 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3810 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3811 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3812 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3813 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3814 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3815 /* DCS_CMD_CODE, 1=start, 0=continue */
3816 r = FLD_MOD(r, 0, 25, 25);
3819 dsi_write_reg(dsidev, DSI_CTRL, r);
3821 dsi_config_vp_num_line_buffers(dssdev);
3823 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3824 dsi_config_vp_sync_events(dssdev);
3825 dsi_config_blanking_modes(dssdev);
3828 dsi_vc_initial_config(dsidev, 0);
3829 dsi_vc_initial_config(dsidev, 1);
3830 dsi_vc_initial_config(dsidev, 2);
3831 dsi_vc_initial_config(dsidev, 3);
3836 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3838 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3839 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3840 unsigned tclk_pre, tclk_post;
3841 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3842 unsigned ths_trail, ths_exit;
3843 unsigned ddr_clk_pre, ddr_clk_post;
3844 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3846 int ndl = dsi_get_num_data_lanes_dssdev(dssdev);
3849 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3850 ths_prepare = FLD_GET(r, 31, 24);
3851 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3852 ths_zero = ths_prepare_ths_zero - ths_prepare;
3853 ths_trail = FLD_GET(r, 15, 8);
3854 ths_exit = FLD_GET(r, 7, 0);
3856 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3857 tlpx = FLD_GET(r, 22, 16) * 2;
3858 tclk_trail = FLD_GET(r, 15, 8);
3859 tclk_zero = FLD_GET(r, 7, 0);
3861 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3862 tclk_prepare = FLD_GET(r, 7, 0);
3866 /* min 60ns + 52*UI */
3867 tclk_post = ns2ddr(dsidev, 60) + 26;
3869 ths_eot = DIV_ROUND_UP(4, ndl);
3871 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3873 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3875 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3876 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3878 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3879 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3880 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3881 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3883 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3887 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3888 DIV_ROUND_UP(ths_prepare, 4) +
3889 DIV_ROUND_UP(ths_zero + 3, 4);
3891 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3893 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3894 FLD_VAL(exit_hs_mode_lat, 15, 0);
3895 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3897 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3898 enter_hs_mode_lat, exit_hs_mode_lat);
3900 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3901 /* TODO: Implement a video mode check_timings function */
3902 int hsa = dssdev->panel.dsi_vm_data.hsa;
3903 int hfp = dssdev->panel.dsi_vm_data.hfp;
3904 int hbp = dssdev->panel.dsi_vm_data.hbp;
3905 int vsa = dssdev->panel.dsi_vm_data.vsa;
3906 int vfp = dssdev->panel.dsi_vm_data.vfp;
3907 int vbp = dssdev->panel.dsi_vm_data.vbp;
3908 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3909 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3910 struct omap_video_timings *timings = &dssdev->panel.timings;
3911 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3912 int tl, t_he, width_bytes;
3915 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3917 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3919 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3920 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3921 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3923 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3924 hfp, hsync_end ? hsa : 0, tl);
3925 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3926 vsa, timings->y_res);
3928 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3929 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3930 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3931 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3932 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3934 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3935 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3936 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3937 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3938 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3939 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3941 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3942 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3943 r = FLD_MOD(r, tl, 31, 16); /* TL */
3944 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3948 int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel)
3950 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3951 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3955 switch (dssdev->panel.dsi_pix_fmt) {
3956 case OMAP_DSS_DSI_FMT_RGB888:
3957 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3959 case OMAP_DSS_DSI_FMT_RGB666:
3960 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3962 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3963 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3965 case OMAP_DSS_DSI_FMT_RGB565:
3966 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3972 dsi_if_enable(dsidev, false);
3973 dsi_vc_enable(dsidev, channel, false);
3975 /* MODE, 1 = video mode */
3976 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3978 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
3980 dsi_vc_write_long_header(dsidev, channel, data_type, word_count, 0);
3982 dsi_vc_enable(dsidev, channel, true);
3983 dsi_if_enable(dsidev, true);
3985 dssdev->manager->enable(dssdev->manager);
3989 EXPORT_SYMBOL(dsi_video_mode_enable);
3991 void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel)
3993 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3995 dsi_if_enable(dsidev, false);
3996 dsi_vc_enable(dsidev, channel, false);
3998 /* MODE, 0 = command mode */
3999 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4001 dsi_vc_enable(dsidev, channel, true);
4002 dsi_if_enable(dsidev, true);
4004 dssdev->manager->disable(dssdev->manager);
4006 EXPORT_SYMBOL(dsi_video_mode_disable);
4008 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
4009 u16 x, u16 y, u16 w, u16 h)
4011 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4012 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4017 unsigned packet_payload;
4018 unsigned packet_len;
4021 const unsigned channel = dsi->update_channel;
4022 const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4024 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
4027 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4029 bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4030 bytespl = w * bytespp;
4031 bytespf = bytespl * h;
4033 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4034 * number of lines in a packet. See errata about VP_CLK_RATIO */
4036 if (bytespf < line_buf_size)
4037 packet_payload = bytespf;
4039 packet_payload = (line_buf_size) / bytespl * bytespl;
4041 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4042 total_len = (bytespf / packet_payload) * packet_len;
4044 if (bytespf % packet_payload)
4045 total_len += (bytespf % packet_payload) + 1;
4047 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4048 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4050 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4053 if (dsi->te_enabled)
4054 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4056 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4057 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4059 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4060 * because DSS interrupts are not capable of waking up the CPU and the
4061 * framedone interrupt could be delayed for quite a long time. I think
4062 * the same goes for any DSS interrupts, but for some reason I have not
4063 * seen the problem anywhere else than here.
4065 dispc_disable_sidle();
4067 dsi_perf_mark_start(dsidev);
4069 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4070 msecs_to_jiffies(250));
4073 dss_start_update(dssdev);
4075 if (dsi->te_enabled) {
4076 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4077 * for TE is longer than the timer allows */
4078 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4080 dsi_vc_send_bta(dsidev, channel);
4082 #ifdef DSI_CATCH_MISSING_TE
4083 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4088 #ifdef DSI_CATCH_MISSING_TE
4089 static void dsi_te_timeout(unsigned long arg)
4091 DSSERR("TE not received for 250ms!\n");
4095 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4097 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4099 /* SIDLEMODE back to smart-idle */
4100 dispc_enable_sidle();
4102 if (dsi->te_enabled) {
4103 /* enable LP_RX_TO again after the TE */
4104 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4107 dsi->framedone_callback(error, dsi->framedone_data);
4110 dsi_perf_show(dsidev, "DISPC");
4113 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4115 struct dsi_data *dsi = container_of(work, struct dsi_data,
4116 framedone_timeout_work.work);
4117 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4118 * 250ms which would conflict with this timeout work. What should be
4119 * done is first cancel the transfer on the HW, and then cancel the
4120 * possibly scheduled framedone work. However, cancelling the transfer
4121 * on the HW is buggy, and would probably require resetting the whole
4124 DSSERR("Framedone not received for 250ms!\n");
4126 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4129 static void dsi_framedone_irq_callback(void *data, u32 mask)
4131 struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4132 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4133 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4135 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4136 * turns itself off. However, DSI still has the pixels in its buffers,
4137 * and is sending the data.
4140 __cancel_delayed_work(&dsi->framedone_timeout_work);
4142 dsi_handle_framedone(dsidev, 0);
4144 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
4145 dispc_fake_vsync_irq();
4149 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
4150 u16 *x, u16 *y, u16 *w, u16 *h,
4151 bool enlarge_update_area)
4153 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4156 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4158 if (*x > dw || *y > dh)
4170 if (*w == 0 || *h == 0)
4173 dsi_perf_mark_setup(dsidev);
4175 dss_setup_partial_planes(dssdev, x, y, w, h,
4176 enlarge_update_area);
4177 dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h);
4181 EXPORT_SYMBOL(omap_dsi_prepare_update);
4183 int omap_dsi_update(struct omap_dss_device *dssdev,
4185 u16 x, u16 y, u16 w, u16 h,
4186 void (*callback)(int, void *), void *data)
4188 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4189 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4191 dsi->update_channel = channel;
4193 /* OMAP DSS cannot send updates of odd widths.
4194 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
4195 * here to make sure we catch erroneous updates. Otherwise we'll only
4196 * see rather obscure HW error happening, as DSS halts. */
4199 dsi->framedone_callback = callback;
4200 dsi->framedone_data = data;
4202 dsi->update_region.x = x;
4203 dsi->update_region.y = y;
4204 dsi->update_region.w = w;
4205 dsi->update_region.h = h;
4206 dsi->update_region.device = dssdev;
4208 dsi_update_screen_dispc(dssdev, x, y, w, h);
4212 EXPORT_SYMBOL(omap_dsi_update);
4216 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4220 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4222 struct omap_video_timings timings = {
4231 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4232 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4234 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4235 (void *) dssdev, irq);
4237 DSSERR("can't get FRAMEDONE irq\n");
4241 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4242 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4244 dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
4246 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4247 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4249 dispc_mgr_set_lcd_timings(dssdev->manager->id,
4250 &dssdev->panel.timings);
4253 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4254 OMAP_DSS_LCD_DISPLAY_TFT);
4255 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4256 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4260 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4262 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4265 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4266 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4268 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4269 (void *) dssdev, irq);
4273 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4275 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4276 struct dsi_clock_info cinfo;
4279 /* we always use DSS_CLK_SYSCK as input clock */
4280 cinfo.use_sys_clk = true;
4281 cinfo.regn = dssdev->clocks.dsi.regn;
4282 cinfo.regm = dssdev->clocks.dsi.regm;
4283 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4284 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4285 r = dsi_calc_clock_rates(dssdev, &cinfo);
4287 DSSERR("Failed to calc dsi clocks\n");
4291 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4293 DSSERR("Failed to set dsi clocks\n");
4300 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4302 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4303 struct dispc_clock_info dispc_cinfo;
4305 unsigned long long fck;
4307 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4309 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4310 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4312 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4314 DSSERR("Failed to calc dispc clocks\n");
4318 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4320 DSSERR("Failed to set dispc clocks\n");
4327 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4329 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4330 int dsi_module = dsi_get_dsidev_id(dsidev);
4333 r = dsi_pll_init(dsidev, true, true);
4337 r = dsi_configure_dsi_clocks(dssdev);
4341 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4342 dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4343 dss_select_lcd_clk_source(dssdev->manager->id,
4344 dssdev->clocks.dispc.channel.lcd_clk_src);
4348 r = dsi_configure_dispc_clocks(dssdev);
4352 r = dsi_cio_init(dssdev);
4356 _dsi_print_reset_status(dsidev);
4358 dsi_proto_timings(dssdev);
4359 dsi_set_lp_clk_divisor(dssdev);
4362 _dsi_print_reset_status(dsidev);
4364 r = dsi_proto_config(dssdev);
4368 /* enable interface */
4369 dsi_vc_enable(dsidev, 0, 1);
4370 dsi_vc_enable(dsidev, 1, 1);
4371 dsi_vc_enable(dsidev, 2, 1);
4372 dsi_vc_enable(dsidev, 3, 1);
4373 dsi_if_enable(dsidev, 1);
4374 dsi_force_tx_stop_mode_io(dsidev);
4378 dsi_cio_uninit(dssdev);
4380 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4381 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4382 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4385 dsi_pll_uninit(dsidev, true);
4390 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4391 bool disconnect_lanes, bool enter_ulps)
4393 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4394 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4395 int dsi_module = dsi_get_dsidev_id(dsidev);
4397 if (enter_ulps && !dsi->ulps_enabled)
4398 dsi_enter_ulps(dsidev);
4400 /* disable interface */
4401 dsi_if_enable(dsidev, 0);
4402 dsi_vc_enable(dsidev, 0, 0);
4403 dsi_vc_enable(dsidev, 1, 0);
4404 dsi_vc_enable(dsidev, 2, 0);
4405 dsi_vc_enable(dsidev, 3, 0);
4407 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4408 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4409 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4410 dsi_cio_uninit(dssdev);
4411 dsi_pll_uninit(dsidev, disconnect_lanes);
4414 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4416 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4417 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4420 DSSDBG("dsi_display_enable\n");
4422 WARN_ON(!dsi_bus_is_locked(dsidev));
4424 mutex_lock(&dsi->lock);
4426 if (dssdev->manager == NULL) {
4427 DSSERR("failed to enable display: no manager\n");
4432 r = omap_dss_start_device(dssdev);
4434 DSSERR("failed to start device\n");
4438 r = dsi_runtime_get(dsidev);
4442 dsi_enable_pll_clock(dsidev, 1);
4444 _dsi_initialize_irq(dsidev);
4446 r = dsi_display_init_dispc(dssdev);
4448 goto err_init_dispc;
4450 r = dsi_display_init_dsi(dssdev);
4454 mutex_unlock(&dsi->lock);
4459 dsi_display_uninit_dispc(dssdev);
4461 dsi_enable_pll_clock(dsidev, 0);
4462 dsi_runtime_put(dsidev);
4464 omap_dss_stop_device(dssdev);
4466 mutex_unlock(&dsi->lock);
4467 DSSDBG("dsi_display_enable FAILED\n");
4470 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4472 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4473 bool disconnect_lanes, bool enter_ulps)
4475 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4476 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4478 DSSDBG("dsi_display_disable\n");
4480 WARN_ON(!dsi_bus_is_locked(dsidev));
4482 mutex_lock(&dsi->lock);
4484 dsi_sync_vc(dsidev, 0);
4485 dsi_sync_vc(dsidev, 1);
4486 dsi_sync_vc(dsidev, 2);
4487 dsi_sync_vc(dsidev, 3);
4489 dsi_display_uninit_dispc(dssdev);
4491 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4493 dsi_runtime_put(dsidev);
4494 dsi_enable_pll_clock(dsidev, 0);
4496 omap_dss_stop_device(dssdev);
4498 mutex_unlock(&dsi->lock);
4500 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4502 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4504 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4505 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4507 dsi->te_enabled = enable;
4510 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4512 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4513 u32 fifo_size, u32 burst_size,
4514 u32 *fifo_low, u32 *fifo_high)
4516 *fifo_high = fifo_size - burst_size;
4517 *fifo_low = fifo_size - burst_size * 2;
4520 int dsi_init_display(struct omap_dss_device *dssdev)
4522 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4523 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4524 int dsi_module = dsi_get_dsidev_id(dsidev);
4526 DSSDBG("DSI init\n");
4528 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4529 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4530 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4533 if (dsi->vdds_dsi_reg == NULL) {
4534 struct regulator *vdds_dsi;
4536 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4538 if (IS_ERR(vdds_dsi)) {
4539 DSSERR("can't get VDDS_DSI regulator\n");
4540 return PTR_ERR(vdds_dsi);
4543 dsi->vdds_dsi_reg = vdds_dsi;
4546 if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) {
4547 DSSERR("DSI%d can't support more than %d data lanes\n",
4548 dsi_module + 1, dsi->num_data_lanes);
4555 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4557 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4558 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4561 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4562 if (!dsi->vc[i].dssdev) {
4563 dsi->vc[i].dssdev = dssdev;
4569 DSSERR("cannot get VC for display %s", dssdev->name);
4572 EXPORT_SYMBOL(omap_dsi_request_vc);
4574 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4576 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4577 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4579 if (vc_id < 0 || vc_id > 3) {
4580 DSSERR("VC ID out of range\n");
4584 if (channel < 0 || channel > 3) {
4585 DSSERR("Virtual Channel out of range\n");
4589 if (dsi->vc[channel].dssdev != dssdev) {
4590 DSSERR("Virtual Channel not allocated to display %s\n",
4595 dsi->vc[channel].vc_id = vc_id;
4599 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4601 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4603 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4604 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4606 if ((channel >= 0 && channel <= 3) &&
4607 dsi->vc[channel].dssdev == dssdev) {
4608 dsi->vc[channel].dssdev = NULL;
4609 dsi->vc[channel].vc_id = 0;
4612 EXPORT_SYMBOL(omap_dsi_release_vc);
4614 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4616 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4617 DSSERR("%s (%s) not active\n",
4618 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4619 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4622 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4624 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4625 DSSERR("%s (%s) not active\n",
4626 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4627 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4630 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4632 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4634 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4635 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4636 dsi->regm_dispc_max =
4637 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4638 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4639 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4640 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4641 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4644 static int dsi_get_clocks(struct platform_device *dsidev)
4646 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4649 clk = clk_get(&dsidev->dev, "fck");
4651 DSSERR("can't get fck\n");
4652 return PTR_ERR(clk);
4657 clk = clk_get(&dsidev->dev, "sys_clk");
4659 DSSERR("can't get sys_clk\n");
4660 clk_put(dsi->dss_clk);
4661 dsi->dss_clk = NULL;
4662 return PTR_ERR(clk);
4670 static void dsi_put_clocks(struct platform_device *dsidev)
4672 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4675 clk_put(dsi->dss_clk);
4677 clk_put(dsi->sys_clk);
4680 /* DSI1 HW IP initialisation */
4681 static int omap_dsihw_probe(struct platform_device *dsidev)
4683 struct omap_display_platform_data *dss_plat_data;
4684 struct omap_dss_board_info *board_info;
4686 int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4687 struct resource *dsi_mem;
4688 struct dsi_data *dsi;
4690 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4697 dsi_pdev_map[dsi_module] = dsidev;
4698 dev_set_drvdata(&dsidev->dev, dsi);
4700 dss_plat_data = dsidev->dev.platform_data;
4701 board_info = dss_plat_data->board_data;
4702 dsi->enable_pads = board_info->dsi_enable_pads;
4703 dsi->disable_pads = board_info->dsi_disable_pads;
4705 spin_lock_init(&dsi->irq_lock);
4706 spin_lock_init(&dsi->errors_lock);
4709 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4710 spin_lock_init(&dsi->irq_stats_lock);
4711 dsi->irq_stats.last_reset = jiffies;
4714 mutex_init(&dsi->lock);
4715 sema_init(&dsi->bus_lock, 1);
4717 r = dsi_get_clocks(dsidev);
4721 pm_runtime_enable(&dsidev->dev);
4723 INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4724 dsi_framedone_timeout_work_callback);
4726 #ifdef DSI_CATCH_MISSING_TE
4727 init_timer(&dsi->te_timer);
4728 dsi->te_timer.function = dsi_te_timeout;
4729 dsi->te_timer.data = 0;
4731 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4733 DSSERR("can't get IORESOURCE_MEM DSI\n");
4737 dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
4739 DSSERR("can't ioremap DSI\n");
4743 dsi->irq = platform_get_irq(dsi->pdev, 0);
4745 DSSERR("platform_get_irq failed\n");
4750 r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
4751 dev_name(&dsidev->dev), dsi->pdev);
4753 DSSERR("request_irq failed\n");
4757 /* DSI VCs initialization */
4758 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4759 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4760 dsi->vc[i].dssdev = NULL;
4761 dsi->vc[i].vc_id = 0;
4764 dsi_calc_clock_param_ranges(dsidev);
4766 r = dsi_runtime_get(dsidev);
4770 rev = dsi_read_reg(dsidev, DSI_REVISION);
4771 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4772 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4774 dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev);
4776 dsi_runtime_put(dsidev);
4781 free_irq(dsi->irq, dsi->pdev);
4785 pm_runtime_disable(&dsidev->dev);
4792 static int omap_dsihw_remove(struct platform_device *dsidev)
4794 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4796 WARN_ON(dsi->scp_clk_refcount > 0);
4798 pm_runtime_disable(&dsidev->dev);
4800 dsi_put_clocks(dsidev);
4802 if (dsi->vdds_dsi_reg != NULL) {
4803 if (dsi->vdds_dsi_enabled) {
4804 regulator_disable(dsi->vdds_dsi_reg);
4805 dsi->vdds_dsi_enabled = false;
4808 regulator_put(dsi->vdds_dsi_reg);
4809 dsi->vdds_dsi_reg = NULL;
4812 free_irq(dsi->irq, dsi->pdev);
4820 static int dsi_runtime_suspend(struct device *dev)
4822 dispc_runtime_put();
4828 static int dsi_runtime_resume(struct device *dev)
4832 r = dss_runtime_get();
4836 r = dispc_runtime_get();
4848 static const struct dev_pm_ops dsi_pm_ops = {
4849 .runtime_suspend = dsi_runtime_suspend,
4850 .runtime_resume = dsi_runtime_resume,
4853 static struct platform_driver omap_dsihw_driver = {
4854 .probe = omap_dsihw_probe,
4855 .remove = omap_dsihw_remove,
4857 .name = "omapdss_dsi",
4858 .owner = THIS_MODULE,
4863 int dsi_init_platform_driver(void)
4865 return platform_driver_register(&omap_dsihw_driver);
4868 void dsi_uninit_platform_driver(void)
4870 return platform_driver_unregister(&omap_dsihw_driver);