1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
4 * Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 **************************************************************************/
25 #define PSB_NUM_PIPE 3
27 #define PSB_GPU_ACCESS_READ (1ULL << 32)
28 #define PSB_GPU_ACCESS_WRITE (1ULL << 33)
29 #define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)
31 #define PSB_BO_FLAG_COMMAND (1ULL << 52)
34 * Feedback components:
37 struct drm_psb_sizes_arg {
46 struct drm_psb_dpst_lut_arg {
51 #define PSB_DC_CRTC_SAVE 0x01
52 #define PSB_DC_CRTC_RESTORE 0x02
53 #define PSB_DC_OUTPUT_SAVE 0x04
54 #define PSB_DC_OUTPUT_RESTORE 0x08
55 #define PSB_DC_CRTC_MASK 0x03
56 #define PSB_DC_OUTPUT_MASK 0x0C
58 struct drm_psb_dc_state_arg {
63 struct drm_psb_mode_operation_arg {
66 struct drm_mode_modeinfo mode;
70 struct drm_psb_stolen_memory_arg {
75 /*Display Register Bits*/
76 #define REGRWBITS_PFIT_CONTROLS (1 << 0)
77 #define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1)
78 #define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2)
79 #define REGRWBITS_PIPEASRC (1 << 3)
80 #define REGRWBITS_PIPEBSRC (1 << 4)
81 #define REGRWBITS_VTOTAL_A (1 << 5)
82 #define REGRWBITS_VTOTAL_B (1 << 6)
83 #define REGRWBITS_DSPACNTR (1 << 8)
84 #define REGRWBITS_DSPBCNTR (1 << 9)
85 #define REGRWBITS_DSPCCNTR (1 << 10)
87 /*Overlay Register Bits*/
88 #define OV_REGRWBITS_OVADD (1 << 0)
89 #define OV_REGRWBITS_OGAM_ALL (1 << 1)
91 #define OVC_REGRWBITS_OVADD (1 << 2)
92 #define OVC_REGRWBITS_OGAM_ALL (1 << 3)
94 struct drm_psb_register_rw_arg {
97 u32 display_read_mask;
98 u32 display_write_mask;
102 u32 pfit_autoscale_ratios;
103 u32 pfit_programmed_scale_ratios;
110 u32 overlay_read_mask;
111 u32 overlay_write_mask;
123 u32 IEP_BSSCC_CONTROL;
127 u32 sprite_enable_mask;
128 u32 sprite_disable_mask;
137 u32 dspc_linear_offset;
142 u32 subpicture_enable_mask;
143 u32 subpicture_disable_mask;
146 /* Controlling the kernel modesetting buffers */
148 #define DRM_PSB_KMS_OFF 0x00
149 #define DRM_PSB_KMS_ON 0x01
150 #define DRM_PSB_SIZES 0x07
151 #define DRM_PSB_FUSE_REG 0x08
152 #define DRM_PSB_DC_STATE 0x0A
153 #define DRM_PSB_ADB 0x0B
154 #define DRM_PSB_MODE_OPERATION 0x0C
155 #define DRM_PSB_STOLEN_MEMORY 0x0D
156 #define DRM_PSB_REGISTER_RW 0x0E
159 * NOTE: Add new commands here, but increment
160 * the values below and increment their
161 * corresponding defines where they're
164 #define DRM_PVR_RESERVED1 0x12
165 #define DRM_PVR_RESERVED2 0x13
166 #define DRM_PVR_RESERVED3 0x14
167 #define DRM_PVR_RESERVED4 0x15
168 #define DRM_PVR_RESERVED5 0x16
170 #define DRM_PSB_DPST 0x1B
171 #define DRM_PSB_GAMMA 0x1C
172 #define DRM_PSB_DPST_BL 0x1D
174 #define DRM_PVR_RESERVED6 0x1E
176 #define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F
178 #define PSB_MODE_OPERATION_MODE_VALID 0x01
179 #define PSB_MODE_OPERATION_SET_DC_BASE 0x02
181 struct drm_psb_get_pipe_from_crtc_id_arg {
182 /** ID of CRTC being requested **/
185 /** pipe of requested CRTC **/