1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <net/mac80211.h>
33 #include "iwl-eeprom.h"
38 #include "iwl-helpers.h"
40 static const u16 default_tid_to_tx_fifo[] = {
60 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
61 struct iwl_dma_ptr *ptr, size_t size)
63 ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
70 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
71 struct iwl_dma_ptr *ptr)
73 if (unlikely(!ptr->addr))
76 pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
77 memset(ptr, 0, sizeof(*ptr));
81 * iwl_txq_update_write_ptr - Send new write index to hardware
83 int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
87 int txq_id = txq->q.id;
89 if (txq->need_update == 0)
92 /* if we're trying to save power */
93 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
94 /* wake up nic if it's powered down ...
95 * uCode will wake up, and interrupt us again, so next
96 * time we'll skip this part. */
97 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
99 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
100 IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
102 iwl_set_bit(priv, CSR_GP_CNTRL,
103 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
107 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
108 txq->q.write_ptr | (txq_id << 8));
110 /* else not in power-save mode, uCode will never sleep when we're
111 * trying to tx (during RFKILL, we're not trying to tx). */
113 iwl_write32(priv, HBUS_TARG_WRPTR,
114 txq->q.write_ptr | (txq_id << 8));
116 txq->need_update = 0;
120 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
124 * iwl_tx_queue_free - Deallocate DMA queue.
125 * @txq: Transmit queue to deallocate.
127 * Empty queue by removing and destroying all BD's.
129 * 0-fill, but do not free "txq" descriptor structure.
131 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
133 struct iwl_tx_queue *txq = &priv->txq[txq_id];
134 struct iwl_queue *q = &txq->q;
135 struct pci_dev *dev = priv->pci_dev;
141 /* first, empty all BD's */
142 for (; q->write_ptr != q->read_ptr;
143 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
144 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
146 /* De-alloc array of command/tx buffers */
147 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
150 /* De-alloc circular buffer of TFDs */
152 pci_free_consistent(dev, priv->hw_params.tfd_size *
153 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
155 /* De-alloc array of per-TFD driver data */
159 /* deallocate arrays */
165 /* 0-fill queue descriptor structure */
166 memset(txq, 0, sizeof(*txq));
168 EXPORT_SYMBOL(iwl_tx_queue_free);
171 * iwl_cmd_queue_free - Deallocate DMA queue.
172 * @txq: Transmit queue to deallocate.
174 * Empty queue by removing and destroying all BD's.
176 * 0-fill, but do not free "txq" descriptor structure.
178 void iwl_cmd_queue_free(struct iwl_priv *priv)
180 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
181 struct iwl_queue *q = &txq->q;
182 struct pci_dev *dev = priv->pci_dev;
188 /* De-alloc array of command/tx buffers */
189 for (i = 0; i <= TFD_CMD_SLOTS; i++)
192 /* De-alloc circular buffer of TFDs */
194 pci_free_consistent(dev, priv->hw_params.tfd_size *
195 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
197 /* deallocate arrays */
203 /* 0-fill queue descriptor structure */
204 memset(txq, 0, sizeof(*txq));
206 EXPORT_SYMBOL(iwl_cmd_queue_free);
208 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
211 * Theory of operation
213 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
214 * of buffer descriptors, each of which points to one or more data buffers for
215 * the device to read from or fill. Driver and device exchange status of each
216 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
217 * entries in each circular buffer, to protect against confusing empty and full
220 * The device reads or writes the data in the queues via the device's several
221 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
223 * For Tx queue, there are low mark and high mark limits. If, after queuing
224 * the packet for Tx, free space become < low mark, Tx queue stopped. When
225 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
228 * See more detailed info in iwl-4965-hw.h.
229 ***************************************************/
231 int iwl_queue_space(const struct iwl_queue *q)
233 int s = q->read_ptr - q->write_ptr;
235 if (q->read_ptr > q->write_ptr)
240 /* keep some reserve to not confuse empty and full situations */
246 EXPORT_SYMBOL(iwl_queue_space);
250 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
252 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
253 int count, int slots_num, u32 id)
256 q->n_window = slots_num;
259 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
260 * and iwl_queue_dec_wrap are broken. */
261 BUG_ON(!is_power_of_2(count));
263 /* slots_num must be power-of-two size, otherwise
264 * get_cmd_index is broken. */
265 BUG_ON(!is_power_of_2(slots_num));
267 q->low_mark = q->n_window / 4;
271 q->high_mark = q->n_window / 8;
272 if (q->high_mark < 2)
275 q->write_ptr = q->read_ptr = 0;
281 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
283 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
284 struct iwl_tx_queue *txq, u32 id)
286 struct pci_dev *dev = priv->pci_dev;
287 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
289 /* Driver private data, only for Tx (not command) queues,
290 * not shared with device. */
291 if (id != IWL_CMD_QUEUE_NUM) {
292 txq->txb = kmalloc(sizeof(txq->txb[0]) *
293 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
295 IWL_ERR(priv, "kmalloc for auxiliary BD "
296 "structures failed\n");
303 /* Circular buffer of transmit frame descriptors (TFDs),
304 * shared with device */
305 txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr);
308 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
323 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
325 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
326 int slots_num, u32 txq_id)
330 int actual_slots = slots_num;
333 * Alloc buffer array for commands (Tx or other types of commands).
334 * For the command queue (#4), allocate command space + one big
335 * command for scan, since scan command is very huge; the system will
336 * not have two scans at the same time, so only one is needed.
337 * For normal Tx queues (all other queues), no super-size command
340 if (txq_id == IWL_CMD_QUEUE_NUM)
343 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
345 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
348 if (!txq->meta || !txq->cmd)
349 goto out_free_arrays;
351 len = sizeof(struct iwl_device_cmd);
352 for (i = 0; i < actual_slots; i++) {
353 /* only happens for cmd queue */
355 len += IWL_MAX_SCAN_SIZE;
357 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
362 /* Alloc driver data array and TFD circular buffer */
363 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
367 txq->need_update = 0;
370 * Aggregation TX queues will get their ID when aggregation begins;
371 * they overwrite the setting done here. The command FIFO doesn't
372 * need an swq_id so don't set one to catch errors, all others can
373 * be set up to the identity mapping.
375 if (txq_id != IWL_CMD_QUEUE_NUM)
376 txq->swq_id = txq_id;
378 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
379 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
380 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
382 /* Initialize queue's high/low-water marks, and head/tail indexes */
383 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
385 /* Tell device where to find queue */
386 priv->cfg->ops->lib->txq_init(priv, txq);
390 for (i = 0; i < actual_slots; i++)
398 EXPORT_SYMBOL(iwl_tx_queue_init);
401 * iwl_hw_txq_ctx_free - Free TXQ Context
403 * Destroy all TX DMA queues and structures
405 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
411 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
413 if (txq_id == IWL_CMD_QUEUE_NUM)
414 iwl_cmd_queue_free(priv);
416 iwl_tx_queue_free(priv, txq_id);
418 iwl_free_dma_ptr(priv, &priv->kw);
420 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
422 /* free tx queue structure */
423 iwl_free_txq_mem(priv);
425 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
428 * iwl_txq_ctx_reset - Reset TX queue context
429 * Destroys all DMA structures and initialize them again
434 int iwl_txq_ctx_reset(struct iwl_priv *priv)
437 int txq_id, slots_num;
440 /* Free all tx/cmd queues and keep-warm buffer */
441 iwl_hw_txq_ctx_free(priv);
443 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
444 priv->hw_params.scd_bc_tbls_size);
446 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
449 /* Alloc keep-warm buffer */
450 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
452 IWL_ERR(priv, "Keep Warm allocation failed\n");
456 /* allocate tx queue structure */
457 ret = iwl_alloc_txq_mem(priv);
461 spin_lock_irqsave(&priv->lock, flags);
463 /* Turn off all Tx DMA fifos */
464 priv->cfg->ops->lib->txq_set_sched(priv, 0);
466 /* Tell NIC where to find the "keep warm" buffer */
467 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
469 spin_unlock_irqrestore(&priv->lock, flags);
471 /* Alloc and init all Tx queues, including the command queue (#4) */
472 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
473 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
474 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
475 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
478 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
486 iwl_hw_txq_ctx_free(priv);
487 iwl_free_dma_ptr(priv, &priv->kw);
489 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
495 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
497 void iwl_txq_ctx_stop(struct iwl_priv *priv)
502 /* Turn off all Tx DMA fifos */
503 spin_lock_irqsave(&priv->lock, flags);
505 priv->cfg->ops->lib->txq_set_sched(priv, 0);
507 /* Stop each Tx DMA channel, and wait for it to be idle */
508 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
509 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
510 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
511 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
514 spin_unlock_irqrestore(&priv->lock, flags);
516 /* Deallocate memory for all Tx queues */
517 iwl_hw_txq_ctx_free(priv);
519 EXPORT_SYMBOL(iwl_txq_ctx_stop);
522 * handle build REPLY_TX command notification.
524 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
525 struct iwl_tx_cmd *tx_cmd,
526 struct ieee80211_tx_info *info,
527 struct ieee80211_hdr *hdr,
530 __le16 fc = hdr->frame_control;
531 __le32 tx_flags = tx_cmd->tx_flags;
533 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
534 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
535 tx_flags |= TX_CMD_FLG_ACK_MSK;
536 if (ieee80211_is_mgmt(fc))
537 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
538 if (ieee80211_is_probe_resp(fc) &&
539 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
540 tx_flags |= TX_CMD_FLG_TSF_MSK;
542 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
543 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
546 if (ieee80211_is_back_req(fc))
547 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
550 tx_cmd->sta_id = std_id;
551 if (ieee80211_has_morefrags(fc))
552 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
554 if (ieee80211_is_data_qos(fc)) {
555 u8 *qc = ieee80211_get_qos_ctl(hdr);
556 tx_cmd->tid_tspec = qc[0] & 0xf;
557 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
559 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
562 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
564 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
565 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
567 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
568 if (ieee80211_is_mgmt(fc)) {
569 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
570 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
572 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
574 tx_cmd->timeout.pm_frame_timeout = 0;
577 tx_cmd->driver_txop = 0;
578 tx_cmd->tx_flags = tx_flags;
579 tx_cmd->next_frame_len = 0;
582 #define RTS_HCCA_RETRY_LIMIT 3
583 #define RTS_DFAULT_RETRY_LIMIT 60
585 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
586 struct iwl_tx_cmd *tx_cmd,
587 struct ieee80211_tx_info *info,
588 __le16 fc, int is_hcca)
596 /* Set retry limit on DATA packets and Probe Responses*/
597 if (ieee80211_is_probe_resp(fc))
598 data_retry_limit = 3;
600 data_retry_limit = IWL_DEFAULT_TX_RETRY;
601 tx_cmd->data_retry_limit = data_retry_limit;
603 /* Set retry limit on RTS packets */
604 rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT :
605 RTS_DFAULT_RETRY_LIMIT;
606 if (data_retry_limit < rts_retry_limit)
607 rts_retry_limit = data_retry_limit;
608 tx_cmd->rts_retry_limit = rts_retry_limit;
610 /* DATA packets will use the uCode station table for rate/antenna
612 if (ieee80211_is_data(fc)) {
613 tx_cmd->initial_rate_index = 0;
614 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
619 * If the current TX rate stored in mac80211 has the MCS bit set, it's
620 * not really a TX rate. Thus, we use the lowest supported rate for
621 * this band. Also use the lowest supported rate if the stored rate
624 rate_idx = info->control.rates[0].idx;
625 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
626 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
627 rate_idx = rate_lowest_index(&priv->bands[info->band],
629 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
630 if (info->band == IEEE80211_BAND_5GHZ)
631 rate_idx += IWL_FIRST_OFDM_RATE;
632 /* Get PLCP rate for tx_cmd->rate_n_flags */
633 rate_plcp = iwl_rates[rate_idx].plcp;
634 /* Zero out flags for this packet */
637 /* Set CCK flag as needed */
638 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
639 rate_flags |= RATE_MCS_CCK_MSK;
641 /* Set up RTS and CTS flags for certain packets */
642 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
643 case cpu_to_le16(IEEE80211_STYPE_AUTH):
644 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
645 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
646 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
647 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
648 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
649 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
656 /* Set up antennas */
657 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
658 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
660 /* Set the rate in the TX cmd */
661 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
664 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
665 struct ieee80211_tx_info *info,
666 struct iwl_tx_cmd *tx_cmd,
667 struct sk_buff *skb_frag,
670 struct ieee80211_key_conf *keyconf = info->control.hw_key;
672 switch (keyconf->alg) {
674 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
675 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
676 if (info->flags & IEEE80211_TX_CTL_AMPDU)
677 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
678 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
682 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
683 ieee80211_get_tkip_key(keyconf, skb_frag,
684 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
685 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
689 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
690 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
692 if (keyconf->keylen == WEP_KEY_LEN_128)
693 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
695 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
697 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
698 "with key %d\n", keyconf->keyidx);
702 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
708 * start REPLY_TX command process
710 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
712 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
713 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
714 struct ieee80211_sta *sta = info->control.sta;
715 struct iwl_station_priv *sta_priv = NULL;
716 struct iwl_tx_queue *txq;
718 struct iwl_device_cmd *out_cmd;
719 struct iwl_cmd_meta *out_meta;
720 struct iwl_tx_cmd *tx_cmd;
722 dma_addr_t phys_addr;
723 dma_addr_t txcmd_phys;
724 dma_addr_t scratch_phys;
725 u16 len, len_org, firstlen, secondlen;
730 u8 wait_write_ptr = 0;
736 spin_lock_irqsave(&priv->lock, flags);
737 if (iwl_is_rfkill(priv)) {
738 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
742 fc = hdr->frame_control;
744 #ifdef CONFIG_IWLWIFI_DEBUG
745 if (ieee80211_is_auth(fc))
746 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
747 else if (ieee80211_is_assoc_req(fc))
748 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
749 else if (ieee80211_is_reassoc_req(fc))
750 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
753 /* drop all non-injected data frame if we are not associated */
754 if (ieee80211_is_data(fc) &&
755 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
756 (!iwl_is_associated(priv) ||
757 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
758 !priv->assoc_station_added)) {
759 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
763 hdr_len = ieee80211_hdrlen(fc);
765 /* Find (or create) index into station table for destination station */
766 if (info->flags & IEEE80211_TX_CTL_INJECTED)
767 sta_id = priv->hw_params.bcast_sta_id;
769 sta_id = iwl_get_sta_id(priv, hdr);
770 if (sta_id == IWL_INVALID_STATION) {
771 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
776 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
779 sta_priv = (void *)sta->drv_priv;
781 if (sta_priv && sta_id != priv->hw_params.bcast_sta_id &&
783 WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE));
785 * This sends an asynchronous command to the device,
786 * but we can rely on it being processed before the
787 * next frame is processed -- and the next frame to
788 * this station is the one that will consume this
790 * For now set the counter to just 1 since we do not
793 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
796 txq_id = skb_get_queue_mapping(skb);
797 if (ieee80211_is_data_qos(fc)) {
798 qc = ieee80211_get_qos_ctl(hdr);
799 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
800 if (unlikely(tid >= MAX_TID_COUNT))
802 seq_number = priv->stations[sta_id].tid[tid].seq_number;
803 seq_number &= IEEE80211_SCTL_SEQ;
804 hdr->seq_ctrl = hdr->seq_ctrl &
805 cpu_to_le16(IEEE80211_SCTL_FRAG);
806 hdr->seq_ctrl |= cpu_to_le16(seq_number);
808 /* aggregation is on for this <sta,tid> */
809 if (info->flags & IEEE80211_TX_CTL_AMPDU)
810 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
813 txq = &priv->txq[txq_id];
814 swq_id = txq->swq_id;
817 if (unlikely(iwl_queue_space(q) < q->high_mark))
820 if (ieee80211_is_data_qos(fc))
821 priv->stations[sta_id].tid[tid].tfds_in_queue++;
823 /* Set up driver data for this TFD */
824 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
825 txq->txb[q->write_ptr].skb[0] = skb;
827 /* Set up first empty entry in queue's array of Tx/cmd buffers */
828 out_cmd = txq->cmd[q->write_ptr];
829 out_meta = &txq->meta[q->write_ptr];
830 tx_cmd = &out_cmd->cmd.tx;
831 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
832 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
835 * Set up the Tx-command (not MAC!) header.
836 * Store the chosen Tx queue and TFD index within the sequence field;
837 * after Tx, uCode's Tx response will return this value so driver can
838 * locate the frame within the tx queue and do post-tx processing.
840 out_cmd->hdr.cmd = REPLY_TX;
841 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
842 INDEX_TO_SEQ(q->write_ptr)));
844 /* Copy MAC header from skb into command buffer */
845 memcpy(tx_cmd->hdr, hdr, hdr_len);
848 /* Total # bytes to be transmitted */
850 tx_cmd->len = cpu_to_le16(len);
852 if (info->control.hw_key)
853 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
855 /* TODO need this for burst mode later on */
856 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
857 iwl_dbg_log_tx_data_frame(priv, len, hdr);
859 /* set is_hcca to 0; it probably will never be implemented */
860 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0);
862 iwl_update_stats(priv, true, fc, len);
864 * Use the first empty entry in this queue's command buffer array
865 * to contain the Tx command and MAC header concatenated together
866 * (payload data will be in another buffer).
867 * Size of this varies, due to varying MAC header length.
868 * If end is not dword aligned, we'll have 2 extra bytes at the end
869 * of the MAC header (device reads on dword boundaries).
870 * We'll tell device about this padding later.
872 len = sizeof(struct iwl_tx_cmd) +
873 sizeof(struct iwl_cmd_header) + hdr_len;
876 firstlen = len = (len + 3) & ~3;
883 /* Tell NIC about any 2-byte padding after MAC header */
885 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
887 /* Physical address of this Tx command's header (not MAC header!),
888 * within command buffer array. */
889 txcmd_phys = pci_map_single(priv->pci_dev,
891 PCI_DMA_BIDIRECTIONAL);
892 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
893 pci_unmap_len_set(out_meta, len, len);
894 /* Add buffer containing Tx command and MAC(!) header to TFD's
896 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
897 txcmd_phys, len, 1, 0);
899 if (!ieee80211_has_morefrags(hdr->frame_control)) {
900 txq->need_update = 1;
902 priv->stations[sta_id].tid[tid].seq_number = seq_number;
905 txq->need_update = 0;
908 /* Set up TFD's 2nd entry to point directly to remainder of skb,
909 * if any (802.11 null frames have no payload). */
910 secondlen = len = skb->len - hdr_len;
912 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
913 len, PCI_DMA_TODEVICE);
914 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
919 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
920 offsetof(struct iwl_tx_cmd, scratch);
922 len = sizeof(struct iwl_tx_cmd) +
923 sizeof(struct iwl_cmd_header) + hdr_len;
924 /* take back ownership of DMA buffer to enable update */
925 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
926 len, PCI_DMA_BIDIRECTIONAL);
927 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
928 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
930 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
931 le16_to_cpu(out_cmd->hdr.sequence));
932 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
933 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
934 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
936 /* Set up entry for this TFD in Tx byte-count array */
937 if (info->flags & IEEE80211_TX_CTL_AMPDU)
938 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
939 le16_to_cpu(tx_cmd->len));
941 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
942 len, PCI_DMA_BIDIRECTIONAL);
944 trace_iwlwifi_dev_tx(priv,
945 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
946 sizeof(struct iwl_tfd),
947 &out_cmd->hdr, firstlen,
948 skb->data + hdr_len, secondlen);
950 /* Tell device the write index *just past* this latest filled TFD */
951 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
952 ret = iwl_txq_update_write_ptr(priv, txq);
953 spin_unlock_irqrestore(&priv->lock, flags);
956 * At this point the frame is "transmitted" successfully
957 * and we will get a TX status notification eventually,
958 * regardless of the value of ret. "ret" only indicates
959 * whether or not we should update the write pointer.
962 /* avoid atomic ops if it isn't an associated client */
963 if (sta_priv && sta_priv->client)
964 atomic_inc(&sta_priv->pending_frames);
969 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
970 if (wait_write_ptr) {
971 spin_lock_irqsave(&priv->lock, flags);
972 txq->need_update = 1;
973 iwl_txq_update_write_ptr(priv, txq);
974 spin_unlock_irqrestore(&priv->lock, flags);
976 iwl_stop_queue(priv, txq->swq_id);
983 spin_unlock_irqrestore(&priv->lock, flags);
986 EXPORT_SYMBOL(iwl_tx_skb);
988 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
991 * iwl_enqueue_hcmd - enqueue a uCode command
992 * @priv: device private data point
993 * @cmd: a point to the ucode command structure
995 * The function returns < 0 values to indicate the operation is
996 * failed. On success, it turns the index (> 0) of command in the
999 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1001 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1002 struct iwl_queue *q = &txq->q;
1003 struct iwl_device_cmd *out_cmd;
1004 struct iwl_cmd_meta *out_meta;
1005 dma_addr_t phys_addr;
1006 unsigned long flags;
1011 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1012 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1014 /* If any of the command structures end up being larger than
1015 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1016 * we will need to increase the size of the TFD entries */
1017 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1018 !(cmd->flags & CMD_SIZE_HUGE));
1020 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
1021 IWL_WARN(priv, "Not sending command - %s KILL\n",
1022 iwl_is_rfkill(priv) ? "RF" : "CT");
1026 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1027 IWL_ERR(priv, "No space in command queue\n");
1028 if (iwl_within_ct_kill_margin(priv))
1029 iwl_tt_enter_ct_kill(priv);
1031 IWL_ERR(priv, "Restarting adapter due to queue full\n");
1032 queue_work(priv->workqueue, &priv->restart);
1037 spin_lock_irqsave(&priv->hcmd_lock, flags);
1039 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
1040 out_cmd = txq->cmd[idx];
1041 out_meta = &txq->meta[idx];
1043 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1044 out_meta->flags = cmd->flags;
1045 if (cmd->flags & CMD_WANT_SKB)
1046 out_meta->source = cmd;
1047 if (cmd->flags & CMD_ASYNC)
1048 out_meta->callback = cmd->callback;
1050 out_cmd->hdr.cmd = cmd->id;
1051 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1053 /* At this point, the out_cmd now has all of the incoming cmd
1056 out_cmd->hdr.flags = 0;
1057 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1058 INDEX_TO_SEQ(q->write_ptr));
1059 if (cmd->flags & CMD_SIZE_HUGE)
1060 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
1061 len = sizeof(struct iwl_device_cmd);
1062 len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0;
1065 #ifdef CONFIG_IWLWIFI_DEBUG
1066 switch (out_cmd->hdr.cmd) {
1067 case REPLY_TX_LINK_QUALITY_CMD:
1068 case SENSITIVITY_CMD:
1069 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
1070 "%d bytes at %d[%d]:%d\n",
1071 get_cmd_string(out_cmd->hdr.cmd),
1073 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1074 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1077 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
1078 "%d bytes at %d[%d]:%d\n",
1079 get_cmd_string(out_cmd->hdr.cmd),
1081 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1082 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1085 txq->need_update = 1;
1087 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1088 /* Set up entry in queue's byte count circular buffer */
1089 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1091 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
1092 fix_size, PCI_DMA_BIDIRECTIONAL);
1093 pci_unmap_addr_set(out_meta, mapping, phys_addr);
1094 pci_unmap_len_set(out_meta, len, fix_size);
1096 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
1098 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
1099 phys_addr, fix_size, 1,
1102 /* Increment and update queue's write index */
1103 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1104 ret = iwl_txq_update_write_ptr(priv, txq);
1106 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1107 return ret ? ret : idx;
1110 static void iwl_tx_status(struct iwl_priv *priv, struct sk_buff *skb)
1112 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1113 struct ieee80211_sta *sta;
1114 struct iwl_station_priv *sta_priv;
1116 sta = ieee80211_find_sta(priv->vif, hdr->addr1);
1118 sta_priv = (void *)sta->drv_priv;
1119 /* avoid atomic ops if this isn't a client */
1120 if (sta_priv->client &&
1121 atomic_dec_return(&sta_priv->pending_frames) == 0)
1122 ieee80211_sta_block_awake(priv->hw, sta, false);
1125 ieee80211_tx_status_irqsafe(priv->hw, skb);
1128 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1130 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1131 struct iwl_queue *q = &txq->q;
1132 struct iwl_tx_info *tx_info;
1135 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1136 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1137 "is out of range [0-%d] %d %d.\n", txq_id,
1138 index, q->n_bd, q->write_ptr, q->read_ptr);
1142 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1143 q->read_ptr != index;
1144 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1146 tx_info = &txq->txb[txq->q.read_ptr];
1147 iwl_tx_status(priv, tx_info->skb[0]);
1148 tx_info->skb[0] = NULL;
1150 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1151 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1153 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1158 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1162 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1164 * When FW advances 'R' index, all entries between old and new 'R' index
1165 * need to be reclaimed. As result, some free space forms. If there is
1166 * enough free space (> low mark), wake the stack that feeds us.
1168 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1169 int idx, int cmd_idx)
1171 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1172 struct iwl_queue *q = &txq->q;
1175 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1176 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1177 "is out of range [0-%d] %d %d.\n", txq_id,
1178 idx, q->n_bd, q->write_ptr, q->read_ptr);
1182 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1183 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1186 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1187 q->write_ptr, q->read_ptr);
1188 queue_work(priv->workqueue, &priv->restart);
1195 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1196 * @rxb: Rx buffer to reclaim
1198 * If an Rx buffer has an async callback associated with it the callback
1199 * will be executed. The attached skb (if present) will only be freed
1200 * if the callback returns 1
1202 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1204 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1205 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1206 int txq_id = SEQ_TO_QUEUE(sequence);
1207 int index = SEQ_TO_INDEX(sequence);
1209 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1210 struct iwl_device_cmd *cmd;
1211 struct iwl_cmd_meta *meta;
1213 /* If a Tx command is being handled and it isn't in the actual
1214 * command queue then there a command routing bug has been introduced
1215 * in the queue management code. */
1216 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1217 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1219 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1220 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1221 iwl_print_hex_error(priv, pkt, 32);
1225 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1226 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1227 meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index];
1229 pci_unmap_single(priv->pci_dev,
1230 pci_unmap_addr(meta, mapping),
1231 pci_unmap_len(meta, len),
1232 PCI_DMA_BIDIRECTIONAL);
1234 /* Input error checking is done when commands are added to queue. */
1235 if (meta->flags & CMD_WANT_SKB) {
1236 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
1238 } else if (meta->callback)
1239 meta->callback(priv, cmd, pkt);
1241 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1243 if (!(meta->flags & CMD_ASYNC)) {
1244 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1245 wake_up_interruptible(&priv->wait_command_queue);
1248 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1251 * Find first available (lowest unused) Tx Queue, mark it "active".
1252 * Called only when finding queue for aggregation.
1253 * Should never return anything < 7, because they should already
1254 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1256 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1260 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1261 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1266 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1272 unsigned long flags;
1273 struct iwl_tid_data *tid_data;
1275 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1276 tx_fifo = default_tid_to_tx_fifo[tid];
1280 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1283 sta_id = iwl_find_station(priv, ra);
1284 if (sta_id == IWL_INVALID_STATION) {
1285 IWL_ERR(priv, "Start AGG on invalid station\n");
1288 if (unlikely(tid >= MAX_TID_COUNT))
1291 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1292 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1296 txq_id = iwl_txq_ctx_activate_free(priv);
1298 IWL_ERR(priv, "No free aggregation queue available\n");
1302 spin_lock_irqsave(&priv->sta_lock, flags);
1303 tid_data = &priv->stations[sta_id].tid[tid];
1304 *ssn = SEQ_TO_SN(tid_data->seq_number);
1305 tid_data->agg.txq_id = txq_id;
1306 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id);
1307 spin_unlock_irqrestore(&priv->sta_lock, flags);
1309 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1314 if (tid_data->tfds_in_queue == 0) {
1315 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1316 tid_data->agg.state = IWL_AGG_ON;
1317 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1319 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1320 tid_data->tfds_in_queue);
1321 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1325 EXPORT_SYMBOL(iwl_tx_agg_start);
1327 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1329 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1330 struct iwl_tid_data *tid_data;
1331 int ret, write_ptr, read_ptr;
1332 unsigned long flags;
1335 IWL_ERR(priv, "ra = NULL\n");
1339 if (unlikely(tid >= MAX_TID_COUNT))
1342 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1343 tx_fifo_id = default_tid_to_tx_fifo[tid];
1347 sta_id = iwl_find_station(priv, ra);
1349 if (sta_id == IWL_INVALID_STATION) {
1350 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1354 if (priv->stations[sta_id].tid[tid].agg.state ==
1355 IWL_EMPTYING_HW_QUEUE_ADDBA) {
1356 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1357 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1358 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1362 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1363 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1365 tid_data = &priv->stations[sta_id].tid[tid];
1366 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1367 txq_id = tid_data->agg.txq_id;
1368 write_ptr = priv->txq[txq_id].q.write_ptr;
1369 read_ptr = priv->txq[txq_id].q.read_ptr;
1371 /* The queue is not empty */
1372 if (write_ptr != read_ptr) {
1373 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1374 priv->stations[sta_id].tid[tid].agg.state =
1375 IWL_EMPTYING_HW_QUEUE_DELBA;
1379 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1380 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1382 spin_lock_irqsave(&priv->lock, flags);
1383 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1385 spin_unlock_irqrestore(&priv->lock, flags);
1390 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1394 EXPORT_SYMBOL(iwl_tx_agg_stop);
1396 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1398 struct iwl_queue *q = &priv->txq[txq_id].q;
1399 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1400 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1402 switch (priv->stations[sta_id].tid[tid].agg.state) {
1403 case IWL_EMPTYING_HW_QUEUE_DELBA:
1404 /* We are reclaiming the last packet of the */
1405 /* aggregated HW queue */
1406 if ((txq_id == tid_data->agg.txq_id) &&
1407 (q->read_ptr == q->write_ptr)) {
1408 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1409 int tx_fifo = default_tid_to_tx_fifo[tid];
1410 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1411 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1413 tid_data->agg.state = IWL_AGG_OFF;
1414 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1417 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1418 /* We are reclaiming the last packet of the queue */
1419 if (tid_data->tfds_in_queue == 0) {
1420 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1421 tid_data->agg.state = IWL_AGG_ON;
1422 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1428 EXPORT_SYMBOL(iwl_txq_check_empty);
1431 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1433 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1434 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1436 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1437 struct iwl_ht_agg *agg,
1438 struct iwl_compressed_ba_resp *ba_resp)
1442 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1443 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1446 struct ieee80211_tx_info *info;
1448 if (unlikely(!agg->wait_for_ba)) {
1449 IWL_ERR(priv, "Received BA when not expected\n");
1453 /* Mark that the expected block-ack response arrived */
1454 agg->wait_for_ba = 0;
1455 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1457 /* Calculate shift to align block-ack bits with our Tx window bits */
1458 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1459 if (sh < 0) /* tbw something is wrong with indices */
1462 /* don't use 64-bit values for now */
1463 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1465 if (agg->frame_count > (64 - sh)) {
1466 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1470 /* check for success or failure according to the
1471 * transmitted bitmap and block-ack bitmap */
1472 bitmap &= agg->bitmap;
1474 /* For each frame attempted in aggregation,
1475 * update driver's record of tx frame's status. */
1476 for (i = 0; i < agg->frame_count ; i++) {
1477 ack = bitmap & (1ULL << i);
1479 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1480 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1481 agg->start_idx + i);
1484 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1485 memset(&info->status, 0, sizeof(info->status));
1486 info->flags |= IEEE80211_TX_STAT_ACK;
1487 info->flags |= IEEE80211_TX_STAT_AMPDU;
1488 info->status.ampdu_ack_map = successes;
1489 info->status.ampdu_ack_len = agg->frame_count;
1490 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1492 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1498 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1500 * Handles block-acknowledge notification from device, which reports success
1501 * of frames sent via aggregation.
1503 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1504 struct iwl_rx_mem_buffer *rxb)
1506 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1507 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1508 struct iwl_tx_queue *txq = NULL;
1509 struct iwl_ht_agg *agg;
1514 /* "flow" corresponds to Tx queue */
1515 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1517 /* "ssn" is start of block-ack Tx window, corresponds to index
1518 * (in Tx queue's circular buffer) of first TFD/frame in window */
1519 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1521 if (scd_flow >= priv->hw_params.max_txq_num) {
1523 "BUG_ON scd_flow is bigger than number of queues\n");
1527 txq = &priv->txq[scd_flow];
1528 sta_id = ba_resp->sta_id;
1530 agg = &priv->stations[sta_id].tid[tid].agg;
1532 /* Find index just before block-ack window */
1533 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1535 /* TODO: Need to get this copy more safely - now good for debug */
1537 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1540 (u8 *) &ba_resp->sta_addr_lo32,
1542 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1543 "%d, scd_ssn = %d\n",
1546 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1549 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1551 (unsigned long long)agg->bitmap);
1553 /* Update driver's record of ACK vs. not for each frame in window */
1554 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1556 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1557 * block-ack window (we assume that they've been successfully
1558 * transmitted ... if not, it's too late anyway). */
1559 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1560 /* calculate mac80211 ampdu sw queue to wake */
1561 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1562 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1564 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1565 priv->mac80211_registered &&
1566 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1567 iwl_wake_queue(priv, txq->swq_id);
1569 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1572 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1574 #ifdef CONFIG_IWLWIFI_DEBUG
1575 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1577 const char *iwl_get_tx_fail_reason(u32 status)
1579 switch (status & TX_STATUS_MSK) {
1580 case TX_STATUS_SUCCESS:
1582 TX_STATUS_ENTRY(SHORT_LIMIT);
1583 TX_STATUS_ENTRY(LONG_LIMIT);
1584 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1585 TX_STATUS_ENTRY(MGMNT_ABORT);
1586 TX_STATUS_ENTRY(NEXT_FRAG);
1587 TX_STATUS_ENTRY(LIFE_EXPIRE);
1588 TX_STATUS_ENTRY(DEST_PS);
1589 TX_STATUS_ENTRY(ABORTED);
1590 TX_STATUS_ENTRY(BT_RETRY);
1591 TX_STATUS_ENTRY(STA_INVALID);
1592 TX_STATUS_ENTRY(FRAG_DROPPED);
1593 TX_STATUS_ENTRY(TID_DISABLE);
1594 TX_STATUS_ENTRY(FRAME_FLUSHED);
1595 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1596 TX_STATUS_ENTRY(TX_LOCKED);
1597 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1602 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1603 #endif /* CONFIG_IWLWIFI_DEBUG */