2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/pci.h>
19 #include <linux/ath9k_platform.h>
22 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
23 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
24 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
25 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
26 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
27 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
28 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
29 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
30 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
31 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
32 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
33 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
37 /* return bus cachesize in 4B word units */
38 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
40 struct ath_softc *sc = (struct ath_softc *) common->priv;
43 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
47 * This check was put in to avoid "unplesant" consequences if
48 * the bootrom has not fully initialized all PCI devices.
49 * Sometimes the cache line size register is not set
53 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
56 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
58 struct ath_softc *sc = (struct ath_softc *) common->priv;
59 struct ath9k_platform_data *pdata = sc->dev->platform_data;
62 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
64 "%s: eeprom read failed, offset %08x is out of range\n",
68 *data = pdata->eeprom_data[off];
70 struct ath_hw *ah = (struct ath_hw *) common->ah;
72 common->ops->read(ah, AR5416_EEPROM_OFFSET +
73 (off << AR5416_EEPROM_S));
75 if (!ath9k_hw_wait(ah,
76 AR_EEPROM_STATUS_DATA,
77 AR_EEPROM_STATUS_DATA_BUSY |
78 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
83 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
84 AR_EEPROM_STATUS_DATA_VAL);
91 * Bluetooth coexistance requires disabling ASPM.
93 static void ath_pci_bt_coex_prep(struct ath_common *common)
95 struct ath_softc *sc = (struct ath_softc *) common->priv;
96 struct pci_dev *pdev = to_pci_dev(sc->dev);
99 if (!pci_is_pcie(pdev))
102 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
103 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
104 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
107 static void ath_pci_extn_synch_enable(struct ath_common *common)
109 struct ath_softc *sc = (struct ath_softc *) common->priv;
110 struct pci_dev *pdev = to_pci_dev(sc->dev);
113 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
114 lnkctl |= PCI_EXP_LNKCTL_ES;
115 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
118 static const struct ath_bus_ops ath_pci_bus_ops = {
119 .ath_bus_type = ATH_PCI,
120 .read_cachesize = ath_pci_read_cachesize,
121 .eeprom_read = ath_pci_eeprom_read,
122 .bt_coex_prep = ath_pci_bt_coex_prep,
123 .extn_synch_en = ath_pci_extn_synch_enable,
126 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
129 struct ath_wiphy *aphy;
130 struct ath_softc *sc;
131 struct ieee80211_hw *hw;
138 if (pci_enable_device(pdev))
141 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
143 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
147 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
149 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
150 "DMA enable failed\n");
155 * Cache line size is used to size and align various
156 * structures used to communicate with the hardware.
158 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
161 * Linux 2.4.18 (at least) writes the cache line size
162 * register as a 16-bit wide register which is wrong.
163 * We must have this setup properly for rx buffer
164 * DMA to work so force a reasonable value here if it
167 csz = L1_CACHE_BYTES / sizeof(u32);
168 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
171 * The default setting of latency timer yields poor results,
172 * set it to the value used by other systems. It may be worth
173 * tweaking this setting more.
175 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
177 pci_set_master(pdev);
180 * Disable the RETRY_TIMEOUT register (0x41) to keep
181 * PCI Tx retries from interfering with C3 CPU state.
183 pci_read_config_dword(pdev, 0x40, &val);
184 if ((val & 0x0000ff00) != 0)
185 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
187 ret = pci_request_region(pdev, 0, "ath9k");
189 dev_err(&pdev->dev, "PCI memory region reserve error\n");
194 mem = pci_iomap(pdev, 0, 0);
196 printk(KERN_ERR "PCI memory map error\n") ;
201 hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
202 sizeof(struct ath_softc), &ath9k_ops);
204 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
209 SET_IEEE80211_DEV(hw, &pdev->dev);
210 pci_set_drvdata(pdev, hw);
213 sc = (struct ath_softc *) (aphy + 1);
216 sc->pri_wiphy = aphy;
218 sc->dev = &pdev->dev;
221 /* Will be cleared in ath9k_start() */
222 sc->sc_flags |= SC_OP_INVALID;
224 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
226 dev_err(&pdev->dev, "request_irq failed\n");
232 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
233 ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
235 dev_err(&pdev->dev, "Failed to initialize device\n");
239 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
240 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
241 hw_name, (unsigned long)mem, pdev->irq);
246 free_irq(sc->irq, sc);
248 ieee80211_free_hw(hw);
250 pci_iounmap(pdev, mem);
252 pci_release_region(pdev, 0);
256 pci_disable_device(pdev);
260 static void ath_pci_remove(struct pci_dev *pdev)
262 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
263 struct ath_wiphy *aphy = hw->priv;
264 struct ath_softc *sc = aphy->sc;
265 void __iomem *mem = sc->mem;
267 if (!is_ath9k_unloaded)
268 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
269 ath9k_deinit_device(sc);
270 free_irq(sc->irq, sc);
271 ieee80211_free_hw(sc->hw);
273 pci_iounmap(pdev, mem);
274 pci_disable_device(pdev);
275 pci_release_region(pdev, 0);
280 static int ath_pci_suspend(struct device *device)
282 struct pci_dev *pdev = to_pci_dev(device);
283 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
284 struct ath_wiphy *aphy = hw->priv;
285 struct ath_softc *sc = aphy->sc;
287 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
292 static int ath_pci_resume(struct device *device)
294 struct pci_dev *pdev = to_pci_dev(device);
295 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
296 struct ath_wiphy *aphy = hw->priv;
297 struct ath_softc *sc = aphy->sc;
301 * Suspend/Resume resets the PCI configuration space, so we have to
302 * re-disable the RETRY_TIMEOUT register (0x41) to keep
303 * PCI Tx retries from interfering with C3 CPU state
305 pci_read_config_dword(pdev, 0x40, &val);
306 if ((val & 0x0000ff00) != 0)
307 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
310 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
311 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
312 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
315 * Reset key cache to sane defaults (all entries cleared) instead of
316 * semi-random values after suspend/resume.
319 ath9k_init_crypto(sc);
320 ath9k_ps_restore(sc);
323 ath9k_set_wiphy_idle(aphy, true);
324 ath_radio_disable(sc, hw);
329 static const struct dev_pm_ops ath9k_pm_ops = {
330 .suspend = ath_pci_suspend,
331 .resume = ath_pci_resume,
332 .freeze = ath_pci_suspend,
333 .thaw = ath_pci_resume,
334 .poweroff = ath_pci_suspend,
335 .restore = ath_pci_resume,
338 #define ATH9K_PM_OPS (&ath9k_pm_ops)
340 #else /* !CONFIG_PM */
342 #define ATH9K_PM_OPS NULL
344 #endif /* !CONFIG_PM */
347 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
349 static struct pci_driver ath_pci_driver = {
351 .id_table = ath_pci_id_table,
352 .probe = ath_pci_probe,
353 .remove = ath_pci_remove,
354 .driver.pm = ATH9K_PM_OPS,
357 int ath_pci_init(void)
359 return pci_register_driver(&ath_pci_driver);
362 void ath_pci_exit(void)
364 pci_unregister_driver(&ath_pci_driver);