2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * DOC: Programming Atheros 802.11n analog front end radios
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
29 * The following single-chips exist with a respective embedded radio:
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
39 * AR9287 - 11n single-band 1x1 MIMO for USB
43 #include "ar9002_phy.h"
46 * ar9002_hw_set_channel - set channel on single-chip device
47 * @ah: atheros hardware structure
50 * This is the function to change channel on single-chip devices, that is
51 * all devices after ar9280.
53 * This function takes the channel value in MHz and sets
54 * hardware channel value. Assumes writes have been enabled to analog bus.
59 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
63 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
64 * (freq_ref = 40MHz/(24>>amodeRefSel))
66 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
68 u16 bMode, fracMode, aModeRefSel = 0;
69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
70 struct chan_centers centers;
73 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
74 freq = centers.synth_center;
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
79 if (freq < 4800) { /* 2 GHz, fractional mode */
86 channelSel = CHANSEL_2G(freq);
88 if (AR_SREV_9287_11_OR_LATER(ah)) {
90 /* Enable channel spreading for channel 14 */
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
100 /* Enable channel spreading for channel 14 */
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
102 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
105 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
114 if ((freq % 20) == 0)
116 else if ((freq % 10) == 0)
124 * Enable 2G (fractional) mode for channels
125 * which are 5MHz spaced.
129 channelSel = CHANSEL_5G(freq);
131 /* RefDivA setting */
132 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
133 AR_AN_SYNTH9_REFDIVA, refDivA);
138 ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
139 channelSel = ndiv & 0x1ff;
140 channelFrac = (ndiv & 0xfffffe00) * 2;
141 channelSel = (channelSel << 17) | channelFrac;
147 (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
149 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
152 ah->curchan_rad_index = -1;
158 * ar9002_hw_spur_mitigate - convert baseband spur frequency
159 * @ah: atheros hardware structure
162 * For single-chip solutions. Converts to baseband spur frequency given the
163 * input channel frequency and compute register settings below.
165 static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
166 struct ath9k_channel *chan)
168 int bb_spur = AR_NO_SPUR;
171 int bb_spur_off, spur_subchannel_sd;
173 int spur_delta_phase;
175 int upper, lower, cur_vit_mask;
178 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
179 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
181 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
182 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
184 int inc[4] = { 0, 100, 0, 0 };
185 struct chan_centers centers;
192 bool is2GHz = IS_CHAN_2GHZ(chan);
194 memset(&mask_m, 0, sizeof(int8_t) * 123);
195 memset(&mask_p, 0, sizeof(int8_t) * 123);
197 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
198 freq = centers.synth_center;
200 ah->config.spurmode = SPUR_ENABLE_EEPROM;
201 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
202 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
205 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
207 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
209 if (AR_NO_SPUR == cur_bb_spur)
211 cur_bb_spur = cur_bb_spur - freq;
213 if (IS_CHAN_HT40(chan)) {
214 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
215 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
216 bb_spur = cur_bb_spur;
219 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
220 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
221 bb_spur = cur_bb_spur;
226 if (AR_NO_SPUR == bb_spur) {
227 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
228 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
231 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
232 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
237 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
239 ENABLE_REGWRITE_BUFFER(ah);
241 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
242 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
243 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
244 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
245 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
247 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
248 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
249 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
250 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
251 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
252 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
254 if (IS_CHAN_HT40(chan)) {
256 spur_subchannel_sd = 1;
257 bb_spur_off = bb_spur + 10;
259 spur_subchannel_sd = 0;
260 bb_spur_off = bb_spur - 10;
263 spur_subchannel_sd = 0;
264 bb_spur_off = bb_spur;
267 if (IS_CHAN_HT40(chan))
269 ((bb_spur * 262144) /
270 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
273 ((bb_spur * 524288) /
274 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
276 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
277 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
279 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
280 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
281 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
282 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
284 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
285 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
291 for (i = 0; i < 4; i++) {
295 for (bp = 0; bp < 30; bp++) {
296 if ((cur_bin > lower) && (cur_bin < upper)) {
297 pilot_mask = pilot_mask | 0x1 << bp;
298 chan_mask = chan_mask | 0x1 << bp;
303 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
304 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
311 for (i = 0; i < 123; i++) {
312 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
314 /* workaround for gcc bug #37014 */
315 volatile int tmp_v = abs(cur_vit_mask - bin);
321 if (cur_vit_mask < 0)
322 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
324 mask_p[cur_vit_mask / 100] = mask_amt;
329 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
330 | (mask_m[48] << 26) | (mask_m[49] << 24)
331 | (mask_m[50] << 22) | (mask_m[51] << 20)
332 | (mask_m[52] << 18) | (mask_m[53] << 16)
333 | (mask_m[54] << 14) | (mask_m[55] << 12)
334 | (mask_m[56] << 10) | (mask_m[57] << 8)
335 | (mask_m[58] << 6) | (mask_m[59] << 4)
336 | (mask_m[60] << 2) | (mask_m[61] << 0);
337 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
338 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
340 tmp_mask = (mask_m[31] << 28)
341 | (mask_m[32] << 26) | (mask_m[33] << 24)
342 | (mask_m[34] << 22) | (mask_m[35] << 20)
343 | (mask_m[36] << 18) | (mask_m[37] << 16)
344 | (mask_m[48] << 14) | (mask_m[39] << 12)
345 | (mask_m[40] << 10) | (mask_m[41] << 8)
346 | (mask_m[42] << 6) | (mask_m[43] << 4)
347 | (mask_m[44] << 2) | (mask_m[45] << 0);
348 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
349 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
351 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
352 | (mask_m[18] << 26) | (mask_m[18] << 24)
353 | (mask_m[20] << 22) | (mask_m[20] << 20)
354 | (mask_m[22] << 18) | (mask_m[22] << 16)
355 | (mask_m[24] << 14) | (mask_m[24] << 12)
356 | (mask_m[25] << 10) | (mask_m[26] << 8)
357 | (mask_m[27] << 6) | (mask_m[28] << 4)
358 | (mask_m[29] << 2) | (mask_m[30] << 0);
359 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
360 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
362 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
363 | (mask_m[2] << 26) | (mask_m[3] << 24)
364 | (mask_m[4] << 22) | (mask_m[5] << 20)
365 | (mask_m[6] << 18) | (mask_m[7] << 16)
366 | (mask_m[8] << 14) | (mask_m[9] << 12)
367 | (mask_m[10] << 10) | (mask_m[11] << 8)
368 | (mask_m[12] << 6) | (mask_m[13] << 4)
369 | (mask_m[14] << 2) | (mask_m[15] << 0);
370 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
371 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
373 tmp_mask = (mask_p[15] << 28)
374 | (mask_p[14] << 26) | (mask_p[13] << 24)
375 | (mask_p[12] << 22) | (mask_p[11] << 20)
376 | (mask_p[10] << 18) | (mask_p[9] << 16)
377 | (mask_p[8] << 14) | (mask_p[7] << 12)
378 | (mask_p[6] << 10) | (mask_p[5] << 8)
379 | (mask_p[4] << 6) | (mask_p[3] << 4)
380 | (mask_p[2] << 2) | (mask_p[1] << 0);
381 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
382 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
384 tmp_mask = (mask_p[30] << 28)
385 | (mask_p[29] << 26) | (mask_p[28] << 24)
386 | (mask_p[27] << 22) | (mask_p[26] << 20)
387 | (mask_p[25] << 18) | (mask_p[24] << 16)
388 | (mask_p[23] << 14) | (mask_p[22] << 12)
389 | (mask_p[21] << 10) | (mask_p[20] << 8)
390 | (mask_p[19] << 6) | (mask_p[18] << 4)
391 | (mask_p[17] << 2) | (mask_p[16] << 0);
392 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
393 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
395 tmp_mask = (mask_p[45] << 28)
396 | (mask_p[44] << 26) | (mask_p[43] << 24)
397 | (mask_p[42] << 22) | (mask_p[41] << 20)
398 | (mask_p[40] << 18) | (mask_p[39] << 16)
399 | (mask_p[38] << 14) | (mask_p[37] << 12)
400 | (mask_p[36] << 10) | (mask_p[35] << 8)
401 | (mask_p[34] << 6) | (mask_p[33] << 4)
402 | (mask_p[32] << 2) | (mask_p[31] << 0);
403 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
404 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
406 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
407 | (mask_p[59] << 26) | (mask_p[58] << 24)
408 | (mask_p[57] << 22) | (mask_p[56] << 20)
409 | (mask_p[55] << 18) | (mask_p[54] << 16)
410 | (mask_p[53] << 14) | (mask_p[52] << 12)
411 | (mask_p[51] << 10) | (mask_p[50] << 8)
412 | (mask_p[49] << 6) | (mask_p[48] << 4)
413 | (mask_p[47] << 2) | (mask_p[46] << 0);
414 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
415 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
417 REGWRITE_BUFFER_FLUSH(ah);
420 static void ar9002_olc_init(struct ath_hw *ah)
424 if (!OLC_FOR_AR9280_20_LATER)
427 if (OLC_FOR_AR9287_10_LATER) {
428 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
429 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
430 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
431 AR9287_AN_TXPC0_TXPCMODE,
432 AR9287_AN_TXPC0_TXPCMODE_S,
433 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
436 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
437 ah->originalGain[i] =
438 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
444 static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
445 struct ath9k_channel *chan)
449 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
451 if (chan && IS_CHAN_HALF_RATE(chan))
452 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
453 else if (chan && IS_CHAN_QUARTER_RATE(chan))
454 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
456 if (chan && IS_CHAN_5GHZ(chan)) {
457 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
459 else if (AR_SREV_9280_20(ah))
462 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
464 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
470 static void ar9002_hw_do_getnf(struct ath_hw *ah,
471 int16_t nfarray[NUM_NF_READINGS])
475 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
476 nfarray[0] = sign_extend(nf, 9);
478 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
479 if (IS_CHAN_HT40(ah->curchan))
480 nfarray[3] = sign_extend(nf, 9);
482 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
485 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
486 nfarray[1] = sign_extend(nf, 9);
488 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
489 if (IS_CHAN_HT40(ah->curchan))
490 nfarray[4] = sign_extend(nf, 9);
493 static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
495 if (AR_SREV_9285(ah)) {
496 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
497 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
498 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
499 } else if (AR_SREV_9287(ah)) {
500 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
501 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
502 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
503 } else if (AR_SREV_9271(ah)) {
504 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
505 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
506 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
508 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
509 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
510 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
511 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
512 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
513 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
517 void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
519 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
521 priv_ops->set_rf_regs = NULL;
522 priv_ops->rf_alloc_ext_banks = NULL;
523 priv_ops->rf_free_ext_banks = NULL;
524 priv_ops->rf_set_freq = ar9002_hw_set_channel;
525 priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
526 priv_ops->olc_init = ar9002_olc_init;
527 priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
528 priv_ops->do_getnf = ar9002_hw_do_getnf;
530 ar9002_hw_set_nf_limits(ah);
533 void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
534 struct ath_hw_antcomb_conf *antconf)
538 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
539 antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
540 AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
541 antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
542 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
543 antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
544 AR_PHY_9285_FAST_DIV_BIAS_S;
546 EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_get);
548 void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
549 struct ath_hw_antcomb_conf *antconf)
553 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
554 regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
555 AR_PHY_9285_ANT_DIV_ALT_LNACONF |
556 AR_PHY_9285_FAST_DIV_BIAS);
557 regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
558 & AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
559 regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
560 & AR_PHY_9285_ANT_DIV_ALT_LNACONF);
561 regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
562 & AR_PHY_9285_FAST_DIV_BIAS);
564 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
566 EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_set);