1 /****************************************************************************
2 * Driver for Solarflare 802.3an compliant PHY
3 * Copyright 2007 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include <linux/delay.h>
11 #include <linux/seq_file.h>
17 #include "falcon_hwdefs.h"
21 /* We expect these MMDs to be in the package */
22 /* AN not here as mdio_check_mmds() requires STAT2 support */
23 #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_PMAPMD | \
24 MDIO_MMDREG_DEVS0_PCS | \
25 MDIO_MMDREG_DEVS0_PHYXS)
27 #define TENXPRESS_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
28 (1 << LOOPBACK_PCS) | \
29 (1 << LOOPBACK_PMAPMD) | \
30 (1 << LOOPBACK_NETWORK))
32 /* We complain if we fail to see the link partner as 10G capable this many
33 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
35 #define MAX_BAD_LP_TRIES (5)
37 /* Extended control register */
38 #define PMA_PMD_XCONTROL_REG 0xc000
39 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8
40 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
42 /* extended status register */
43 #define PMA_PMD_XSTATUS_REG 0xc001
44 #define PMA_PMD_XSTAT_FLP_LBN (12)
46 /* LED control register */
47 #define PMA_PMD_LED_CTRL_REG (0xc007)
48 #define PMA_PMA_LED_ACTIVITY_LBN (3)
50 /* LED function override register */
51 #define PMA_PMD_LED_OVERR_REG (0xc009)
52 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
53 #define PMA_PMD_LED_LINK_LBN (0)
54 #define PMA_PMD_LED_SPEED_LBN (2)
55 #define PMA_PMD_LED_TX_LBN (4)
56 #define PMA_PMD_LED_RX_LBN (6)
57 /* Override settings */
58 #define PMA_PMD_LED_AUTO (0) /* H/W control */
59 #define PMA_PMD_LED_ON (1)
60 #define PMA_PMD_LED_OFF (2)
61 #define PMA_PMD_LED_FLASH (3)
62 /* All LEDs under hardware control */
63 #define PMA_PMD_LED_FULL_AUTO (0)
64 /* Green and Amber under hardware control, Red off */
65 #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
68 /* Special Software reset register */
69 #define PMA_PMD_EXT_CTRL_REG 49152
70 #define PMA_PMD_EXT_SSR_LBN 15
72 /* Misc register defines */
73 #define PCS_CLOCK_CTRL_REG 0xd801
74 #define PLL312_RST_N_LBN 2
76 #define PCS_SOFT_RST2_REG 0xd806
77 #define SERDES_RST_N_LBN 13
78 #define XGXS_RST_N_LBN 12
80 #define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */
81 #define CLK312_EN_LBN 3
84 #define PHYXS_TEST1 (49162)
85 #define LOOPBACK_NEAR_LBN (8)
86 #define LOOPBACK_NEAR_WIDTH (1)
88 /* Boot status register */
89 #define PCS_BOOT_STATUS_REG (0xd000)
90 #define PCS_BOOT_FATAL_ERR_LBN (0)
91 #define PCS_BOOT_PROGRESS_LBN (1)
92 #define PCS_BOOT_PROGRESS_WIDTH (2)
93 #define PCS_BOOT_COMPLETE_LBN (3)
94 #define PCS_BOOT_MAX_DELAY (100)
95 #define PCS_BOOT_POLL_DELAY (10)
97 /* Time to wait between powering down the LNPGA and turning off the power
99 #define LNPGA_PDOWN_WAIT (HZ / 5)
101 static int crc_error_reset_threshold = 100;
102 module_param(crc_error_reset_threshold, int, 0644);
103 MODULE_PARM_DESC(crc_error_reset_threshold,
104 "Max number of CRC errors before XAUI reset");
106 struct tenxpress_phy_data {
107 enum efx_loopback_mode loopback_mode;
108 atomic_t bad_crc_count;
109 enum efx_phy_mode phy_mode;
113 void tenxpress_crc_err(struct efx_nic *efx)
115 struct tenxpress_phy_data *phy_data = efx->phy_data;
116 if (phy_data != NULL)
117 atomic_inc(&phy_data->bad_crc_count);
120 /* Check that the C166 has booted successfully */
121 static int tenxpress_phy_check(struct efx_nic *efx)
123 int phy_id = efx->mii.phy_id;
124 int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
127 /* Wait for the boot to complete (or not) */
129 boot_stat = mdio_clause45_read(efx, phy_id,
131 PCS_BOOT_STATUS_REG);
132 if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
135 udelay(PCS_BOOT_POLL_DELAY);
139 EFX_ERR(efx, "%s: PHY boot timed out. Last status "
141 (boot_stat >> PCS_BOOT_PROGRESS_LBN) &
142 ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
149 static void tenxpress_reset_xaui(struct efx_nic *efx);
151 static int tenxpress_init(struct efx_nic *efx)
155 /* Turn on the clock */
156 reg = (1 << CLK312_EN_LBN);
157 mdio_clause45_write(efx, efx->mii.phy_id,
158 MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg);
160 rc = tenxpress_phy_check(efx);
164 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
165 reg = mdio_clause45_read(efx, efx->mii.phy_id,
166 MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG);
167 reg |= (1 << PMA_PMA_LED_ACTIVITY_LBN);
168 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
169 PMA_PMD_LED_CTRL_REG, reg);
171 reg = PMA_PMD_LED_DEFAULT;
172 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
173 PMA_PMD_LED_OVERR_REG, reg);
178 static int tenxpress_phy_init(struct efx_nic *efx)
180 struct tenxpress_phy_data *phy_data;
183 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
186 efx->phy_data = phy_data;
187 phy_data->phy_mode = efx->phy_mode;
189 rc = mdio_clause45_wait_reset_mmds(efx,
190 TENXPRESS_REQUIRED_DEVS);
194 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
198 rc = tenxpress_init(efx);
202 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
204 /* Let XGXS and SerDes out of reset and resets 10XPress */
205 falcon_reset_xaui(efx);
210 kfree(efx->phy_data);
211 efx->phy_data = NULL;
215 static int tenxpress_special_reset(struct efx_nic *efx)
219 EFX_TRACE(efx, "%s\n", __func__);
222 reg = mdio_clause45_read(efx, efx->mii.phy_id,
223 MDIO_MMD_PMAPMD, PMA_PMD_EXT_CTRL_REG);
224 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
225 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
226 PMA_PMD_EXT_CTRL_REG, reg);
230 /* Wait for the blocks to come out of reset */
231 rc = mdio_clause45_wait_reset_mmds(efx,
232 TENXPRESS_REQUIRED_DEVS);
236 /* Try and reconfigure the device */
237 rc = tenxpress_init(efx);
244 static void tenxpress_set_bad_lp(struct efx_nic *efx, bool bad_lp)
246 struct tenxpress_phy_data *pd = efx->phy_data;
249 /* Nothing to do if all is well and was previously so. */
250 if (!(bad_lp || pd->bad_lp_tries))
253 reg = mdio_clause45_read(efx, efx->mii.phy_id,
254 MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG);
259 pd->bad_lp_tries = 0;
261 if (pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
262 pd->bad_lp_tries = 0; /* Restart count */
263 reg &= ~(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
264 reg |= (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
265 EFX_ERR(efx, "This NIC appears to be plugged into"
266 " a port that is not 10GBASE-T capable.\n"
267 " This PHY is 10GBASE-T ONLY, so no link can"
268 " be established.\n");
270 reg |= (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN);
272 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
273 PMA_PMD_LED_OVERR_REG, reg);
276 /* Check link status and return a boolean OK value. If the link is NOT
277 * OK we have a quick rummage round to see if we appear to be plugged
278 * into a non-10GBT port and if so warn the user that they won't get
279 * link any time soon as we are 10GBT only, unless caller specified
280 * not to do this check (it isn't useful in loopback) */
281 static bool tenxpress_link_ok(struct efx_nic *efx, bool check_lp)
283 bool ok = mdio_clause45_links_ok(efx, TENXPRESS_REQUIRED_DEVS);
286 tenxpress_set_bad_lp(efx, false);
287 } else if (check_lp) {
288 /* Are we plugged into the wrong sort of link? */
290 int phy_id = efx->mii.phy_id;
291 int an_stat = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
293 int xphy_stat = mdio_clause45_read(efx, phy_id,
295 PMA_PMD_XSTATUS_REG);
296 /* Are we plugged into anything that sends FLPs? If
297 * not we can't distinguish between not being plugged
298 * in and being plugged into a non-AN antique. The FLP
299 * bit has the advantage of not clearing when autoneg
301 if (!(xphy_stat & (1 << PMA_PMD_XSTAT_FLP_LBN))) {
302 tenxpress_set_bad_lp(efx, false);
306 /* If it can do 10GBT it must be XNP capable */
307 bad_lp = !(an_stat & (1 << MDIO_AN_STATUS_XNP_LBN));
308 if (!bad_lp && (an_stat & (1 << MDIO_AN_STATUS_PAGE_LBN))) {
309 bad_lp = !(mdio_clause45_read(efx, phy_id,
310 MDIO_MMD_AN, MDIO_AN_10GBT_STATUS) &
311 (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN));
313 tenxpress_set_bad_lp(efx, bad_lp);
318 static void tenxpress_phyxs_loopback(struct efx_nic *efx)
320 int phy_id = efx->mii.phy_id;
323 ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
325 if (efx->loopback_mode == LOOPBACK_PHYXS)
326 ctrl2 |= (1 << LOOPBACK_NEAR_LBN);
328 ctrl2 &= ~(1 << LOOPBACK_NEAR_LBN);
330 mdio_clause45_write(efx, phy_id, MDIO_MMD_PHYXS,
334 static void tenxpress_phy_reconfigure(struct efx_nic *efx)
336 struct tenxpress_phy_data *phy_data = efx->phy_data;
337 bool loop_change = LOOPBACK_OUT_OF(phy_data, efx,
338 TENXPRESS_LOOPBACKS);
340 if (efx->phy_mode & PHY_MODE_SPECIAL) {
341 phy_data->phy_mode = efx->phy_mode;
345 /* When coming out of transmit disable, coming out of low power
346 * mode, or moving out of any PHY internal loopback mode,
347 * perform a special software reset */
348 if ((efx->phy_mode == PHY_MODE_NORMAL &&
349 phy_data->phy_mode != PHY_MODE_NORMAL) ||
351 tenxpress_special_reset(efx);
352 falcon_reset_xaui(efx);
355 mdio_clause45_transmit_disable(efx);
356 mdio_clause45_phy_reconfigure(efx);
357 tenxpress_phyxs_loopback(efx);
359 phy_data->loopback_mode = efx->loopback_mode;
360 phy_data->phy_mode = efx->phy_mode;
361 efx->link_up = tenxpress_link_ok(efx, false);
362 efx->link_options = GM_LPA_10000FULL;
365 static void tenxpress_phy_clear_interrupt(struct efx_nic *efx)
367 /* Nothing done here - LASI interrupts aren't reliable so poll */
371 /* Poll PHY for interrupt */
372 static int tenxpress_phy_check_hw(struct efx_nic *efx)
374 struct tenxpress_phy_data *phy_data = efx->phy_data;
377 link_ok = (phy_data->phy_mode == PHY_MODE_NORMAL &&
378 tenxpress_link_ok(efx, true));
380 if (link_ok != efx->link_up)
381 falcon_xmac_sim_phy_event(efx);
383 if (phy_data->phy_mode != PHY_MODE_NORMAL)
386 if (atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) {
387 EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n");
388 falcon_reset_xaui(efx);
389 atomic_set(&phy_data->bad_crc_count, 0);
395 static void tenxpress_phy_fini(struct efx_nic *efx)
399 /* Power down the LNPGA */
400 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
401 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
402 PMA_PMD_XCONTROL_REG, reg);
404 /* Waiting here ensures that the board fini, which can turn off the
405 * power to the PHY, won't get run until the LNPGA powerdown has been
406 * given long enough to complete. */
407 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
409 kfree(efx->phy_data);
410 efx->phy_data = NULL;
414 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
415 * (which probably aren't wired anyway) are left in AUTO mode */
416 void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
421 reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
422 (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
423 (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
425 reg = PMA_PMD_LED_DEFAULT;
427 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
428 PMA_PMD_LED_OVERR_REG, reg);
431 static void tenxpress_reset_xaui(struct efx_nic *efx)
433 int phy = efx->mii.phy_id;
434 int clk_ctrl, test_select, soft_rst2;
436 /* Real work is done on clock_ctrl other resets are thought to be
437 * optional but make the reset more reliable
441 clk_ctrl = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
443 test_select = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
444 PCS_TEST_SELECT_REG);
445 soft_rst2 = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
449 test_select &= ~(1 << CLK312_EN_LBN);
450 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
451 PCS_TEST_SELECT_REG, test_select);
453 soft_rst2 &= ~((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN));
454 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
455 PCS_SOFT_RST2_REG, soft_rst2);
457 clk_ctrl &= ~(1 << PLL312_RST_N_LBN);
458 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
459 PCS_CLOCK_CTRL_REG, clk_ctrl);
463 clk_ctrl |= (1 << PLL312_RST_N_LBN);
464 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
465 PCS_CLOCK_CTRL_REG, clk_ctrl);
468 soft_rst2 |= ((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN));
469 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
470 PCS_SOFT_RST2_REG, soft_rst2);
473 test_select |= (1 << CLK312_EN_LBN);
474 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
475 PCS_TEST_SELECT_REG, test_select);
479 static int tenxpress_phy_test(struct efx_nic *efx)
481 /* BIST is automatically run after a special software reset */
482 return tenxpress_special_reset(efx);
485 struct efx_phy_operations falcon_tenxpress_phy_ops = {
486 .init = tenxpress_phy_init,
487 .reconfigure = tenxpress_phy_reconfigure,
488 .check_hw = tenxpress_phy_check_hw,
489 .fini = tenxpress_phy_fini,
490 .clear_interrupt = tenxpress_phy_clear_interrupt,
491 .reset_xaui = tenxpress_reset_xaui,
492 .test = tenxpress_phy_test,
493 .mmds = TENXPRESS_REQUIRED_DEVS,
494 .loopbacks = TENXPRESS_LOOPBACKS,