1 /*******************************************************************************
2 This is the driver for the MAC 10/100 on-chip Ethernet controller
3 currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
5 DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
8 This only implements the mac core functions for this chip.
10 Copyright (C) 2007-2009 STMicroelectronics Ltd
12 This program is free software; you can redistribute it and/or modify it
13 under the terms and conditions of the GNU General Public License,
14 version 2, as published by the Free Software Foundation.
16 This program is distributed in the hope it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 You should have received a copy of the GNU General Public License along with
22 this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
25 The full GNU General Public License is included in this distribution in
26 the file called "COPYING".
28 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
29 *******************************************************************************/
31 #include <linux/crc32.h>
35 static void dwmac100_core_init(void __iomem *ioaddr)
37 u32 value = readl(ioaddr + MAC_CONTROL);
39 writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);
41 #ifdef STMMAC_VLAN_TAG_USED
42 writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
46 static void dwmac100_dump_mac_regs(void __iomem *ioaddr)
48 pr_info("\t----------------------------------------------\n"
49 "\t DWMAC 100 CSR (base addr = 0x%p)\n"
50 "\t----------------------------------------------\n",
52 pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
53 readl(ioaddr + MAC_CONTROL));
54 pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
55 readl(ioaddr + MAC_ADDR_HIGH));
56 pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
57 readl(ioaddr + MAC_ADDR_LOW));
58 pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
59 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
60 pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
61 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
62 pr_info("\tflow control (offset 0x%x): 0x%08x\n",
63 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
64 pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
65 readl(ioaddr + MAC_VLAN1));
66 pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
67 readl(ioaddr + MAC_VLAN2));
70 static int dwmac100_rx_ipc_enable(void __iomem *ioaddr)
75 static int dwmac100_irq_status(void __iomem *ioaddr,
76 struct stmmac_extra_stats *x)
81 static void dwmac100_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
84 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
87 static void dwmac100_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
90 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
93 static void dwmac100_set_filter(struct net_device *dev, int id)
95 void __iomem *ioaddr = (void __iomem *) dev->base_addr;
96 u32 value = readl(ioaddr + MAC_CONTROL);
98 if (dev->flags & IFF_PROMISC) {
99 value |= MAC_CONTROL_PR;
100 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
102 } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
103 || (dev->flags & IFF_ALLMULTI)) {
104 value |= MAC_CONTROL_PM;
105 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
106 writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
107 writel(0xffffffff, ioaddr + MAC_HASH_LOW);
108 } else if (netdev_mc_empty(dev)) { /* no multicast */
109 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
110 MAC_CONTROL_HO | MAC_CONTROL_HP);
113 struct netdev_hw_addr *ha;
115 /* Perfect filter mode for physical address and Hash
116 filter for multicast */
117 value |= MAC_CONTROL_HP;
118 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
119 MAC_CONTROL_IF | MAC_CONTROL_HO);
121 memset(mc_filter, 0, sizeof(mc_filter));
122 netdev_for_each_mc_addr(ha, dev) {
123 /* The upper 6 bits of the calculated CRC are used to
124 * index the contens of the hash table */
126 ether_crc(ETH_ALEN, ha->addr) >> 26;
127 /* The most significant bit determines the register to
128 * use (H/L) while the other 5 bits determine the bit
129 * within the register. */
130 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
132 writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
133 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
136 writel(value, ioaddr + MAC_CONTROL);
138 CHIP_DBG(KERN_INFO "%s: CTRL reg: 0x%08x Hash regs: "
139 "HI 0x%08x, LO 0x%08x\n",
140 __func__, readl(ioaddr + MAC_CONTROL),
141 readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
144 static void dwmac100_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
145 unsigned int fc, unsigned int pause_time)
147 unsigned int flow = MAC_FLOW_CTRL_ENABLE;
150 flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
151 writel(flow, ioaddr + MAC_FLOW_CTRL);
154 /* No PMT module supported for this Ethernet Controller.
155 * Tested on ST platforms only.
157 static void dwmac100_pmt(void __iomem *ioaddr, unsigned long mode)
162 static const struct stmmac_ops dwmac100_ops = {
163 .core_init = dwmac100_core_init,
164 .rx_ipc = dwmac100_rx_ipc_enable,
165 .dump_regs = dwmac100_dump_mac_regs,
166 .host_irq_status = dwmac100_irq_status,
167 .set_filter = dwmac100_set_filter,
168 .flow_ctrl = dwmac100_flow_ctrl,
170 .set_umac_addr = dwmac100_set_umac_addr,
171 .get_umac_addr = dwmac100_get_umac_addr,
174 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr)
176 struct mac_device_info *mac;
178 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
182 pr_info("\tDWMAC100\n");
184 mac->mac = &dwmac100_ops;
185 mac->dma = &dwmac100_dma_ops;
187 mac->link.port = MAC_CONTROL_PS;
188 mac->link.duplex = MAC_CONTROL_F;
190 mac->mii.addr = MAC_MII_ADDR;
191 mac->mii.data = MAC_MII_DATA;
192 mac->synopsys_uid = 0;