1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2010 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
12 #include "bnx2x_fw_defs.h"
17 #if defined(__BIG_ENDIAN)
18 u16 max_iscsi_init_conn;
19 u16 max_iscsi_trgt_conn;
20 #elif defined(__LITTLE_ENDIAN)
21 u16 max_iscsi_trgt_conn;
22 u16 max_iscsi_init_conn;
33 /****************************************************************************
34 * Shared HW configuration *
35 ****************************************************************************/
36 struct shared_hw_cfg { /* NVRAM Offset */
37 /* Up to 16 bytes of NULL-terminated string */
38 u8 part_num[16]; /* 0x104 */
40 u32 config; /* 0x114 */
41 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
42 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
43 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
44 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
45 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
47 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
49 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
51 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
52 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
53 /* Whatever MFW found in NVM
54 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
55 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
56 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
57 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
58 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
59 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
60 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
61 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
62 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
63 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
64 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
65 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
66 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
67 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
69 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
70 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
71 #define SHARED_HW_CFG_LED_MAC1 0x00000000
72 #define SHARED_HW_CFG_LED_PHY1 0x00010000
73 #define SHARED_HW_CFG_LED_PHY2 0x00020000
74 #define SHARED_HW_CFG_LED_PHY3 0x00030000
75 #define SHARED_HW_CFG_LED_MAC2 0x00040000
76 #define SHARED_HW_CFG_LED_PHY4 0x00050000
77 #define SHARED_HW_CFG_LED_PHY5 0x00060000
78 #define SHARED_HW_CFG_LED_PHY6 0x00070000
79 #define SHARED_HW_CFG_LED_MAC3 0x00080000
80 #define SHARED_HW_CFG_LED_PHY7 0x00090000
81 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
82 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
83 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
84 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
85 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
88 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
89 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
90 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
91 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
92 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
93 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
94 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
95 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
97 u32 config2; /* 0x118 */
98 /* one time auto detect grace period (in sec) */
99 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
100 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
102 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
104 /* The default value for the core clock is 250MHz and it is
105 achieved by setting the clock change to 4 */
106 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
107 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
109 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
110 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
112 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
114 /* The fan failure mechanism is usually related to the PHY type
115 since the power consumption of the board is determined by the PHY.
116 Currently, fan is required for most designs with SFX7101, BCM8727
117 and BCM8481. If a fan is not required for a board which uses one
118 of those PHYs, this field should be set to "Disabled". If a fan is
119 required for a different PHY type, this option should be set to
121 The fan failure indication is expected on
123 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
124 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
125 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
126 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
127 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
129 /* Set the MDC/MDIO access for the first external phy */
130 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
131 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
132 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
133 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
134 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
135 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
136 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
138 /* Set the MDC/MDIO access for the second external phy */
139 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
140 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
141 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
142 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
143 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
144 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
145 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
146 u32 power_dissipated; /* 0x11c */
147 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
148 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
150 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
151 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
152 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
153 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
154 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
155 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
157 u32 ump_nc_si_config; /* 0x120 */
158 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
159 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
160 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
161 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
162 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
163 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
165 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
166 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
168 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
169 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
170 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
171 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
173 u32 board; /* 0x124 */
174 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
175 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
177 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
178 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
180 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
181 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
183 u32 reserved; /* 0x128 */
188 /****************************************************************************
189 * Port HW configuration *
190 ****************************************************************************/
191 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
194 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
195 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
198 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
199 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
201 u32 power_dissipated;
202 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
203 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
204 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
205 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
206 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
207 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
208 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
209 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
212 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
213 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
214 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
215 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
216 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
217 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
218 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
219 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
222 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
223 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
226 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
229 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
233 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
234 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
236 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
237 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
240 u32 Reserved0[16]; /* 0x158 */
242 /* for external PHY, or forced mode or during AN */
243 u16 xgxs_config_rx[4]; /* 0x198 */
245 u16 xgxs_config_tx[4]; /* 0x1A0 */
247 u32 Reserved1[56]; /* 0x1A8 */
248 u32 default_cfg; /* 0x288 */
249 /* Enable BAM on KR */
250 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
251 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
252 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
253 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
255 u32 speed_capability_mask2; /* 0x28C */
256 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
257 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
258 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
259 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
260 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
261 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
262 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
263 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
264 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
265 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12G 0x00000080
266 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12_DOT_5G 0x00000100
267 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_13G 0x00000200
268 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_15G 0x00000400
269 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_16G 0x00000800
271 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
272 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
273 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
274 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
275 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
276 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
277 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
278 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
279 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
280 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12G 0x00800000
281 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12_DOT_5G 0x01000000
282 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_13G 0x02000000
283 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_15G 0x04000000
284 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_16G 0x08000000
286 /* In the case where two media types (e.g. copper and fiber) are
287 present and electrically active at the same time, PHY Selection
288 will determine which of the two PHYs will be designated as the
289 Active PHY and used for a connection to the network. */
290 u32 multi_phy_config; /* 0x290 */
291 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
292 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
293 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
294 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
295 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
296 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
297 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
299 /* When enabled, all second phy nvram parameters will be swapped
300 with the first phy parameters */
301 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
302 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
303 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
304 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
307 /* Address of the second external phy */
308 u32 external_phy_config2; /* 0x294 */
309 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
310 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
312 /* The second XGXS external PHY type */
313 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
314 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
315 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
316 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
317 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
318 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
319 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
320 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
321 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
322 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
323 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
324 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
325 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
326 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
327 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
328 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
329 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
330 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
332 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
333 8706, 8726 and 8727) not all 4 values are needed. */
334 u16 xgxs_config2_rx[4]; /* 0x296 */
335 u16 xgxs_config2_tx[4]; /* 0x2A0 */
338 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
339 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
341 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
342 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
343 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
344 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
345 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
346 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
348 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
350 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
352 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
354 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
356 u32 external_phy_config;
357 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
358 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
359 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
360 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
361 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
363 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
364 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
366 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
367 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
368 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
369 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
370 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
371 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
372 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
373 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
374 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
375 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
376 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
377 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
378 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
379 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
380 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
381 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
383 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
384 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
386 u32 speed_capability_mask;
387 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
388 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
389 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
390 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
391 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
392 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
393 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
394 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
395 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
396 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
397 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
398 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
399 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
400 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
401 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
403 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
404 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
405 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
406 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
407 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
408 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
409 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
410 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
411 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
412 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
413 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
414 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
415 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
416 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
417 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
424 /****************************************************************************
425 * Shared Feature configuration *
426 ****************************************************************************/
427 struct shared_feat_cfg { /* NVRAM Offset */
429 u32 config; /* 0x450 */
430 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
432 /* Use the values from options 47 and 48 instead of the HW default
434 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000
435 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002
437 #define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
442 /****************************************************************************
443 * Port Feature configuration *
444 ****************************************************************************/
445 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
448 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
449 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
450 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
451 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
452 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
453 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
454 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
455 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
456 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
457 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
458 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
459 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
460 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
461 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
462 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
463 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
464 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
465 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
466 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
467 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
468 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
469 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
470 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
471 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
472 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
473 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
474 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
475 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
476 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
477 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
478 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
479 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
480 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
481 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
482 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
483 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
484 #define PORT_FEATURE_EN_SIZE_MASK 0x07000000
485 #define PORT_FEATURE_EN_SIZE_SHIFT 24
486 #define PORT_FEATURE_WOL_ENABLED 0x01000000
487 #define PORT_FEATURE_MBA_ENABLED 0x02000000
488 #define PORT_FEATURE_MFW_ENABLED 0x04000000
490 /* Reserved bits: 28-29 */
491 /* Check the optic vendor via i2c against a list of approved modules
492 in a separate nvram image */
493 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
494 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
495 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000
496 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000
497 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
498 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
502 /* Default is used when driver sets to "auto" mode */
503 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
504 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
505 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
506 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
507 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
508 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
509 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
510 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
511 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
514 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
515 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
516 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
517 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
518 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
519 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
520 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
521 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
522 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
523 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
524 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
525 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
526 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
527 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
528 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
529 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
530 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
531 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
532 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
533 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
534 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
535 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
536 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
537 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
538 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
539 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
540 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
541 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
542 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
543 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
544 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
545 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
546 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
547 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
548 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
549 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
550 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
551 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
552 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
553 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
554 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
555 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
556 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
557 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
558 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
559 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
560 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
561 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
562 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
563 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
564 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
565 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
566 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
567 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
570 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
571 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
574 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
575 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
576 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
579 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
580 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
581 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
582 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
583 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
587 #define PORT_FEATURE_SMBUS_EN 0x00000001
588 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
589 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
593 u32 link_config; /* Used as HW defaults for the driver */
594 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
595 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
596 /* (forced) low speed switch (< 10G) */
597 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
598 /* (forced) high speed switch (>= 10G) */
599 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
600 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
601 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
603 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
604 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
605 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
606 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
607 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
608 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
609 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
610 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
611 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
612 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
613 #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
614 #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
615 #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
616 #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
617 #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
618 #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
619 #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
621 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
622 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
623 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
624 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
625 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
626 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
627 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
629 /* The default for MCP link configuration,
630 uses the same defines as link_config */
631 u32 mfw_wol_link_cfg;
632 /* The default for the driver of the second external phy,
633 uses the same defines as link_config */
634 u32 link_config2; /* 0x47C */
636 /* The default for MCP of the second external phy,
637 uses the same defines as link_config */
638 u32 mfw_wol_link_cfg2; /* 0x480 */
640 u32 Reserved2[17]; /* 0x484 */
645 /****************************************************************************
646 * Device Information *
647 ****************************************************************************/
648 struct shm_dev_info { /* size */
650 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
652 struct shared_hw_cfg shared_hw_config; /* 40 */
654 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
656 struct shared_feat_cfg shared_feature_config; /* 4 */
658 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
671 #define E1_FUNC_MAX 2
672 #define E1H_FUNC_MAX 8
673 #define E2_FUNC_MAX 4 /* per path */
683 /* This value (in milliseconds) determines the frequency of the driver
684 * issuing the PULSE message code. The firmware monitors this periodic
685 * pulse to determine when to switch to an OS-absent mode. */
686 #define DRV_PULSE_PERIOD_MS 250
688 /* This value (in milliseconds) determines how long the driver should
689 * wait for an acknowledgement from the firmware before timing out. Once
690 * the firmware has timed out, the driver will assume there is no firmware
691 * running and there won't be any firmware-driver synchronization during a
693 #define FW_ACK_TIME_OUT_MS 5000
695 #define FW_ACK_POLL_TIME_MS 1
697 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
699 /* LED Blink rate that will achieve ~15.9Hz */
700 #define LED_BLINK_RATE_VAL 480
702 /****************************************************************************
703 * Driver <-> FW Mailbox *
704 ****************************************************************************/
708 /* Driver should update this field on any link change event */
710 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
711 #define LINK_STATUS_LINK_UP 0x00000001
712 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
713 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
714 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
715 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
716 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
717 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
718 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
719 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
720 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
721 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
722 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
723 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
724 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
725 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
726 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
727 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
728 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
729 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
730 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
731 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
732 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
733 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
734 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
735 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
736 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
738 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
739 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
741 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
742 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
743 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
745 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
746 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
747 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
748 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
749 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
750 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
751 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
753 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
754 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
756 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
757 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
759 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
760 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
761 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
762 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
763 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
765 #define LINK_STATUS_SERDES_LINK 0x00100000
767 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
768 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
769 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
770 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
771 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
772 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
773 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
774 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
780 /* MCP firmware does not use this field */
781 u32 ext_phy_fw_version;
789 #define DRV_MSG_CODE_MASK 0xffff0000
790 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
791 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
792 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
793 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
794 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
795 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
796 #define DRV_MSG_CODE_DCC_OK 0x30000000
797 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
798 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
799 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
800 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
801 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
802 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
803 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
804 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
806 * The optic module verification commands require bootcode
809 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
810 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
812 * The specific optic module verification command requires bootcode
815 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
816 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
818 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
819 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
820 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
821 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
823 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
828 #define FW_MSG_CODE_MASK 0xffff0000
829 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
830 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
831 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
832 /* Load common chip is supported from bc 6.0.0 */
833 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
834 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
835 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
836 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
837 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
838 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
839 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
840 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
841 #define FW_MSG_CODE_DCC_DONE 0x30100000
842 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
843 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
844 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
845 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
846 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
847 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
848 #define FW_MSG_CODE_NO_KEY 0x80f00000
849 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
850 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
851 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
852 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
853 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
854 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
855 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
856 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
857 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
859 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
860 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
861 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
862 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
864 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
869 #define DRV_PULSE_SEQ_MASK 0x00007fff
870 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
871 /* The system time is in the format of
872 * (year-2001)*12*32 + month*32 + day. */
873 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
874 /* Indicate to the firmware not to go into the
875 * OS-absent when it is not getting driver pulse.
876 * This is used for debugging as well for PXE(MBA). */
879 #define MCP_PULSE_SEQ_MASK 0x00007fff
880 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
881 /* Indicates to the driver not to assert due to lack
883 #define MCP_EVENT_MASK 0xffff0000
884 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
886 u32 iscsi_boot_signature;
887 u32 iscsi_boot_block_offset;
890 #define DRV_STATUS_PMF 0x00000001
892 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
893 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
894 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
895 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
896 #define DRV_STATUS_DCC_RESERVED1 0x00000800
897 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
898 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
901 #define VIRT_MAC_SIGN_MASK 0xffff0000
902 #define VIRT_MAC_SIGNATURE 0x564d0000
908 /****************************************************************************
909 * Management firmware state *
910 ****************************************************************************/
911 /* Allocate 440 bytes for management firmware */
912 #define MGMTFW_STATE_WORD_SIZE 110
914 struct mgmtfw_state {
915 u32 opaque[MGMTFW_STATE_WORD_SIZE];
919 /****************************************************************************
920 * Multi-Function configuration *
921 ****************************************************************************/
922 struct shared_mf_cfg {
925 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
927 #define SHARED_MF_CLP_EXIT 0x00000001
929 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
935 u32 dynamic_cfg; /* device control channel */
936 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
937 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
938 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
948 /* function 0 of each port cannot be hidden */
949 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
951 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
952 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
953 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
954 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
955 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
956 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
958 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
961 /* 0 - low priority, 3 - high priority */
962 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
963 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
964 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
967 /* value range - 0..100, increments in 100Mbps */
968 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
969 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
970 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
971 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
972 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
973 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
975 u32 mac_upper; /* MAC */
976 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
977 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
978 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
980 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
982 u32 e1hov_tag; /* VNI */
983 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
984 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
985 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
993 struct shared_mf_cfg shared_mf_config;
994 struct port_mf_cfg port_mf_config[PORT_MAX];
995 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
1000 /****************************************************************************
1001 * Shared Memory Region *
1002 ****************************************************************************/
1003 struct shmem_region { /* SharedMem Offset (size) */
1005 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1006 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1007 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1009 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1010 #define SHR_MEM_VALIDITY_MB 0x00200000
1011 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1012 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1013 /* One licensing bit should be set */
1014 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1015 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1016 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1017 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1019 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1020 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1021 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1022 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1023 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1024 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1026 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1028 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1030 /* FW information (for internal FW use) */
1031 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1032 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1034 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1035 struct drv_func_mb func_mb[]; /* 0x684
1036 (44*2/4/8=0x58/0xb0/0x160) */
1038 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1049 struct fw_flr_ack ack;
1053 struct shmem2_region {
1058 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
1059 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1060 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1061 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1062 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1063 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1064 #define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE
1065 u32 ext_phy_fw_version2[PORT_MAX];
1067 * For backwards compatibility, if the mf_cfg_addr does not exist
1068 * (the size filed is smaller than 0xc) the mf_cfg resides at the
1069 * end of struct shmem_region
1072 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
1074 struct fw_flr_mb flr_mb;
1077 * The other shmemX_base_addr holds the other path's shmem address
1078 * required for example in case of common phy init, or for path1 to know
1079 * the address of mcp debug trace which is located in offset from shmem
1082 u32 other_shmem_base_addr;
1083 u32 other_shmem2_base_addr;
1088 u32 rx_stat_ifhcinoctets;
1089 u32 rx_stat_ifhcinbadoctets;
1090 u32 rx_stat_etherstatsfragments;
1091 u32 rx_stat_ifhcinucastpkts;
1092 u32 rx_stat_ifhcinmulticastpkts;
1093 u32 rx_stat_ifhcinbroadcastpkts;
1094 u32 rx_stat_dot3statsfcserrors;
1095 u32 rx_stat_dot3statsalignmenterrors;
1096 u32 rx_stat_dot3statscarriersenseerrors;
1097 u32 rx_stat_xonpauseframesreceived;
1098 u32 rx_stat_xoffpauseframesreceived;
1099 u32 rx_stat_maccontrolframesreceived;
1100 u32 rx_stat_xoffstateentered;
1101 u32 rx_stat_dot3statsframestoolong;
1102 u32 rx_stat_etherstatsjabbers;
1103 u32 rx_stat_etherstatsundersizepkts;
1104 u32 rx_stat_etherstatspkts64octets;
1105 u32 rx_stat_etherstatspkts65octetsto127octets;
1106 u32 rx_stat_etherstatspkts128octetsto255octets;
1107 u32 rx_stat_etherstatspkts256octetsto511octets;
1108 u32 rx_stat_etherstatspkts512octetsto1023octets;
1109 u32 rx_stat_etherstatspkts1024octetsto1522octets;
1110 u32 rx_stat_etherstatspktsover1522octets;
1112 u32 rx_stat_falsecarriererrors;
1114 u32 tx_stat_ifhcoutoctets;
1115 u32 tx_stat_ifhcoutbadoctets;
1116 u32 tx_stat_etherstatscollisions;
1117 u32 tx_stat_outxonsent;
1118 u32 tx_stat_outxoffsent;
1119 u32 tx_stat_flowcontroldone;
1120 u32 tx_stat_dot3statssinglecollisionframes;
1121 u32 tx_stat_dot3statsmultiplecollisionframes;
1122 u32 tx_stat_dot3statsdeferredtransmissions;
1123 u32 tx_stat_dot3statsexcessivecollisions;
1124 u32 tx_stat_dot3statslatecollisions;
1125 u32 tx_stat_ifhcoutucastpkts;
1126 u32 tx_stat_ifhcoutmulticastpkts;
1127 u32 tx_stat_ifhcoutbroadcastpkts;
1128 u32 tx_stat_etherstatspkts64octets;
1129 u32 tx_stat_etherstatspkts65octetsto127octets;
1130 u32 tx_stat_etherstatspkts128octetsto255octets;
1131 u32 tx_stat_etherstatspkts256octetsto511octets;
1132 u32 tx_stat_etherstatspkts512octetsto1023octets;
1133 u32 tx_stat_etherstatspkts1024octetsto1522octets;
1134 u32 tx_stat_etherstatspktsover1522octets;
1135 u32 tx_stat_dot3statsinternalmactransmiterrors;
1139 struct bmac1_stats {
1140 u32 tx_stat_gtpkt_lo;
1141 u32 tx_stat_gtpkt_hi;
1142 u32 tx_stat_gtxpf_lo;
1143 u32 tx_stat_gtxpf_hi;
1144 u32 tx_stat_gtfcs_lo;
1145 u32 tx_stat_gtfcs_hi;
1146 u32 tx_stat_gtmca_lo;
1147 u32 tx_stat_gtmca_hi;
1148 u32 tx_stat_gtbca_lo;
1149 u32 tx_stat_gtbca_hi;
1150 u32 tx_stat_gtfrg_lo;
1151 u32 tx_stat_gtfrg_hi;
1152 u32 tx_stat_gtovr_lo;
1153 u32 tx_stat_gtovr_hi;
1154 u32 tx_stat_gt64_lo;
1155 u32 tx_stat_gt64_hi;
1156 u32 tx_stat_gt127_lo;
1157 u32 tx_stat_gt127_hi;
1158 u32 tx_stat_gt255_lo;
1159 u32 tx_stat_gt255_hi;
1160 u32 tx_stat_gt511_lo;
1161 u32 tx_stat_gt511_hi;
1162 u32 tx_stat_gt1023_lo;
1163 u32 tx_stat_gt1023_hi;
1164 u32 tx_stat_gt1518_lo;
1165 u32 tx_stat_gt1518_hi;
1166 u32 tx_stat_gt2047_lo;
1167 u32 tx_stat_gt2047_hi;
1168 u32 tx_stat_gt4095_lo;
1169 u32 tx_stat_gt4095_hi;
1170 u32 tx_stat_gt9216_lo;
1171 u32 tx_stat_gt9216_hi;
1172 u32 tx_stat_gt16383_lo;
1173 u32 tx_stat_gt16383_hi;
1174 u32 tx_stat_gtmax_lo;
1175 u32 tx_stat_gtmax_hi;
1176 u32 tx_stat_gtufl_lo;
1177 u32 tx_stat_gtufl_hi;
1178 u32 tx_stat_gterr_lo;
1179 u32 tx_stat_gterr_hi;
1180 u32 tx_stat_gtbyt_lo;
1181 u32 tx_stat_gtbyt_hi;
1183 u32 rx_stat_gr64_lo;
1184 u32 rx_stat_gr64_hi;
1185 u32 rx_stat_gr127_lo;
1186 u32 rx_stat_gr127_hi;
1187 u32 rx_stat_gr255_lo;
1188 u32 rx_stat_gr255_hi;
1189 u32 rx_stat_gr511_lo;
1190 u32 rx_stat_gr511_hi;
1191 u32 rx_stat_gr1023_lo;
1192 u32 rx_stat_gr1023_hi;
1193 u32 rx_stat_gr1518_lo;
1194 u32 rx_stat_gr1518_hi;
1195 u32 rx_stat_gr2047_lo;
1196 u32 rx_stat_gr2047_hi;
1197 u32 rx_stat_gr4095_lo;
1198 u32 rx_stat_gr4095_hi;
1199 u32 rx_stat_gr9216_lo;
1200 u32 rx_stat_gr9216_hi;
1201 u32 rx_stat_gr16383_lo;
1202 u32 rx_stat_gr16383_hi;
1203 u32 rx_stat_grmax_lo;
1204 u32 rx_stat_grmax_hi;
1205 u32 rx_stat_grpkt_lo;
1206 u32 rx_stat_grpkt_hi;
1207 u32 rx_stat_grfcs_lo;
1208 u32 rx_stat_grfcs_hi;
1209 u32 rx_stat_grmca_lo;
1210 u32 rx_stat_grmca_hi;
1211 u32 rx_stat_grbca_lo;
1212 u32 rx_stat_grbca_hi;
1213 u32 rx_stat_grxcf_lo;
1214 u32 rx_stat_grxcf_hi;
1215 u32 rx_stat_grxpf_lo;
1216 u32 rx_stat_grxpf_hi;
1217 u32 rx_stat_grxuo_lo;
1218 u32 rx_stat_grxuo_hi;
1219 u32 rx_stat_grjbr_lo;
1220 u32 rx_stat_grjbr_hi;
1221 u32 rx_stat_grovr_lo;
1222 u32 rx_stat_grovr_hi;
1223 u32 rx_stat_grflr_lo;
1224 u32 rx_stat_grflr_hi;
1225 u32 rx_stat_grmeg_lo;
1226 u32 rx_stat_grmeg_hi;
1227 u32 rx_stat_grmeb_lo;
1228 u32 rx_stat_grmeb_hi;
1229 u32 rx_stat_grbyt_lo;
1230 u32 rx_stat_grbyt_hi;
1231 u32 rx_stat_grund_lo;
1232 u32 rx_stat_grund_hi;
1233 u32 rx_stat_grfrg_lo;
1234 u32 rx_stat_grfrg_hi;
1235 u32 rx_stat_grerb_lo;
1236 u32 rx_stat_grerb_hi;
1237 u32 rx_stat_grfre_lo;
1238 u32 rx_stat_grfre_hi;
1239 u32 rx_stat_gripj_lo;
1240 u32 rx_stat_gripj_hi;
1243 struct bmac2_stats {
1244 u32 tx_stat_gtpk_lo; /* gtpok */
1245 u32 tx_stat_gtpk_hi; /* gtpok */
1246 u32 tx_stat_gtxpf_lo; /* gtpf */
1247 u32 tx_stat_gtxpf_hi; /* gtpf */
1248 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */
1249 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */
1250 u32 tx_stat_gtfcs_lo;
1251 u32 tx_stat_gtfcs_hi;
1252 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */
1253 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */
1254 u32 tx_stat_gtmca_lo;
1255 u32 tx_stat_gtmca_hi;
1256 u32 tx_stat_gtbca_lo;
1257 u32 tx_stat_gtbca_hi;
1258 u32 tx_stat_gtovr_lo;
1259 u32 tx_stat_gtovr_hi;
1260 u32 tx_stat_gtfrg_lo;
1261 u32 tx_stat_gtfrg_hi;
1262 u32 tx_stat_gtpkt1_lo; /* gtpkt */
1263 u32 tx_stat_gtpkt1_hi; /* gtpkt */
1264 u32 tx_stat_gt64_lo;
1265 u32 tx_stat_gt64_hi;
1266 u32 tx_stat_gt127_lo;
1267 u32 tx_stat_gt127_hi;
1268 u32 tx_stat_gt255_lo;
1269 u32 tx_stat_gt255_hi;
1270 u32 tx_stat_gt511_lo;
1271 u32 tx_stat_gt511_hi;
1272 u32 tx_stat_gt1023_lo;
1273 u32 tx_stat_gt1023_hi;
1274 u32 tx_stat_gt1518_lo;
1275 u32 tx_stat_gt1518_hi;
1276 u32 tx_stat_gt2047_lo;
1277 u32 tx_stat_gt2047_hi;
1278 u32 tx_stat_gt4095_lo;
1279 u32 tx_stat_gt4095_hi;
1280 u32 tx_stat_gt9216_lo;
1281 u32 tx_stat_gt9216_hi;
1282 u32 tx_stat_gt16383_lo;
1283 u32 tx_stat_gt16383_hi;
1284 u32 tx_stat_gtmax_lo;
1285 u32 tx_stat_gtmax_hi;
1286 u32 tx_stat_gtufl_lo;
1287 u32 tx_stat_gtufl_hi;
1288 u32 tx_stat_gterr_lo;
1289 u32 tx_stat_gterr_hi;
1290 u32 tx_stat_gtbyt_lo;
1291 u32 tx_stat_gtbyt_hi;
1293 u32 rx_stat_gr64_lo;
1294 u32 rx_stat_gr64_hi;
1295 u32 rx_stat_gr127_lo;
1296 u32 rx_stat_gr127_hi;
1297 u32 rx_stat_gr255_lo;
1298 u32 rx_stat_gr255_hi;
1299 u32 rx_stat_gr511_lo;
1300 u32 rx_stat_gr511_hi;
1301 u32 rx_stat_gr1023_lo;
1302 u32 rx_stat_gr1023_hi;
1303 u32 rx_stat_gr1518_lo;
1304 u32 rx_stat_gr1518_hi;
1305 u32 rx_stat_gr2047_lo;
1306 u32 rx_stat_gr2047_hi;
1307 u32 rx_stat_gr4095_lo;
1308 u32 rx_stat_gr4095_hi;
1309 u32 rx_stat_gr9216_lo;
1310 u32 rx_stat_gr9216_hi;
1311 u32 rx_stat_gr16383_lo;
1312 u32 rx_stat_gr16383_hi;
1313 u32 rx_stat_grmax_lo;
1314 u32 rx_stat_grmax_hi;
1315 u32 rx_stat_grpkt_lo;
1316 u32 rx_stat_grpkt_hi;
1317 u32 rx_stat_grfcs_lo;
1318 u32 rx_stat_grfcs_hi;
1319 u32 rx_stat_gruca_lo;
1320 u32 rx_stat_gruca_hi;
1321 u32 rx_stat_grmca_lo;
1322 u32 rx_stat_grmca_hi;
1323 u32 rx_stat_grbca_lo;
1324 u32 rx_stat_grbca_hi;
1325 u32 rx_stat_grxpf_lo; /* grpf */
1326 u32 rx_stat_grxpf_hi; /* grpf */
1327 u32 rx_stat_grpp_lo;
1328 u32 rx_stat_grpp_hi;
1329 u32 rx_stat_grxuo_lo; /* gruo */
1330 u32 rx_stat_grxuo_hi; /* gruo */
1331 u32 rx_stat_grjbr_lo;
1332 u32 rx_stat_grjbr_hi;
1333 u32 rx_stat_grovr_lo;
1334 u32 rx_stat_grovr_hi;
1335 u32 rx_stat_grxcf_lo; /* grcf */
1336 u32 rx_stat_grxcf_hi; /* grcf */
1337 u32 rx_stat_grflr_lo;
1338 u32 rx_stat_grflr_hi;
1339 u32 rx_stat_grpok_lo;
1340 u32 rx_stat_grpok_hi;
1341 u32 rx_stat_grmeg_lo;
1342 u32 rx_stat_grmeg_hi;
1343 u32 rx_stat_grmeb_lo;
1344 u32 rx_stat_grmeb_hi;
1345 u32 rx_stat_grbyt_lo;
1346 u32 rx_stat_grbyt_hi;
1347 u32 rx_stat_grund_lo;
1348 u32 rx_stat_grund_hi;
1349 u32 rx_stat_grfrg_lo;
1350 u32 rx_stat_grfrg_hi;
1351 u32 rx_stat_grerb_lo; /* grerrbyt */
1352 u32 rx_stat_grerb_hi; /* grerrbyt */
1353 u32 rx_stat_grfre_lo; /* grfrerr */
1354 u32 rx_stat_grfre_hi; /* grfrerr */
1355 u32 rx_stat_gripj_lo;
1356 u32 rx_stat_gripj_hi;
1360 struct emac_stats emac_stats;
1361 struct bmac1_stats bmac1_stats;
1362 struct bmac2_stats bmac2_stats;
1368 u32 rx_stat_ifhcinbadoctets_hi;
1369 u32 rx_stat_ifhcinbadoctets_lo;
1371 /* out_bad_octets */
1372 u32 tx_stat_ifhcoutbadoctets_hi;
1373 u32 tx_stat_ifhcoutbadoctets_lo;
1375 /* crc_receive_errors */
1376 u32 rx_stat_dot3statsfcserrors_hi;
1377 u32 rx_stat_dot3statsfcserrors_lo;
1378 /* alignment_errors */
1379 u32 rx_stat_dot3statsalignmenterrors_hi;
1380 u32 rx_stat_dot3statsalignmenterrors_lo;
1381 /* carrier_sense_errors */
1382 u32 rx_stat_dot3statscarriersenseerrors_hi;
1383 u32 rx_stat_dot3statscarriersenseerrors_lo;
1384 /* false_carrier_detections */
1385 u32 rx_stat_falsecarriererrors_hi;
1386 u32 rx_stat_falsecarriererrors_lo;
1388 /* runt_packets_received */
1389 u32 rx_stat_etherstatsundersizepkts_hi;
1390 u32 rx_stat_etherstatsundersizepkts_lo;
1391 /* jabber_packets_received */
1392 u32 rx_stat_dot3statsframestoolong_hi;
1393 u32 rx_stat_dot3statsframestoolong_lo;
1395 /* error_runt_packets_received */
1396 u32 rx_stat_etherstatsfragments_hi;
1397 u32 rx_stat_etherstatsfragments_lo;
1398 /* error_jabber_packets_received */
1399 u32 rx_stat_etherstatsjabbers_hi;
1400 u32 rx_stat_etherstatsjabbers_lo;
1402 /* control_frames_received */
1403 u32 rx_stat_maccontrolframesreceived_hi;
1404 u32 rx_stat_maccontrolframesreceived_lo;
1405 u32 rx_stat_bmac_xpf_hi;
1406 u32 rx_stat_bmac_xpf_lo;
1407 u32 rx_stat_bmac_xcf_hi;
1408 u32 rx_stat_bmac_xcf_lo;
1410 /* xoff_state_entered */
1411 u32 rx_stat_xoffstateentered_hi;
1412 u32 rx_stat_xoffstateentered_lo;
1413 /* pause_xon_frames_received */
1414 u32 rx_stat_xonpauseframesreceived_hi;
1415 u32 rx_stat_xonpauseframesreceived_lo;
1416 /* pause_xoff_frames_received */
1417 u32 rx_stat_xoffpauseframesreceived_hi;
1418 u32 rx_stat_xoffpauseframesreceived_lo;
1419 /* pause_xon_frames_transmitted */
1420 u32 tx_stat_outxonsent_hi;
1421 u32 tx_stat_outxonsent_lo;
1422 /* pause_xoff_frames_transmitted */
1423 u32 tx_stat_outxoffsent_hi;
1424 u32 tx_stat_outxoffsent_lo;
1425 /* flow_control_done */
1426 u32 tx_stat_flowcontroldone_hi;
1427 u32 tx_stat_flowcontroldone_lo;
1429 /* ether_stats_collisions */
1430 u32 tx_stat_etherstatscollisions_hi;
1431 u32 tx_stat_etherstatscollisions_lo;
1432 /* single_collision_transmit_frames */
1433 u32 tx_stat_dot3statssinglecollisionframes_hi;
1434 u32 tx_stat_dot3statssinglecollisionframes_lo;
1435 /* multiple_collision_transmit_frames */
1436 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
1437 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
1438 /* deferred_transmissions */
1439 u32 tx_stat_dot3statsdeferredtransmissions_hi;
1440 u32 tx_stat_dot3statsdeferredtransmissions_lo;
1441 /* excessive_collision_frames */
1442 u32 tx_stat_dot3statsexcessivecollisions_hi;
1443 u32 tx_stat_dot3statsexcessivecollisions_lo;
1444 /* late_collision_frames */
1445 u32 tx_stat_dot3statslatecollisions_hi;
1446 u32 tx_stat_dot3statslatecollisions_lo;
1448 /* frames_transmitted_64_bytes */
1449 u32 tx_stat_etherstatspkts64octets_hi;
1450 u32 tx_stat_etherstatspkts64octets_lo;
1451 /* frames_transmitted_65_127_bytes */
1452 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
1453 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
1454 /* frames_transmitted_128_255_bytes */
1455 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
1456 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
1457 /* frames_transmitted_256_511_bytes */
1458 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
1459 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
1460 /* frames_transmitted_512_1023_bytes */
1461 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
1462 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
1463 /* frames_transmitted_1024_1522_bytes */
1464 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
1465 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
1466 /* frames_transmitted_1523_9022_bytes */
1467 u32 tx_stat_etherstatspktsover1522octets_hi;
1468 u32 tx_stat_etherstatspktsover1522octets_lo;
1469 u32 tx_stat_bmac_2047_hi;
1470 u32 tx_stat_bmac_2047_lo;
1471 u32 tx_stat_bmac_4095_hi;
1472 u32 tx_stat_bmac_4095_lo;
1473 u32 tx_stat_bmac_9216_hi;
1474 u32 tx_stat_bmac_9216_lo;
1475 u32 tx_stat_bmac_16383_hi;
1476 u32 tx_stat_bmac_16383_lo;
1478 /* internal_mac_transmit_errors */
1479 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
1480 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
1482 /* if_out_discards */
1483 u32 tx_stat_bmac_ufl_hi;
1484 u32 tx_stat_bmac_ufl_lo;
1488 #define MAC_STX_IDX_MAX 2
1490 struct host_port_stats {
1491 u32 host_port_stats_start;
1493 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1498 u32 host_port_stats_end;
1502 struct host_func_stats {
1503 u32 host_func_stats_start;
1505 u32 total_bytes_received_hi;
1506 u32 total_bytes_received_lo;
1508 u32 total_bytes_transmitted_hi;
1509 u32 total_bytes_transmitted_lo;
1511 u32 total_unicast_packets_received_hi;
1512 u32 total_unicast_packets_received_lo;
1514 u32 total_multicast_packets_received_hi;
1515 u32 total_multicast_packets_received_lo;
1517 u32 total_broadcast_packets_received_hi;
1518 u32 total_broadcast_packets_received_lo;
1520 u32 total_unicast_packets_transmitted_hi;
1521 u32 total_unicast_packets_transmitted_lo;
1523 u32 total_multicast_packets_transmitted_hi;
1524 u32 total_multicast_packets_transmitted_lo;
1526 u32 total_broadcast_packets_transmitted_hi;
1527 u32 total_broadcast_packets_transmitted_lo;
1529 u32 valid_bytes_received_hi;
1530 u32 valid_bytes_received_lo;
1532 u32 host_func_stats_end;
1536 #define BCM_5710_FW_MAJOR_VERSION 6
1537 #define BCM_5710_FW_MINOR_VERSION 0
1538 #define BCM_5710_FW_REVISION_VERSION 34
1539 #define BCM_5710_FW_ENGINEERING_VERSION 0
1540 #define BCM_5710_FW_COMPILE_FLAGS 1
1546 struct atten_sp_status_block {
1548 __le32 attn_bits_ack;
1551 __le16 attn_bits_index;
1557 * common data for all protocols
1559 struct doorbell_hdr {
1561 #define DOORBELL_HDR_RX (0x1<<0)
1562 #define DOORBELL_HDR_RX_SHIFT 0
1563 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1564 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1565 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1566 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1567 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1568 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1572 * doorbell message sent to the chip
1575 #if defined(__BIG_ENDIAN)
1578 struct doorbell_hdr header;
1579 #elif defined(__LITTLE_ENDIAN)
1580 struct doorbell_hdr header;
1588 * doorbell message sent to the chip
1590 struct doorbell_set_prod {
1591 #if defined(__BIG_ENDIAN)
1594 struct doorbell_hdr header;
1595 #elif defined(__LITTLE_ENDIAN)
1596 struct doorbell_hdr header;
1604 * 3 lines. status block
1606 struct hc_status_block_e1x {
1607 __le16 index_values[HC_SB_MAX_INDICES_E1X];
1608 __le16 running_index[HC_SB_MAX_SM];
1615 struct host_hc_status_block_e1x {
1616 struct hc_status_block_e1x sb;
1621 * 3 lines. status block
1623 struct hc_status_block_e2 {
1624 __le16 index_values[HC_SB_MAX_INDICES_E2];
1625 __le16 running_index[HC_SB_MAX_SM];
1632 struct host_hc_status_block_e2 {
1633 struct hc_status_block_e2 sb;
1638 * 5 lines. slow-path status block
1640 struct hc_sp_status_block {
1641 __le16 index_values[HC_SP_SB_MAX_INDICES];
1642 __le16 running_index;
1650 struct host_sp_status_block {
1651 struct atten_sp_status_block atten_status_block;
1652 struct hc_sp_status_block sp_sb;
1657 * IGU driver acknowledgment register
1659 struct igu_ack_register {
1660 #if defined(__BIG_ENDIAN)
1661 u16 sb_id_and_flags;
1662 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1663 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1664 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1665 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1666 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1667 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1668 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1669 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1670 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1671 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1672 u16 status_block_index;
1673 #elif defined(__LITTLE_ENDIAN)
1674 u16 status_block_index;
1675 u16 sb_id_and_flags;
1676 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1677 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1678 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1679 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1680 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1681 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1682 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1683 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1684 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1685 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1691 * IGU driver acknowledgement register
1693 struct igu_backward_compatible {
1694 u32 sb_id_and_flags;
1695 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
1696 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
1697 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
1698 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
1699 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
1700 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
1701 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
1702 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
1703 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
1704 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
1705 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
1706 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
1712 * IGU driver acknowledgement register
1714 struct igu_regular {
1715 u32 sb_id_and_flags;
1716 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
1717 #define IGU_REGULAR_SB_INDEX_SHIFT 0
1718 #define IGU_REGULAR_RESERVED0 (0x1<<20)
1719 #define IGU_REGULAR_RESERVED0_SHIFT 20
1720 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
1721 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
1722 #define IGU_REGULAR_BUPDATE (0x1<<24)
1723 #define IGU_REGULAR_BUPDATE_SHIFT 24
1724 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
1725 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
1726 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
1727 #define IGU_REGULAR_RESERVED_1_SHIFT 27
1728 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
1729 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
1730 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
1731 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
1732 #define IGU_REGULAR_BCLEANUP (0x1<<31)
1733 #define IGU_REGULAR_BCLEANUP_SHIFT 31
1738 * IGU driver acknowledgement register
1740 union igu_consprod_reg {
1741 struct igu_regular regular;
1742 struct igu_backward_compatible backward_compatible;
1747 * Control register for the IGU command register
1749 struct igu_ctrl_reg {
1751 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
1752 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
1753 #define IGU_CTRL_REG_FID (0x7F<<12)
1754 #define IGU_CTRL_REG_FID_SHIFT 12
1755 #define IGU_CTRL_REG_RESERVED (0x1<<19)
1756 #define IGU_CTRL_REG_RESERVED_SHIFT 19
1757 #define IGU_CTRL_REG_TYPE (0x1<<20)
1758 #define IGU_CTRL_REG_TYPE_SHIFT 20
1759 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
1760 #define IGU_CTRL_REG_UNUSED_SHIFT 21
1765 * Parser parsing flags field
1767 struct parsing_flags {
1769 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1770 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1771 #define PARSING_FLAGS_VLAN (0x1<<1)
1772 #define PARSING_FLAGS_VLAN_SHIFT 1
1773 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1774 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1775 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1776 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1777 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1778 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1779 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1780 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1781 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1782 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1783 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1784 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1785 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1786 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1787 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1788 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1789 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1790 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1791 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1792 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1793 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1794 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1805 * dmae command structure
1807 struct dmae_command {
1809 #define DMAE_COMMAND_SRC (0x1<<0)
1810 #define DMAE_COMMAND_SRC_SHIFT 0
1811 #define DMAE_COMMAND_DST (0x3<<1)
1812 #define DMAE_COMMAND_DST_SHIFT 1
1813 #define DMAE_COMMAND_C_DST (0x1<<3)
1814 #define DMAE_COMMAND_C_DST_SHIFT 3
1815 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1816 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1817 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1818 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1819 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1820 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1821 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1822 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1823 #define DMAE_COMMAND_PORT (0x1<<11)
1824 #define DMAE_COMMAND_PORT_SHIFT 11
1825 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1826 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1827 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1828 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1829 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1830 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1831 #define DMAE_COMMAND_E1HVN (0x3<<15)
1832 #define DMAE_COMMAND_E1HVN_SHIFT 15
1833 #define DMAE_COMMAND_DST_VN (0x3<<17)
1834 #define DMAE_COMMAND_DST_VN_SHIFT 17
1835 #define DMAE_COMMAND_C_FUNC (0x1<<19)
1836 #define DMAE_COMMAND_C_FUNC_SHIFT 19
1837 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
1838 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
1839 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
1840 #define DMAE_COMMAND_RESERVED0_SHIFT 22
1845 #if defined(__BIG_ENDIAN)
1848 #elif defined(__LITTLE_ENDIAN)
1857 #if defined(__BIG_ENDIAN)
1860 #elif defined(__LITTLE_ENDIAN)
1864 #if defined(__BIG_ENDIAN)
1867 #elif defined(__LITTLE_ENDIAN)
1871 #if defined(__BIG_ENDIAN)
1874 #elif defined(__LITTLE_ENDIAN)
1881 struct double_regpair {
1890 * SDM operation gen command (generate aggregative interrupt)
1894 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
1895 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1896 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
1897 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
1898 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
1899 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
1900 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
1901 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
1902 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
1903 #define SDM_OP_GEN_RESERVED_SHIFT 17
1907 * The eth Rx Buffer Descriptor
1915 * The eth Rx SGE Descriptor
1925 * The eth storm context of Ustorm
1927 struct ustorm_eth_st_context {
1932 * The eth storm context of Tstorm
1934 struct tstorm_eth_st_context {
1935 u32 __reserved0[28];
1939 * The eth aggregative context of Xstorm
1941 struct xstorm_eth_ag_context {
1943 #if defined(__BIG_ENDIAN)
1947 #elif defined(__LITTLE_ENDIAN)
1956 * The eth aggregative context of Tstorm
1958 struct tstorm_eth_ag_context {
1959 u32 __reserved0[14];
1964 * The eth aggregative context of Cstorm
1966 struct cstorm_eth_ag_context {
1967 u32 __reserved0[10];
1972 * The eth aggregative context of Ustorm
1974 struct ustorm_eth_ag_context {
1976 #if defined(__BIG_ENDIAN)
1980 #elif defined(__LITTLE_ENDIAN)
1989 * Timers connection context
1991 struct timers_block_context {
1996 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1997 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1998 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1999 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
2000 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
2001 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
2005 * structure for easy accessibility to assembler
2007 struct eth_tx_bd_flags {
2009 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
2010 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
2011 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
2012 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
2013 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
2014 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
2015 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
2016 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
2017 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
2018 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
2019 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
2020 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
2021 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
2022 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
2026 * The eth Tx Buffer Descriptor
2028 struct eth_tx_start_bd {
2033 __le16 vlan_or_ethertype;
2034 struct eth_tx_bd_flags bd_flags;
2036 #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
2037 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
2038 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
2039 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
2043 * Tx regular BD structure
2048 __le16 total_pkt_bytes;
2054 * Tx parsing BD structure for ETH E1/E1h
2056 struct eth_tx_parse_bd_e1x {
2058 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
2059 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
2060 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
2061 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
2062 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
2063 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
2064 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
2065 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
2066 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
2067 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
2069 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
2070 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
2071 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
2072 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
2073 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
2074 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
2075 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
2076 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
2077 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
2078 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
2079 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
2080 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
2081 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
2082 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
2083 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
2084 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
2087 __le16 total_hlen_w;
2088 __le16 tcp_pseudo_csum;
2091 __le32 tcp_send_seq;
2095 * Tx parsing BD structure for ETH E2
2097 struct eth_tx_parse_bd_e2 {
2098 __le16 dst_mac_addr_lo;
2099 __le16 dst_mac_addr_mid;
2100 __le16 dst_mac_addr_hi;
2101 __le16 src_mac_addr_lo;
2102 __le16 src_mac_addr_mid;
2103 __le16 src_mac_addr_hi;
2104 __le32 parsing_data;
2105 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
2106 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
2107 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
2108 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
2109 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
2110 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
2111 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
2112 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
2116 * The last BD in the BD memory will hold a pointer to the next BD memory
2118 struct eth_tx_next_bd {
2125 * union for 4 Bd types
2127 union eth_tx_bd_types {
2128 struct eth_tx_start_bd start_bd;
2129 struct eth_tx_bd reg_bd;
2130 struct eth_tx_parse_bd_e1x parse_bd_e1x;
2131 struct eth_tx_parse_bd_e2 parse_bd_e2;
2132 struct eth_tx_next_bd next_bd;
2137 * The eth storm context of Xstorm
2139 struct xstorm_eth_st_context {
2144 * The eth storm context of Cstorm
2146 struct cstorm_eth_st_context {
2151 * Ethernet connection context
2153 struct eth_context {
2154 struct ustorm_eth_st_context ustorm_st_context;
2155 struct tstorm_eth_st_context tstorm_st_context;
2156 struct xstorm_eth_ag_context xstorm_ag_context;
2157 struct tstorm_eth_ag_context tstorm_ag_context;
2158 struct cstorm_eth_ag_context cstorm_ag_context;
2159 struct ustorm_eth_ag_context ustorm_ag_context;
2160 struct timers_block_context timers_context;
2161 struct xstorm_eth_st_context xstorm_st_context;
2162 struct cstorm_eth_st_context cstorm_st_context;
2169 struct eth_tx_doorbell {
2170 #if defined(__BIG_ENDIAN)
2173 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2174 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2175 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2176 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2177 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2178 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2179 struct doorbell_hdr hdr;
2180 #elif defined(__LITTLE_ENDIAN)
2181 struct doorbell_hdr hdr;
2183 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2184 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2185 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2186 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2187 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2188 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2195 * client init fc data
2197 struct client_init_fc_data {
2198 __le16 cqe_pause_thr_low;
2199 __le16 cqe_pause_thr_high;
2200 __le16 bd_pause_thr_low;
2201 __le16 bd_pause_thr_high;
2202 __le16 sge_pause_thr_low;
2203 __le16 sge_pause_thr_high;
2206 u8 safc_group_en_flg;
2215 * client init ramrod data
2217 struct client_init_general_data {
2219 u8 statistics_counter_id;
2220 u8 statistics_en_flg;
2225 __le32 reserved1[2];
2230 * client init rx data
2232 struct client_init_rx_data {
2234 u8 vmqueue_mode_en_flg;
2235 u8 extra_data_over_sgl_en_flg;
2236 u8 cache_line_alignment_log_size;
2237 u8 enable_dynamic_hc;
2238 u8 max_sges_for_packet;
2240 u8 drop_ip_cs_err_flg;
2241 u8 drop_tcp_cs_err_flg;
2243 u8 drop_udp_cs_err_flg;
2244 u8 inner_vlan_removal_enable_flg;
2245 u8 outer_vlan_removal_enable_flg;
2247 u8 rx_sb_index_number;
2249 __le16 bd_buff_size;
2250 __le16 sge_buff_size;
2252 struct regpair bd_page_base;
2253 struct regpair sge_page_base;
2254 struct regpair cqe_page_base;
2257 __le16 max_agg_size;
2258 __le32 reserved2[3];
2262 * client init tx data
2264 struct client_init_tx_data {
2265 u8 enforce_security_flg;
2266 u8 tx_status_block_id;
2267 u8 tx_sb_index_number;
2271 struct regpair tx_bd_page_base;
2272 __le32 reserved2[2];
2276 * client init ramrod data
2278 struct client_init_ramrod_data {
2279 struct client_init_general_data general;
2280 struct client_init_rx_data rx;
2281 struct client_init_tx_data tx;
2282 struct client_init_fc_data fc;
2287 * The data contain client ID need to the ramrod
2289 struct eth_common_ramrod_data {
2296 * union for sgl and raw data.
2298 union eth_sgl_or_raw_data {
2304 * regular eth FP CQE parameters struct
2306 struct eth_fast_path_rx_cqe {
2307 u8 type_error_flags;
2308 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2309 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2310 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2311 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2312 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2313 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2314 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2315 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2316 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2317 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2318 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2319 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2320 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x3<<6)
2321 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 6
2323 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2324 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2325 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2326 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2327 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2328 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2329 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2330 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2331 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2332 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2333 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2334 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2335 u8 placement_offset;
2337 __le32 rss_hash_result;
2341 struct parsing_flags pars_flags;
2342 union eth_sgl_or_raw_data sgl_or_raw_data;
2347 * The data for RSS setup ramrod
2349 struct eth_halt_ramrod_data {
2355 * The data for statistics query ramrod
2357 struct common_query_ramrod_data {
2358 #if defined(__BIG_ENDIAN)
2362 #elif defined(__LITTLE_ENDIAN)
2372 * Place holder for ramrods protocol specific data
2374 struct ramrod_data {
2380 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2382 union eth_ramrod_data {
2383 struct ramrod_data general;
2388 * Eth Rx Cqe structure- general structure for ramrods
2390 struct common_ramrod_eth_rx_cqe {
2392 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2393 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2394 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<1)
2395 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1
2396 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F<<2)
2397 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2
2400 __le32 conn_and_cmd_data;
2401 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2402 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2403 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2404 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2405 struct ramrod_data protocol_data;
2406 __le32 reserved2[4];
2410 * Rx Last CQE in page (in ETH)
2412 struct eth_rx_cqe_next_page {
2419 * union for all eth rx cqe types (fix their sizes)
2422 struct eth_fast_path_rx_cqe fast_path_cqe;
2423 struct common_ramrod_eth_rx_cqe ramrod_cqe;
2424 struct eth_rx_cqe_next_page next_page_cqe;
2429 * common data for all protocols
2432 __le32 conn_and_cmd_data;
2433 #define SPE_HDR_CID (0xFFFFFF<<0)
2434 #define SPE_HDR_CID_SHIFT 0
2435 #define SPE_HDR_CMD_ID (0xFF<<24)
2436 #define SPE_HDR_CMD_ID_SHIFT 24
2438 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2439 #define SPE_HDR_CONN_TYPE_SHIFT 0
2440 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
2441 #define SPE_HDR_FUNCTION_ID_SHIFT 8
2446 * Ethernet slow path element
2448 union eth_specific_data {
2449 u8 protocol_data[8];
2450 struct regpair client_init_ramrod_init_data;
2451 struct eth_halt_ramrod_data halt_ramrod_data;
2452 struct regpair update_data_addr;
2453 struct eth_common_ramrod_data common_ramrod_data;
2457 * Ethernet slow path element
2461 union eth_specific_data data;
2466 * array of 13 bds as appears in the eth xstorm context
2468 struct eth_tx_bds_array {
2469 union eth_tx_bd_types bds[13];
2474 * Common configuration parameters per function in Tstorm
2476 struct tstorm_eth_function_common_config {
2477 #if defined(__BIG_ENDIAN)
2481 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2482 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2483 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2484 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2485 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2486 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2487 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2488 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2489 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2490 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2491 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2492 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2493 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2494 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2495 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2496 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2497 #elif defined(__LITTLE_ENDIAN)
2499 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2500 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2501 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2502 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2503 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2504 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2505 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2506 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2507 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2508 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2509 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2510 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2511 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2512 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2513 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2514 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2522 * RSS idirection table update configuration
2524 struct rss_update_config {
2525 #if defined(__BIG_ENDIAN)
2528 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2529 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2530 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2531 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2532 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2533 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2534 #elif defined(__LITTLE_ENDIAN)
2536 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2537 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2538 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2539 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2540 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2541 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2548 * parameters for eth update ramrod
2550 struct eth_update_ramrod_data {
2551 struct tstorm_eth_function_common_config func_config;
2552 u8 indirectionTable[128];
2553 struct rss_update_config rss_config;
2558 * MAC filtering configuration command header
2560 struct mac_configuration_hdr {
2569 * MAC address in list for ramrod
2571 struct mac_configuration_entry {
2572 __le16 lsb_mac_addr;
2573 __le16 middle_mac_addr;
2574 __le16 msb_mac_addr;
2578 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
2579 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
2580 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
2581 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
2582 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
2583 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
2584 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
2585 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
2586 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
2587 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
2588 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
2589 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
2591 u32 clients_bit_vector;
2595 * MAC filtering configuration command
2597 struct mac_configuration_cmd {
2598 struct mac_configuration_hdr hdr;
2599 struct mac_configuration_entry config_table[64];
2604 * approximate-match multicast filtering for E1H per function in Tstorm
2606 struct tstorm_eth_approximate_match_multicast_filtering {
2607 u32 mcast_add_hash_bit_array[8];
2612 * MAC filtering configuration parameters per port in Tstorm
2614 struct tstorm_eth_mac_filter_config {
2616 u32 ucast_accept_all;
2618 u32 mcast_accept_all;
2620 u32 bcast_accept_all;
2622 u32 unmatched_unicast;
2628 * common flag to indicate existance of TPA.
2630 struct tstorm_eth_tpa_exist {
2631 #if defined(__BIG_ENDIAN)
2635 #elif defined(__LITTLE_ENDIAN)
2645 * Three RX producers for ETH
2647 struct ustorm_eth_rx_producers {
2648 #if defined(__BIG_ENDIAN)
2651 #elif defined(__LITTLE_ENDIAN)
2655 #if defined(__BIG_ENDIAN)
2658 #elif defined(__LITTLE_ENDIAN)
2666 * cfc delete event data
2668 struct cfc_del_event_data {
2678 * per-port SAFC demo variables
2680 struct cmng_flags_per_port {
2681 u8 con_number[NUM_OF_PROTOCOLS];
2683 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2684 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2685 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2686 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2687 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2688 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2689 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2690 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2691 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2692 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2693 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<5)
2694 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 5
2695 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x3FFFFFF<<6)
2696 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 6
2701 * per-port rate shaping variables
2703 struct rate_shaping_vars_per_port {
2704 u32 rs_periodic_timeout;
2709 * per-port fairness variables
2711 struct fairness_vars_per_port {
2714 u32 fairness_timeout;
2718 * per-port SAFC variables
2720 struct safc_struct_per_port {
2721 #if defined(__BIG_ENDIAN)
2724 u8 safc_timeout_usec;
2725 #elif defined(__LITTLE_ENDIAN)
2726 u8 safc_timeout_usec;
2730 u8 cos_to_traffic_types[MAX_COS_NUMBER];
2732 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
2736 * per-port PFC variables
2738 struct pfc_struct_per_port {
2739 u8 priority_to_traffic_types[MAX_PFC_PRIORITIES];
2740 #if defined(__BIG_ENDIAN)
2741 u16 pfc_pause_quanta_in_nanosec;
2743 u8 priority_non_pausable_mask;
2744 #elif defined(__LITTLE_ENDIAN)
2745 u8 priority_non_pausable_mask;
2747 u16 pfc_pause_quanta_in_nanosec;
2754 struct priority_cos {
2755 #if defined(__BIG_ENDIAN)
2759 #elif defined(__LITTLE_ENDIAN)
2768 * Per-port congestion management variables
2770 struct cmng_struct_per_port {
2771 struct rate_shaping_vars_per_port rs_vars;
2772 struct fairness_vars_per_port fair_vars;
2773 struct safc_struct_per_port safc_vars;
2774 struct pfc_struct_per_port pfc_vars;
2775 #if defined(__BIG_ENDIAN)
2779 #elif defined(__LITTLE_ENDIAN)
2785 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
2786 struct cmng_flags_per_port flags;
2792 * Dynamic HC counters set by the driver
2794 struct hc_dynamic_drv_counter {
2795 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
2799 * zone A per-queue data
2801 struct cstorm_queue_zone_data {
2802 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
2803 struct regpair reserved[2];
2807 * Dynamic host coalescing init parameters
2809 struct dynamic_hc_config {
2811 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
2812 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
2813 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
2814 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
2815 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
2820 * Protocol-common statistics collected by the Xstorm (per client)
2822 struct xstorm_per_client_stats {
2824 __le32 unicast_pkts_sent;
2825 struct regpair unicast_bytes_sent;
2826 struct regpair multicast_bytes_sent;
2827 __le32 multicast_pkts_sent;
2828 __le32 broadcast_pkts_sent;
2829 struct regpair broadcast_bytes_sent;
2830 __le16 stats_counter;
2836 * Common statistics collected by the Xstorm (per port)
2838 struct xstorm_common_stats {
2839 struct xstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
2843 * Protocol-common statistics collected by the Tstorm (per port)
2845 struct tstorm_per_port_stats {
2846 __le32 mac_filter_discard;
2847 __le32 xxoverflow_discard;
2848 __le32 brb_truncate_discard;
2853 * Protocol-common statistics collected by the Tstorm (per client)
2855 struct tstorm_per_client_stats {
2856 struct regpair rcv_unicast_bytes;
2857 struct regpair rcv_broadcast_bytes;
2858 struct regpair rcv_multicast_bytes;
2859 struct regpair rcv_error_bytes;
2860 __le32 checksum_discard;
2861 __le32 packets_too_big_discard;
2862 __le32 rcv_unicast_pkts;
2863 __le32 rcv_broadcast_pkts;
2864 __le32 rcv_multicast_pkts;
2865 __le32 no_buff_discard;
2866 __le32 ttl0_discard;
2867 __le16 stats_counter;
2872 * Protocol-common statistics collected by the Tstorm
2874 struct tstorm_common_stats {
2875 struct tstorm_per_port_stats port_statistics;
2876 struct tstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
2880 * Protocol-common statistics collected by the Ustorm (per client)
2882 struct ustorm_per_client_stats {
2883 struct regpair ucast_no_buff_bytes;
2884 struct regpair mcast_no_buff_bytes;
2885 struct regpair bcast_no_buff_bytes;
2886 __le32 ucast_no_buff_pkts;
2887 __le32 mcast_no_buff_pkts;
2888 __le32 bcast_no_buff_pkts;
2889 __le16 stats_counter;
2894 * Protocol-common statistics collected by the Ustorm
2896 struct ustorm_common_stats {
2897 struct ustorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
2901 * Eth statistics query structure for the eth_stats_query ramrod
2903 struct eth_stats_query {
2904 struct xstorm_common_stats xstorm_common;
2905 struct tstorm_common_stats tstorm_common;
2906 struct ustorm_common_stats ustorm_common;
2911 * set mac event data
2913 struct set_mac_event_data {
2921 * union for all event ring message types
2924 struct set_mac_event_data set_mac_event;
2925 struct cfc_del_event_data cfc_del_event;
2930 * per PF event ring data
2932 struct event_ring_data {
2933 struct regpair base_addr;
2934 #if defined(__BIG_ENDIAN)
2938 #elif defined(__LITTLE_ENDIAN)
2948 * event ring message element (each element is 128 bits)
2950 struct event_ring_msg {
2954 union event_data data;
2958 * event ring next page element (128 bits)
2960 struct event_ring_next {
2961 struct regpair addr;
2966 * union for event ring element types (each element is 128 bits)
2968 union event_ring_elem {
2969 struct event_ring_msg message;
2970 struct event_ring_next next_page;
2975 * per-vnic fairness variables
2977 struct fairness_vars_per_vn {
2978 u32 cos_credit_delta[MAX_COS_NUMBER];
2979 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2980 u32 vn_credit_delta;
2986 * FW version stored in the Xstorm RAM
2989 #if defined(__BIG_ENDIAN)
2994 #elif defined(__LITTLE_ENDIAN)
3001 #define FW_VERSION_OPTIMIZED (0x1<<0)
3002 #define FW_VERSION_OPTIMIZED_SHIFT 0
3003 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
3004 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
3005 #define FW_VERSION_CHIP_VERSION (0x3<<2)
3006 #define FW_VERSION_CHIP_VERSION_SHIFT 2
3007 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
3008 #define __FW_VERSION_RESERVED_SHIFT 4
3013 * Dynamic Host-Coalescing - Driver(host) counters
3015 struct hc_dynamic_sb_drv_counters {
3016 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
3021 * 2 bytes. configuration/state parameters for a single protocol index
3023 struct hc_index_data {
3024 #if defined(__BIG_ENDIAN)
3026 #define HC_INDEX_DATA_SM_ID (0x1<<0)
3027 #define HC_INDEX_DATA_SM_ID_SHIFT 0
3028 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3029 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3030 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3031 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3032 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
3033 #define HC_INDEX_DATA_RESERVE_SHIFT 3
3035 #elif defined(__LITTLE_ENDIAN)
3038 #define HC_INDEX_DATA_SM_ID (0x1<<0)
3039 #define HC_INDEX_DATA_SM_ID_SHIFT 0
3040 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3041 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3042 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3043 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3044 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
3045 #define HC_INDEX_DATA_RESERVE_SHIFT 3
3053 struct hc_status_block_sm {
3054 #if defined(__BIG_ENDIAN)
3059 #elif defined(__LITTLE_ENDIAN)
3069 * hold PCI identification variables- used in various places in firmware
3072 #if defined(__BIG_ENDIAN)
3077 #elif defined(__LITTLE_ENDIAN)
3086 * The fast-path status block meta-data, common to all chips
3089 struct regpair host_sb_addr;
3090 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
3091 struct pci_entity p_func;
3092 #if defined(__BIG_ENDIAN)
3095 u8 __dynamic_hc_level;
3097 #elif defined(__LITTLE_ENDIAN)
3099 u8 __dynamic_hc_level;
3103 struct regpair rsrv1[2];
3108 * The fast-path status block meta-data
3110 struct hc_sp_status_block_data {
3111 struct regpair host_sb_addr;
3112 #if defined(__BIG_ENDIAN)
3116 #elif defined(__LITTLE_ENDIAN)
3121 struct pci_entity p_func;
3126 * The fast-path status block meta-data
3128 struct hc_status_block_data_e1x {
3129 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
3130 struct hc_sb_data common;
3135 * The fast-path status block meta-data
3137 struct hc_status_block_data_e2 {
3138 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
3139 struct hc_sb_data common;
3144 * FW version stored in first line of pram
3146 struct pram_fw_version {
3152 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
3153 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
3154 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
3155 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
3156 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
3157 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
3158 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
3159 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
3160 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
3161 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
3166 * Ethernet slow path element
3168 union protocol_common_specific_data {
3169 u8 protocol_data[8];
3170 struct regpair phy_address;
3171 struct regpair mac_config_addr;
3172 struct common_query_ramrod_data query_ramrod_data;
3176 * The send queue element
3178 struct protocol_common_spe {
3180 union protocol_common_specific_data data;
3185 * a single rate shaping counter. can be used as protocol or vnic counter
3187 struct rate_shaping_counter {
3189 #if defined(__BIG_ENDIAN)
3192 #elif defined(__LITTLE_ENDIAN)
3200 * per-vnic rate shaping variables
3202 struct rate_shaping_vars_per_vn {
3203 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
3204 struct rate_shaping_counter vn_counter;
3209 * The send queue element
3211 struct slow_path_element {
3213 struct regpair protocol_data;
3218 * eth/toe flags that indicate if to query
3220 struct stats_indication_flags {
3227 * per-port PFC variables
3229 struct storm_pfc_struct_per_port {
3230 #if defined(__BIG_ENDIAN)
3233 #elif defined(__LITTLE_ENDIAN)
3237 #if defined(__BIG_ENDIAN)
3238 u16 pfc_pause_quanta_in_nanosec;
3240 #elif defined(__LITTLE_ENDIAN)
3242 u16 pfc_pause_quanta_in_nanosec;
3247 * Per-port congestion management variables
3249 struct storm_cmng_struct_per_port {
3250 struct storm_pfc_struct_per_port pfc_vars;
3255 * zone A per-queue data
3257 struct tstorm_queue_zone_data {
3258 struct regpair reserved[4];
3263 * zone B per-VF data
3265 struct tstorm_vf_zone_data {
3266 struct regpair reserved;
3271 * zone A per-queue data
3273 struct ustorm_queue_zone_data {
3274 struct ustorm_eth_rx_producers eth_rx_producers;
3275 struct regpair reserved[3];
3280 * zone B per-VF data
3282 struct ustorm_vf_zone_data {
3283 struct regpair reserved;
3288 * data per VF-PF channel
3290 struct vf_pf_channel_data {
3291 #if defined(__BIG_ENDIAN)
3295 #elif defined(__LITTLE_ENDIAN)
3305 * zone A per-queue data
3307 struct xstorm_queue_zone_data {
3308 struct regpair reserved[4];
3313 * zone B per-VF data
3315 struct xstorm_vf_zone_data {
3316 struct regpair reserved;
3319 #endif /* BNX2X_HSI_H */