1 /* Freescale Enhanced Local Bus Controller NAND driver
3 * Copyright (c) 2006-2007 Freescale Semiconductor
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/ioport.h>
29 #include <linux/of_platform.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/nand.h>
35 #include <linux/mtd/nand_ecc.h>
36 #include <linux/mtd/partitions.h>
39 #include <asm/fsl_lbc.h>
42 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
43 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
47 /* mtd information per set */
51 struct nand_chip chip;
52 struct fsl_elbc_ctrl *ctrl;
55 int bank; /* Chip select bank number */
56 u8 __iomem *vbase; /* Chip select base virtual address */
57 int page_size; /* NAND page size (0=512, 1=2048) */
58 unsigned int fmr; /* FCM Flash Mode Register value */
61 /* overview of the fsl elbc controller */
63 struct fsl_elbc_ctrl {
64 struct nand_hw_control controller;
65 struct fsl_elbc_mtd *chips[MAX_BANKS];
69 struct fsl_lbc_regs __iomem *regs;
71 wait_queue_head_t irq_wait;
72 unsigned int irq_status; /* status read from LTESR by irq handler */
73 u8 __iomem *addr; /* Address of assigned FCM buffer */
74 unsigned int page; /* Last page written to / read from */
75 unsigned int read_bytes; /* Number of bytes read during command */
76 unsigned int column; /* Saved column from SEQIN */
77 unsigned int index; /* Pointer to next byte to 'read' */
78 unsigned int status; /* status read from LTESR after last op */
79 unsigned int mdr; /* UPM/FCM Data Register value */
80 unsigned int use_mdr; /* Non zero if the MDR is to be set */
81 unsigned int oob; /* Non zero if operating on OOB data */
82 char *oob_poi; /* Place to write ECC after read back */
85 /* These map to the positions used by the FCM hardware ECC generator */
87 /* Small Page FLASH with FMR[ECCM] = 0 */
88 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
91 .oobfree = { {0, 5}, {9, 7} },
95 /* Small Page FLASH with FMR[ECCM] = 1 */
96 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
99 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
103 /* Large Page FLASH with FMR[ECCM] = 0 */
104 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
106 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
107 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
111 /* Large Page FLASH with FMR[ECCM] = 1 */
112 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
114 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
115 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
120 * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
121 * 1, so we have to adjust bad block pattern. This pattern should be used for
122 * x8 chips only. So far hardware does not support x16 chips anyway.
124 static u8 scan_ff_pattern[] = { 0xff, };
126 static struct nand_bbt_descr largepage_memorybased = {
130 .pattern = scan_ff_pattern,
134 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
135 * interfere with ECC positions, that's why we implement our own descriptors.
136 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
138 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
139 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
141 static struct nand_bbt_descr bbt_main_descr = {
142 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
143 NAND_BBT_2BIT | NAND_BBT_VERSION,
148 .pattern = bbt_pattern,
151 static struct nand_bbt_descr bbt_mirror_descr = {
152 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
153 NAND_BBT_2BIT | NAND_BBT_VERSION,
158 .pattern = mirror_pattern,
161 /*=================================*/
164 * Set up the FCM hardware block and page address fields, and the fcm
165 * structure addr field to point to the correct FCM buffer in memory
167 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
169 struct nand_chip *chip = mtd->priv;
170 struct fsl_elbc_mtd *priv = chip->priv;
171 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
172 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
175 ctrl->page = page_addr;
178 page_addr >> (chip->phys_erase_shift - chip->page_shift));
180 if (priv->page_size) {
182 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
183 (oob ? FPAR_LP_MS : 0) | column);
184 buf_num = (page_addr & 1) << 2;
187 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
188 (oob ? FPAR_SP_MS : 0) | column);
189 buf_num = page_addr & 7;
192 ctrl->addr = priv->vbase + buf_num * 1024;
193 ctrl->index = column;
195 /* for OOB data point to the second half of the buffer */
197 ctrl->index += priv->page_size ? 2048 : 512;
199 dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
200 "index %x, pes %d ps %d\n",
201 buf_num, ctrl->addr, priv->vbase, ctrl->index,
202 chip->phys_erase_shift, chip->page_shift);
206 * execute FCM command and wait for it to complete
208 static int fsl_elbc_run_command(struct mtd_info *mtd)
210 struct nand_chip *chip = mtd->priv;
211 struct fsl_elbc_mtd *priv = chip->priv;
212 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
213 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
215 /* Setup the FMR[OP] to execute without write protection */
216 out_be32(&lbc->fmr, priv->fmr | 3);
218 out_be32(&lbc->mdr, ctrl->mdr);
221 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
222 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
224 "fsl_elbc_run_command: fbar=%08x fpar=%08x "
225 "fbcr=%08x bank=%d\n",
226 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
227 in_be32(&lbc->fbcr), priv->bank);
229 ctrl->irq_status = 0;
230 /* execute special operation */
231 out_be32(&lbc->lsor, priv->bank);
233 /* wait for FCM complete flag or timeout */
234 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
235 FCM_TIMEOUT_MSECS * HZ/1000);
236 ctrl->status = ctrl->irq_status;
238 /* store mdr value in case it was needed */
240 ctrl->mdr = in_be32(&lbc->mdr);
245 "fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
246 ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
248 /* returns 0 on success otherwise non-zero) */
249 return ctrl->status == LTESR_CC ? 0 : -EIO;
252 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
254 struct fsl_elbc_mtd *priv = chip->priv;
255 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
256 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
258 if (priv->page_size) {
260 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
261 (FIR_OP_CA << FIR_OP1_SHIFT) |
262 (FIR_OP_PA << FIR_OP2_SHIFT) |
263 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
264 (FIR_OP_RBW << FIR_OP4_SHIFT));
266 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
267 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
270 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
271 (FIR_OP_CA << FIR_OP1_SHIFT) |
272 (FIR_OP_PA << FIR_OP2_SHIFT) |
273 (FIR_OP_RBW << FIR_OP3_SHIFT));
276 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
278 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
282 /* cmdfunc send commands to the FCM */
283 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
284 int column, int page_addr)
286 struct nand_chip *chip = mtd->priv;
287 struct fsl_elbc_mtd *priv = chip->priv;
288 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
289 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
293 /* clear the read buffer */
294 ctrl->read_bytes = 0;
295 if (command != NAND_CMD_PAGEPROG)
299 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
306 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
307 " 0x%x, column: 0x%x.\n", page_addr, column);
310 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
311 set_addr(mtd, 0, page_addr, 0);
313 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
314 ctrl->index += column;
316 fsl_elbc_do_read(chip, 0);
317 fsl_elbc_run_command(mtd);
320 /* READOOB reads only the OOB because no ECC is performed. */
321 case NAND_CMD_READOOB:
323 "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
324 " 0x%x, column: 0x%x.\n", page_addr, column);
326 out_be32(&lbc->fbcr, mtd->oobsize - column);
327 set_addr(mtd, column, page_addr, 1);
329 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
331 fsl_elbc_do_read(chip, 1);
332 fsl_elbc_run_command(mtd);
335 /* READID must read all 5 possible bytes while CEB is active */
336 case NAND_CMD_READID:
337 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
339 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
340 (FIR_OP_UA << FIR_OP1_SHIFT) |
341 (FIR_OP_RBW << FIR_OP2_SHIFT));
342 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
343 /* 5 bytes for manuf, device and exts */
344 out_be32(&lbc->fbcr, 5);
345 ctrl->read_bytes = 5;
349 set_addr(mtd, 0, 0, 0);
350 fsl_elbc_run_command(mtd);
353 /* ERASE1 stores the block and page address */
354 case NAND_CMD_ERASE1:
356 "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
357 "page_addr: 0x%x.\n", page_addr);
358 set_addr(mtd, 0, page_addr, 0);
361 /* ERASE2 uses the block and page address from ERASE1 */
362 case NAND_CMD_ERASE2:
363 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
366 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
367 (FIR_OP_PA << FIR_OP1_SHIFT) |
368 (FIR_OP_CM1 << FIR_OP2_SHIFT));
371 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
372 (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
374 out_be32(&lbc->fbcr, 0);
375 ctrl->read_bytes = 0;
377 fsl_elbc_run_command(mtd);
380 /* SEQIN sets up the addr buffer and all registers except the length */
381 case NAND_CMD_SEQIN: {
384 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
385 "page_addr: 0x%x, column: 0x%x.\n",
388 ctrl->column = column;
391 if (priv->page_size) {
392 fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
393 (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
396 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
397 (FIR_OP_CA << FIR_OP1_SHIFT) |
398 (FIR_OP_PA << FIR_OP2_SHIFT) |
399 (FIR_OP_WB << FIR_OP3_SHIFT) |
400 (FIR_OP_CW1 << FIR_OP4_SHIFT));
402 fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
403 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
406 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
407 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
408 (FIR_OP_CA << FIR_OP2_SHIFT) |
409 (FIR_OP_PA << FIR_OP3_SHIFT) |
410 (FIR_OP_WB << FIR_OP4_SHIFT) |
411 (FIR_OP_CW1 << FIR_OP5_SHIFT));
413 if (column >= mtd->writesize) {
414 /* OOB area --> READOOB */
415 column -= mtd->writesize;
416 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
418 } else if (column < 256) {
419 /* First 256 bytes --> READ0 */
420 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
422 /* Second 256 bytes --> READ1 */
423 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
427 out_be32(&lbc->fcr, fcr);
428 set_addr(mtd, column, page_addr, ctrl->oob);
432 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
433 case NAND_CMD_PAGEPROG: {
436 "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
437 "writing %d bytes.\n", ctrl->index);
439 /* if the write did not start at 0 or is not a full page
440 * then set the exact length, otherwise use a full page
441 * write so the HW generates the ECC.
443 if (ctrl->oob || ctrl->column != 0 ||
444 ctrl->index != mtd->writesize + mtd->oobsize) {
445 out_be32(&lbc->fbcr, ctrl->index);
448 out_be32(&lbc->fbcr, 0);
452 fsl_elbc_run_command(mtd);
454 /* Read back the page in order to fill in the ECC for the
455 * caller. Is this really needed?
457 if (full_page && ctrl->oob_poi) {
458 out_be32(&lbc->fbcr, 3);
459 set_addr(mtd, 6, page_addr, 1);
461 ctrl->read_bytes = mtd->writesize + 9;
463 fsl_elbc_do_read(chip, 1);
464 fsl_elbc_run_command(mtd);
466 memcpy_fromio(ctrl->oob_poi + 6,
467 &ctrl->addr[ctrl->index], 3);
471 ctrl->oob_poi = NULL;
475 /* CMD_STATUS must read the status byte while CEB is active */
476 /* Note - it does not wait for the ready line */
477 case NAND_CMD_STATUS:
479 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
480 (FIR_OP_RBW << FIR_OP1_SHIFT));
481 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
482 out_be32(&lbc->fbcr, 1);
483 set_addr(mtd, 0, 0, 0);
484 ctrl->read_bytes = 1;
486 fsl_elbc_run_command(mtd);
488 /* The chip always seems to report that it is
489 * write-protected, even when it is not.
491 setbits8(ctrl->addr, NAND_STATUS_WP);
494 /* RESET without waiting for the ready line */
496 dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
497 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
498 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
499 fsl_elbc_run_command(mtd);
504 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
509 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
511 /* The hardware does not seem to support multiple
517 * Write buf to the FCM Controller Data Buffer
519 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
521 struct nand_chip *chip = mtd->priv;
522 struct fsl_elbc_mtd *priv = chip->priv;
523 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
524 unsigned int bufsize = mtd->writesize + mtd->oobsize;
527 dev_err(ctrl->dev, "write_buf of %d bytes", len);
532 if ((unsigned int)len > bufsize - ctrl->index) {
534 "write_buf beyond end of buffer "
535 "(%d requested, %u available)\n",
536 len, bufsize - ctrl->index);
537 len = bufsize - ctrl->index;
540 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
542 * This is workaround for the weird elbc hangs during nand write,
543 * Scott Wood says: "...perhaps difference in how long it takes a
544 * write to make it through the localbus compared to a write to IMMR
545 * is causing problems, and sync isn't helping for some reason."
546 * Reading back the last byte helps though.
548 in_8(&ctrl->addr[ctrl->index] + len - 1);
554 * read a byte from either the FCM hardware buffer if it has any data left
555 * otherwise issue a command to read a single byte.
557 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
559 struct nand_chip *chip = mtd->priv;
560 struct fsl_elbc_mtd *priv = chip->priv;
561 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
563 /* If there are still bytes in the FCM, then use the next byte. */
564 if (ctrl->index < ctrl->read_bytes)
565 return in_8(&ctrl->addr[ctrl->index++]);
567 dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
572 * Read from the FCM Controller Data Buffer
574 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
576 struct nand_chip *chip = mtd->priv;
577 struct fsl_elbc_mtd *priv = chip->priv;
578 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
584 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
585 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
586 ctrl->index += avail;
590 "read_buf beyond end of buffer "
591 "(%d requested, %d available)\n",
596 * Verify buffer against the FCM Controller Data Buffer
598 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
600 struct nand_chip *chip = mtd->priv;
601 struct fsl_elbc_mtd *priv = chip->priv;
602 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
606 dev_err(ctrl->dev, "write_buf of %d bytes", len);
610 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
612 "verify_buf beyond end of buffer "
613 "(%d requested, %u available)\n",
614 len, ctrl->read_bytes - ctrl->index);
616 ctrl->index = ctrl->read_bytes;
620 for (i = 0; i < len; i++)
621 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
625 return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
628 /* This function is called after Program and Erase Operations to
629 * check for success or failure.
631 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
633 struct fsl_elbc_mtd *priv = chip->priv;
634 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
635 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
637 if (ctrl->status != LTESR_CC)
638 return NAND_STATUS_FAIL;
640 /* Use READ_STATUS command, but wait for the device to be ready */
643 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
644 (FIR_OP_RBW << FIR_OP1_SHIFT));
645 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
646 out_be32(&lbc->fbcr, 1);
647 set_addr(mtd, 0, 0, 0);
648 ctrl->read_bytes = 1;
650 fsl_elbc_run_command(mtd);
652 if (ctrl->status != LTESR_CC)
653 return NAND_STATUS_FAIL;
655 /* The chip always seems to report that it is
656 * write-protected, even when it is not.
658 setbits8(ctrl->addr, NAND_STATUS_WP);
659 return fsl_elbc_read_byte(mtd);
662 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
664 struct nand_chip *chip = mtd->priv;
665 struct fsl_elbc_mtd *priv = chip->priv;
666 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
667 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
670 /* calculate FMR Address Length field */
672 if (chip->pagemask & 0xffff0000)
674 if (chip->pagemask & 0xff000000)
677 /* add to ECCM mode set in fsl_elbc_init */
678 priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
679 (al << FMR_AL_SHIFT);
681 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
683 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %ld\n",
685 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
687 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
689 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
691 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
693 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
695 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
696 chip->phys_erase_shift);
697 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
699 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
701 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
703 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
705 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
707 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
709 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
710 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %d\n", mtd->size);
711 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
713 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
715 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
718 /* adjust Option Register and ECC to match Flash page size */
719 if (mtd->writesize == 512) {
721 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
722 } else if (mtd->writesize == 2048) {
724 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
725 /* adjust ecc setup if needed */
726 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
728 chip->ecc.size = 512;
729 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
730 &fsl_elbc_oob_lp_eccm1 :
731 &fsl_elbc_oob_lp_eccm0;
732 chip->badblock_pattern = &largepage_memorybased;
733 mtd->ecclayout = chip->ecc.layout;
734 mtd->oobavail = chip->ecc.layout->oobavail;
738 "fsl_elbc_init: page size %d is not supported\n",
746 static int fsl_elbc_read_page(struct mtd_info *mtd,
747 struct nand_chip *chip,
750 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
751 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
753 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
754 mtd->ecc_stats.failed++;
759 /* ECC will be calculated automatically, and errors will be detected in
762 static void fsl_elbc_write_page(struct mtd_info *mtd,
763 struct nand_chip *chip,
766 struct fsl_elbc_mtd *priv = chip->priv;
767 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
769 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
770 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
772 ctrl->oob_poi = chip->oob_poi;
775 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
777 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
778 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
779 struct nand_chip *chip = &priv->chip;
781 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
783 /* Fill in fsl_elbc_mtd structure */
784 priv->mtd.priv = chip;
785 priv->mtd.owner = THIS_MODULE;
786 priv->fmr = 0; /* rest filled in later */
788 /* fill in nand_chip structure */
789 /* set up function call table */
790 chip->read_byte = fsl_elbc_read_byte;
791 chip->write_buf = fsl_elbc_write_buf;
792 chip->read_buf = fsl_elbc_read_buf;
793 chip->verify_buf = fsl_elbc_verify_buf;
794 chip->select_chip = fsl_elbc_select_chip;
795 chip->cmdfunc = fsl_elbc_cmdfunc;
796 chip->waitfunc = fsl_elbc_wait;
798 chip->bbt_td = &bbt_main_descr;
799 chip->bbt_md = &bbt_mirror_descr;
801 /* set up nand options */
802 chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
805 chip->controller = &ctrl->controller;
808 chip->ecc.read_page = fsl_elbc_read_page;
809 chip->ecc.write_page = fsl_elbc_write_page;
811 /* If CS Base Register selects full hardware ECC then use it */
812 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
814 chip->ecc.mode = NAND_ECC_HW;
815 /* put in small page settings and adjust later if needed */
816 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
817 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
818 chip->ecc.size = 512;
821 /* otherwise fall back to default software ECC */
822 chip->ecc.mode = NAND_ECC_SOFT;
828 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
830 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
832 nand_release(&priv->mtd);
834 kfree(priv->mtd.name);
837 iounmap(priv->vbase);
839 ctrl->chips[priv->bank] = NULL;
845 static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
846 struct device_node *node)
848 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
849 struct fsl_elbc_mtd *priv;
851 #ifdef CONFIG_MTD_PARTITIONS
852 static const char *part_probe_types[]
853 = { "cmdlinepart", "RedBoot", NULL };
854 struct mtd_partition *parts;
859 /* get, allocate and map the memory resource */
860 ret = of_address_to_resource(node, 0, &res);
862 dev_err(ctrl->dev, "failed to get resource\n");
866 /* find which chip select it is connected to */
867 for (bank = 0; bank < MAX_BANKS; bank++)
868 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
869 (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
870 (in_be32(&lbc->bank[bank].br) &
871 in_be32(&lbc->bank[bank].or) & BR_BA)
875 if (bank >= MAX_BANKS) {
876 dev_err(ctrl->dev, "address did not match any chip selects\n");
880 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
884 ctrl->chips[bank] = priv;
887 priv->dev = ctrl->dev;
889 priv->vbase = ioremap(res.start, res.end - res.start + 1);
891 dev_err(ctrl->dev, "failed to map chip region\n");
896 priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", res.start);
897 if (!priv->mtd.name) {
902 ret = fsl_elbc_chip_init(priv);
906 ret = nand_scan_ident(&priv->mtd, 1);
910 ret = fsl_elbc_chip_init_tail(&priv->mtd);
914 ret = nand_scan_tail(&priv->mtd);
918 #ifdef CONFIG_MTD_PARTITIONS
919 /* First look for RedBoot table or partitions on the command
920 * line, these take precedence over device tree information */
921 ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
925 #ifdef CONFIG_MTD_OF_PARTS
927 ret = of_mtd_parse_partitions(priv->dev, &priv->mtd,
935 add_mtd_partitions(&priv->mtd, parts, ret);
938 add_mtd_device(&priv->mtd);
940 printk(KERN_INFO "eLBC NAND device at 0x%zx, bank %d\n",
941 res.start, priv->bank);
945 fsl_elbc_chip_remove(priv);
949 static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
951 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
953 /* clear event registers */
954 setbits32(&lbc->ltesr, LTESR_NAND_MASK);
955 out_be32(&lbc->lteatr, 0);
957 /* Enable interrupts for any detected events */
958 out_be32(&lbc->lteir, LTESR_NAND_MASK);
960 ctrl->read_bytes = 0;
967 static int fsl_elbc_ctrl_remove(struct of_device *ofdev)
969 struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
972 for (i = 0; i < MAX_BANKS; i++)
974 fsl_elbc_chip_remove(ctrl->chips[i]);
977 free_irq(ctrl->irq, ctrl);
982 dev_set_drvdata(&ofdev->dev, NULL);
987 /* NOTE: This interrupt is also used to report other localbus events,
988 * such as transaction errors on other chipselects. If we want to
989 * capture those, we'll need to move the IRQ code into a shared
993 static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
995 struct fsl_elbc_ctrl *ctrl = data;
996 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
997 __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
1000 out_be32(&lbc->ltesr, status);
1001 out_be32(&lbc->lteatr, 0);
1003 ctrl->irq_status = status;
1005 wake_up(&ctrl->irq_wait);
1013 /* fsl_elbc_ctrl_probe
1015 * called by device layer when it finds a device matching
1016 * one our driver can handled. This code allocates all of
1017 * the resources needed for the controller only. The
1018 * resources for the NAND banks themselves are allocated
1019 * in the chip probe function.
1022 static int __devinit fsl_elbc_ctrl_probe(struct of_device *ofdev,
1023 const struct of_device_id *match)
1025 struct device_node *child;
1026 struct fsl_elbc_ctrl *ctrl;
1029 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1033 dev_set_drvdata(&ofdev->dev, ctrl);
1035 spin_lock_init(&ctrl->controller.lock);
1036 init_waitqueue_head(&ctrl->controller.wq);
1037 init_waitqueue_head(&ctrl->irq_wait);
1039 ctrl->regs = of_iomap(ofdev->node, 0);
1041 dev_err(&ofdev->dev, "failed to get memory region\n");
1046 ctrl->irq = of_irq_to_resource(ofdev->node, 0, NULL);
1047 if (ctrl->irq == NO_IRQ) {
1048 dev_err(&ofdev->dev, "failed to get irq resource\n");
1053 ctrl->dev = &ofdev->dev;
1055 ret = fsl_elbc_ctrl_init(ctrl);
1059 ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
1061 dev_err(&ofdev->dev, "failed to install irq (%d)\n",
1067 for_each_child_of_node(ofdev->node, child)
1068 if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
1069 fsl_elbc_chip_probe(ctrl, child);
1074 fsl_elbc_ctrl_remove(ofdev);
1078 static const struct of_device_id fsl_elbc_match[] = {
1080 .compatible = "fsl,elbc",
1085 static struct of_platform_driver fsl_elbc_ctrl_driver = {
1089 .match_table = fsl_elbc_match,
1090 .probe = fsl_elbc_ctrl_probe,
1091 .remove = fsl_elbc_ctrl_remove,
1094 static int __init fsl_elbc_init(void)
1096 return of_register_platform_driver(&fsl_elbc_ctrl_driver);
1099 static void __exit fsl_elbc_exit(void)
1101 of_unregister_platform_driver(&fsl_elbc_ctrl_driver);
1104 module_init(fsl_elbc_init);
1105 module_exit(fsl_elbc_exit);
1107 MODULE_LICENSE("GPL");
1108 MODULE_AUTHOR("Freescale");
1109 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");