2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
32 #include <linux/semaphore.h>
34 #include <mach/hardware.h>
35 #include <mach/board.h>
39 /* OMAP HSMMC Host Controller Registers */
40 #define OMAP_HSMMC_SYSCONFIG 0x0010
41 #define OMAP_HSMMC_SYSSTATUS 0x0014
42 #define OMAP_HSMMC_CON 0x002C
43 #define OMAP_HSMMC_BLK 0x0104
44 #define OMAP_HSMMC_ARG 0x0108
45 #define OMAP_HSMMC_CMD 0x010C
46 #define OMAP_HSMMC_RSP10 0x0110
47 #define OMAP_HSMMC_RSP32 0x0114
48 #define OMAP_HSMMC_RSP54 0x0118
49 #define OMAP_HSMMC_RSP76 0x011C
50 #define OMAP_HSMMC_DATA 0x0120
51 #define OMAP_HSMMC_HCTL 0x0128
52 #define OMAP_HSMMC_SYSCTL 0x012C
53 #define OMAP_HSMMC_STAT 0x0130
54 #define OMAP_HSMMC_IE 0x0134
55 #define OMAP_HSMMC_ISE 0x0138
56 #define OMAP_HSMMC_CAPA 0x0140
58 #define VS18 (1 << 26)
59 #define VS30 (1 << 25)
60 #define SDVS18 (0x5 << 9)
61 #define SDVS30 (0x6 << 9)
62 #define SDVS33 (0x7 << 9)
63 #define SDVS_MASK 0x00000E00
64 #define SDVSCLR 0xFFFFF1FF
65 #define SDVSDET 0x00000400
72 #define CLKD_MASK 0x0000FFC0
74 #define DTO_MASK 0x000F0000
76 #define INT_EN_MASK 0x307F0033
77 #define BWR_ENABLE (1 << 4)
78 #define BRR_ENABLE (1 << 5)
79 #define INIT_STREAM (1 << 1)
80 #define DP_SELECT (1 << 21)
85 #define FOUR_BIT (1 << 1)
91 #define CMD_TIMEOUT (1 << 16)
92 #define DATA_TIMEOUT (1 << 20)
93 #define CMD_CRC (1 << 17)
94 #define DATA_CRC (1 << 21)
95 #define CARD_ERR (1 << 28)
96 #define STAT_CLEAR 0xFFFFFFFF
97 #define INIT_STREAM_CMD 0x00000000
98 #define DUAL_VOLT_OCR_BIT 7
100 #define SRD (1 << 26)
101 #define SOFTRESET (1 << 1)
102 #define RESETDONE (1 << 0)
105 * FIXME: Most likely all the data using these _DEVID defines should come
106 * from the platform_data, or implemented in controller and slot specific
109 #define OMAP_MMC1_DEVID 0
110 #define OMAP_MMC2_DEVID 1
111 #define OMAP_MMC3_DEVID 2
113 #define MMC_TIMEOUT_MS 20
114 #define OMAP_MMC_MASTER_CLOCK 96000000
115 #define DRIVER_NAME "mmci-omap-hs"
117 /* Timeouts for entering power saving states on inactivity, msec */
118 #define OMAP_MMC_DISABLED_TIMEOUT 100
119 #define OMAP_MMC_SLEEP_TIMEOUT 1000
120 #define OMAP_MMC_OFF_TIMEOUT 8000
123 * One controller can have multiple slots, like on some omap boards using
124 * omap.c controller driver. Luckily this is not currently done on any known
125 * omap_hsmmc.c device.
127 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
130 * MMC Host controller read/write API's
132 #define OMAP_HSMMC_READ(base, reg) \
133 __raw_readl((base) + OMAP_HSMMC_##reg)
135 #define OMAP_HSMMC_WRITE(base, reg, val) \
136 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
138 struct omap_hsmmc_host {
140 struct mmc_host *mmc;
141 struct mmc_request *mrq;
142 struct mmc_command *cmd;
143 struct mmc_data *data;
147 struct semaphore sem;
148 struct work_struct mmc_carddetect_work;
150 resource_size_t mapbase;
151 spinlock_t irq_lock; /* Prevent races with irq handler */
154 unsigned int dma_len;
155 unsigned int dma_sg_idx;
156 unsigned char bus_mode;
157 unsigned char power_mode;
163 int dma_line_tx, dma_line_rx;
173 struct omap_mmc_platform_data *pdata;
177 * Stop clock to the card
179 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
181 OMAP_HSMMC_WRITE(host->base, SYSCTL,
182 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
183 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
184 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
190 * Restore the MMC host context, if it was lost as result of a
191 * power state change.
193 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
195 struct mmc_ios *ios = &host->mmc->ios;
196 struct omap_mmc_platform_data *pdata = host->pdata;
197 int context_loss = 0;
200 unsigned long timeout;
202 if (pdata->get_context_loss_count) {
203 context_loss = pdata->get_context_loss_count(host->dev);
204 if (context_loss < 0)
208 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
209 context_loss == host->context_loss ? "not " : "");
210 if (host->context_loss == context_loss)
213 /* Wait for hardware reset */
214 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
215 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
216 && time_before(jiffies, timeout))
219 /* Do software reset */
220 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
221 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
222 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
223 && time_before(jiffies, timeout))
226 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
227 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
229 if (host->id == OMAP_MMC1_DEVID) {
230 if (host->power_mode != MMC_POWER_OFF &&
231 (1 << ios->vdd) <= MMC_VDD_23_24)
241 OMAP_HSMMC_WRITE(host->base, HCTL,
242 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
244 OMAP_HSMMC_WRITE(host->base, CAPA,
245 OMAP_HSMMC_READ(host->base, CAPA) | capa);
247 OMAP_HSMMC_WRITE(host->base, HCTL,
248 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
250 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
251 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
252 && time_before(jiffies, timeout))
255 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
256 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
257 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
259 /* Do not initialize card-specific things if the power is off */
260 if (host->power_mode == MMC_POWER_OFF)
263 con = OMAP_HSMMC_READ(host->base, CON);
264 switch (ios->bus_width) {
265 case MMC_BUS_WIDTH_8:
266 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
268 case MMC_BUS_WIDTH_4:
269 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
270 OMAP_HSMMC_WRITE(host->base, HCTL,
271 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
273 case MMC_BUS_WIDTH_1:
274 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
275 OMAP_HSMMC_WRITE(host->base, HCTL,
276 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
281 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
285 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
292 OMAP_HSMMC_WRITE(host->base, SYSCTL,
293 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
294 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
295 OMAP_HSMMC_WRITE(host->base, SYSCTL,
296 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
298 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
299 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
300 && time_before(jiffies, timeout))
303 OMAP_HSMMC_WRITE(host->base, SYSCTL,
304 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
306 con = OMAP_HSMMC_READ(host->base, CON);
307 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
308 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
310 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
312 host->context_loss = context_loss;
314 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
319 * Save the MMC host context (store the number of power state changes so far).
321 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
323 struct omap_mmc_platform_data *pdata = host->pdata;
326 if (pdata->get_context_loss_count) {
327 context_loss = pdata->get_context_loss_count(host->dev);
328 if (context_loss < 0)
330 host->context_loss = context_loss;
336 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
341 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
348 * Send init stream sequence to card
349 * before sending IDLE command
351 static void send_init_stream(struct omap_hsmmc_host *host)
354 unsigned long timeout;
356 if (host->protect_card)
359 disable_irq(host->irq);
360 OMAP_HSMMC_WRITE(host->base, CON,
361 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
362 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
364 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
365 while ((reg != CC) && time_before(jiffies, timeout))
366 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
368 OMAP_HSMMC_WRITE(host->base, CON,
369 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
371 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
372 OMAP_HSMMC_READ(host->base, STAT);
374 enable_irq(host->irq);
378 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
382 if (mmc_slot(host).get_cover_state)
383 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
388 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
391 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
392 struct omap_hsmmc_host *host = mmc_priv(mmc);
394 return sprintf(buf, "%s\n",
395 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
398 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
401 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
404 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
405 struct omap_hsmmc_host *host = mmc_priv(mmc);
407 return sprintf(buf, "%s\n", mmc_slot(host).name);
410 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
413 * Configure the response type and send the cmd.
416 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
417 struct mmc_data *data)
419 int cmdreg = 0, resptype = 0, cmdtype = 0;
421 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
422 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
426 * Clear status bits and enable interrupts
428 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
429 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
432 OMAP_HSMMC_WRITE(host->base, IE,
433 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
435 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
437 host->response_busy = 0;
438 if (cmd->flags & MMC_RSP_PRESENT) {
439 if (cmd->flags & MMC_RSP_136)
441 else if (cmd->flags & MMC_RSP_BUSY) {
443 host->response_busy = 1;
449 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
450 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
451 * a val of 0x3, rest 0x0.
453 if (cmd == host->mrq->stop)
456 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
459 cmdreg |= DP_SELECT | MSBS | BCE;
460 if (data->flags & MMC_DATA_READ)
470 * In an interrupt context (i.e. STOP command), the spinlock is unlocked
471 * by the interrupt handler, otherwise (i.e. for a new request) it is
475 spin_unlock_irqrestore(&host->irq_lock, host->flags);
477 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
478 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
482 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
484 if (data->flags & MMC_DATA_WRITE)
485 return DMA_TO_DEVICE;
487 return DMA_FROM_DEVICE;
491 * Notify the transfer complete to MMC core
494 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
497 struct mmc_request *mrq = host->mrq;
499 /* TC before CC from CMD6 - don't know why, but it happens */
500 if (host->cmd && host->cmd->opcode == 6 &&
501 host->response_busy) {
502 host->response_busy = 0;
507 mmc_request_done(host->mmc, mrq);
513 if (host->use_dma && host->dma_ch != -1)
514 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
515 omap_hsmmc_get_dma_dir(host, data));
518 data->bytes_xfered += data->blocks * (data->blksz);
520 data->bytes_xfered = 0;
524 mmc_request_done(host->mmc, data->mrq);
527 omap_hsmmc_start_command(host, data->stop, NULL);
531 * Notify the core about command completion
534 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
538 if (cmd->flags & MMC_RSP_PRESENT) {
539 if (cmd->flags & MMC_RSP_136) {
540 /* response type 2 */
541 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
542 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
543 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
544 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
546 /* response types 1, 1b, 3, 4, 5, 6 */
547 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
550 if ((host->data == NULL && !host->response_busy) || cmd->error) {
552 mmc_request_done(host->mmc, cmd->mrq);
557 * DMA clean up for command errors
559 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
561 host->data->error = errno;
563 if (host->use_dma && host->dma_ch != -1) {
564 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
565 omap_hsmmc_get_dma_dir(host, host->data));
566 omap_free_dma(host->dma_ch);
574 * Readable error output
576 #ifdef CONFIG_MMC_DEBUG
577 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
579 /* --- means reserved bit without definition at documentation */
580 static const char *omap_hsmmc_status_bits[] = {
581 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
582 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
583 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
584 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
590 len = sprintf(buf, "MMC IRQ 0x%x :", status);
593 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
594 if (status & (1 << i)) {
595 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
599 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
601 #endif /* CONFIG_MMC_DEBUG */
604 * MMC controller internal state machines reset
606 * Used to reset command or data internal state machines, using respectively
607 * SRC or SRD bit of SYSCTL register
608 * Can be called from interrupt context
610 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
614 unsigned long limit = (loops_per_jiffy *
615 msecs_to_jiffies(MMC_TIMEOUT_MS));
617 OMAP_HSMMC_WRITE(host->base, SYSCTL,
618 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
620 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
624 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
625 dev_err(mmc_dev(host->mmc),
626 "Timeout waiting on controller reset in %s\n",
631 * MMC controller IRQ handler
633 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
635 struct omap_hsmmc_host *host = dev_id;
636 struct mmc_data *data;
637 int end_cmd = 0, end_trans = 0, status;
639 spin_lock(&host->irq_lock);
641 if (host->mrq == NULL) {
642 OMAP_HSMMC_WRITE(host->base, STAT,
643 OMAP_HSMMC_READ(host->base, STAT));
644 /* Flush posted write */
645 OMAP_HSMMC_READ(host->base, STAT);
646 spin_unlock(&host->irq_lock);
651 status = OMAP_HSMMC_READ(host->base, STAT);
652 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
655 #ifdef CONFIG_MMC_DEBUG
656 omap_hsmmc_report_irq(host, status);
658 if ((status & CMD_TIMEOUT) ||
659 (status & CMD_CRC)) {
661 if (status & CMD_TIMEOUT) {
662 omap_hsmmc_reset_controller_fsm(host,
664 host->cmd->error = -ETIMEDOUT;
666 host->cmd->error = -EILSEQ;
670 if (host->data || host->response_busy) {
672 omap_hsmmc_dma_cleanup(host,
674 host->response_busy = 0;
675 omap_hsmmc_reset_controller_fsm(host, SRD);
678 if ((status & DATA_TIMEOUT) ||
679 (status & DATA_CRC)) {
680 if (host->data || host->response_busy) {
681 int err = (status & DATA_TIMEOUT) ?
682 -ETIMEDOUT : -EILSEQ;
685 omap_hsmmc_dma_cleanup(host, err);
687 host->mrq->cmd->error = err;
688 host->response_busy = 0;
689 omap_hsmmc_reset_controller_fsm(host, SRD);
693 if (status & CARD_ERR) {
694 dev_dbg(mmc_dev(host->mmc),
695 "Ignoring card err CMD%d\n", host->cmd->opcode);
703 OMAP_HSMMC_WRITE(host->base, STAT, status);
704 /* Flush posted write */
705 OMAP_HSMMC_READ(host->base, STAT);
707 if (end_cmd || ((status & CC) && host->cmd))
708 omap_hsmmc_cmd_done(host, host->cmd);
709 if ((end_trans || (status & TC)) && host->mrq)
710 omap_hsmmc_xfer_done(host, data);
712 spin_unlock(&host->irq_lock);
717 static void set_sd_bus_power(struct omap_hsmmc_host *host)
721 OMAP_HSMMC_WRITE(host->base, HCTL,
722 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
723 for (i = 0; i < loops_per_jiffy; i++) {
724 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
731 * Switch MMC interface voltage ... only relevant for MMC1.
733 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
734 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
735 * Some chips, like eMMC ones, use internal transceivers.
737 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
742 /* Disable the clocks */
743 clk_disable(host->fclk);
744 clk_disable(host->iclk);
745 clk_disable(host->dbclk);
747 /* Turn the power off */
748 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
752 /* Turn the power ON with given VDD 1.8 or 3.0v */
753 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
757 clk_enable(host->fclk);
758 clk_enable(host->iclk);
759 clk_enable(host->dbclk);
761 OMAP_HSMMC_WRITE(host->base, HCTL,
762 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
763 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
766 * If a MMC dual voltage card is detected, the set_ios fn calls
767 * this fn with VDD bit set for 1.8V. Upon card removal from the
768 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
770 * Cope with a bit of slop in the range ... per data sheets:
771 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
772 * but recommended values are 1.71V to 1.89V
773 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
774 * but recommended values are 2.7V to 3.3V
776 * Board setup code shouldn't permit anything very out-of-range.
777 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
778 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
780 if ((1 << vdd) <= MMC_VDD_23_24)
785 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
786 set_sd_bus_power(host);
790 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
794 /* Protect the card while the cover is open */
795 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
797 if (!mmc_slot(host).get_cover_state)
800 host->reqs_blocked = 0;
801 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
802 if (host->protect_card) {
803 printk(KERN_INFO "%s: cover is closed, "
804 "card is now accessible\n",
805 mmc_hostname(host->mmc));
806 host->protect_card = 0;
809 if (!host->protect_card) {
810 printk(KERN_INFO "%s: cover is open, "
811 "card is now inaccessible\n",
812 mmc_hostname(host->mmc));
813 host->protect_card = 1;
819 * Work Item to notify the core about card insertion/removal
821 static void omap_hsmmc_detect(struct work_struct *work)
823 struct omap_hsmmc_host *host =
824 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
825 struct omap_mmc_slot_data *slot = &mmc_slot(host);
831 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
833 if (slot->card_detect)
834 carddetect = slot->card_detect(slot->card_detect_irq);
836 omap_hsmmc_protect_card(host);
837 carddetect = -ENOSYS;
841 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
843 mmc_host_enable(host->mmc);
844 omap_hsmmc_reset_controller_fsm(host, SRD);
845 mmc_host_lazy_disable(host->mmc);
847 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
852 * ISR for handling card insertion and removal
854 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
856 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
860 schedule_work(&host->mmc_carddetect_work);
865 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
866 struct mmc_data *data)
870 if (data->flags & MMC_DATA_WRITE)
871 sync_dev = host->dma_line_tx;
873 sync_dev = host->dma_line_rx;
877 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
878 struct mmc_data *data,
879 struct scatterlist *sgl)
881 int blksz, nblk, dma_ch;
883 dma_ch = host->dma_ch;
884 if (data->flags & MMC_DATA_WRITE) {
885 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
886 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
887 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
888 sg_dma_address(sgl), 0, 0);
890 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
891 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
892 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
893 sg_dma_address(sgl), 0, 0);
896 blksz = host->data->blksz;
897 nblk = sg_dma_len(sgl) / blksz;
899 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
900 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
901 omap_hsmmc_get_dma_sync_dev(host, data),
902 !(data->flags & MMC_DATA_WRITE));
904 omap_start_dma(dma_ch);
908 * DMA call back function
910 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data)
912 struct omap_hsmmc_host *host = data;
914 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
915 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
917 if (host->dma_ch < 0)
921 if (host->dma_sg_idx < host->dma_len) {
922 /* Fire up the next transfer. */
923 omap_hsmmc_config_dma_params(host, host->data,
924 host->data->sg + host->dma_sg_idx);
928 omap_free_dma(host->dma_ch);
931 * DMA Callback: run in interrupt context.
932 * mutex_unlock will throw a kernel warning if used.
938 * Routine to configure and start DMA for the MMC card
940 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
941 struct mmc_request *req)
943 int dma_ch = 0, ret = 0, err = 1, i;
944 struct mmc_data *data = req->data;
946 /* Sanity check: all the SG entries must be aligned by block size. */
947 for (i = 0; i < data->sg_len; i++) {
948 struct scatterlist *sgl;
951 if (sgl->length % data->blksz)
954 if ((data->blksz % 4) != 0)
955 /* REVISIT: The MMC buffer increments only when MSB is written.
956 * Return error for blksz which is non multiple of four.
961 * If for some reason the DMA transfer is still active,
962 * we wait for timeout period and free the dma
964 if (host->dma_ch != -1) {
965 set_current_state(TASK_UNINTERRUPTIBLE);
966 schedule_timeout(100);
967 if (down_trylock(&host->sem)) {
968 omap_free_dma(host->dma_ch);
974 if (down_trylock(&host->sem))
978 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
979 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
981 dev_err(mmc_dev(host->mmc),
982 "%s: omap_request_dma() failed with %d\n",
983 mmc_hostname(host->mmc), ret);
987 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
988 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
989 host->dma_ch = dma_ch;
990 host->dma_sg_idx = 0;
992 omap_hsmmc_config_dma_params(host, data, data->sg);
997 static void set_data_timeout(struct omap_hsmmc_host *host,
998 struct mmc_request *req)
1000 unsigned int timeout, cycle_ns;
1001 uint32_t reg, clkd, dto = 0;
1003 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1004 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1008 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1009 timeout = req->data->timeout_ns / cycle_ns;
1010 timeout += req->data->timeout_clks;
1012 while ((timeout & 0x80000000) == 0) {
1029 reg |= dto << DTO_SHIFT;
1030 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1034 * Configure block length for MMC/SD cards and initiate the transfer.
1037 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1040 host->data = req->data;
1042 if (req->data == NULL) {
1043 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1047 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1048 | (req->data->blocks << 16));
1049 set_data_timeout(host, req);
1051 if (host->use_dma) {
1052 ret = omap_hsmmc_start_dma_transfer(host, req);
1054 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1062 * Request function. for read/write operation
1064 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1066 struct omap_hsmmc_host *host = mmc_priv(mmc);
1070 * Prevent races with the interrupt handler because of unexpected
1071 * interrupts, but not if we are already in interrupt context i.e.
1074 if (!in_interrupt()) {
1075 spin_lock_irqsave(&host->irq_lock, host->flags);
1077 * Protect the card from I/O if there is a possibility
1078 * it can be removed.
1080 if (host->protect_card) {
1081 if (host->reqs_blocked < 3) {
1083 * Ensure the controller is left in a consistent
1084 * state by resetting the command and data state
1087 omap_hsmmc_reset_controller_fsm(host, SRD);
1088 omap_hsmmc_reset_controller_fsm(host, SRC);
1089 host->reqs_blocked += 1;
1091 req->cmd->error = -EBADF;
1093 req->data->error = -EBADF;
1094 spin_unlock_irqrestore(&host->irq_lock, host->flags);
1095 mmc_request_done(mmc, req);
1097 } else if (host->reqs_blocked)
1098 host->reqs_blocked = 0;
1100 WARN_ON(host->mrq != NULL);
1102 err = omap_hsmmc_prepare_data(host, req);
1104 req->cmd->error = err;
1106 req->data->error = err;
1108 if (!in_interrupt())
1109 spin_unlock_irqrestore(&host->irq_lock, host->flags);
1110 mmc_request_done(mmc, req);
1114 omap_hsmmc_start_command(host, req->cmd, req->data);
1117 /* Routine to configure clock values. Exposed API to core */
1118 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1120 struct omap_hsmmc_host *host = mmc_priv(mmc);
1122 unsigned long regval;
1123 unsigned long timeout;
1125 int do_send_init_stream = 0;
1127 mmc_host_enable(host->mmc);
1129 if (ios->power_mode != host->power_mode) {
1130 switch (ios->power_mode) {
1132 mmc_slot(host).set_power(host->dev, host->slot_id,
1137 mmc_slot(host).set_power(host->dev, host->slot_id,
1139 host->vdd = ios->vdd;
1142 do_send_init_stream = 1;
1145 host->power_mode = ios->power_mode;
1148 /* FIXME: set registers based only on changes to ios */
1150 con = OMAP_HSMMC_READ(host->base, CON);
1151 switch (mmc->ios.bus_width) {
1152 case MMC_BUS_WIDTH_8:
1153 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1155 case MMC_BUS_WIDTH_4:
1156 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1157 OMAP_HSMMC_WRITE(host->base, HCTL,
1158 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1160 case MMC_BUS_WIDTH_1:
1161 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1162 OMAP_HSMMC_WRITE(host->base, HCTL,
1163 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1167 if (host->id == OMAP_MMC1_DEVID) {
1168 /* Only MMC1 can interface at 3V without some flavor
1169 * of external transceiver; but they all handle 1.8V.
1171 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1172 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1174 * The mmc_select_voltage fn of the core does
1175 * not seem to set the power_mode to
1176 * MMC_POWER_UP upon recalculating the voltage.
1179 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1180 dev_dbg(mmc_dev(host->mmc),
1181 "Switch operation failed\n");
1186 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1190 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1196 omap_hsmmc_stop_clock(host);
1197 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1198 regval = regval & ~(CLKD_MASK);
1199 regval = regval | (dsor << 6) | (DTO << 16);
1200 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1201 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1202 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1204 /* Wait till the ICS bit is set */
1205 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1206 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1207 && time_before(jiffies, timeout))
1210 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1211 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1213 if (do_send_init_stream)
1214 send_init_stream(host);
1216 con = OMAP_HSMMC_READ(host->base, CON);
1217 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1218 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1220 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1222 if (host->power_mode == MMC_POWER_OFF)
1223 mmc_host_disable(host->mmc);
1225 mmc_host_lazy_disable(host->mmc);
1228 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1230 struct omap_hsmmc_host *host = mmc_priv(mmc);
1232 if (!mmc_slot(host).card_detect)
1234 return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq);
1237 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1239 struct omap_hsmmc_host *host = mmc_priv(mmc);
1241 if (!mmc_slot(host).get_ro)
1243 return mmc_slot(host).get_ro(host->dev, 0);
1246 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1248 u32 hctl, capa, value;
1250 /* Only MMC1 supports 3.0V */
1251 if (host->id == OMAP_MMC1_DEVID) {
1259 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1260 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1262 value = OMAP_HSMMC_READ(host->base, CAPA);
1263 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1265 /* Set the controller to AUTO IDLE mode */
1266 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1267 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1269 /* Set SD bus power bit */
1270 set_sd_bus_power(host);
1274 * Dynamic power saving handling, FSM:
1275 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1277 * |______________________|______________________|
1279 * ENABLED: mmc host is fully functional
1280 * DISABLED: fclk is off
1281 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1282 * REGSLEEP: fclk is off, voltage regulator is asleep
1283 * OFF: fclk is off, voltage regulator is off
1285 * Transition handlers return the timeout for the next state transition
1286 * or negative error.
1289 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1291 /* Handler for [ENABLED -> DISABLED] transition */
1292 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1294 omap_hsmmc_context_save(host);
1295 clk_disable(host->fclk);
1296 host->dpm_state = DISABLED;
1298 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1300 if (host->power_mode == MMC_POWER_OFF)
1303 return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
1306 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1307 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1311 if (!mmc_try_claim_host(host->mmc))
1314 clk_enable(host->fclk);
1315 omap_hsmmc_context_restore(host);
1316 if (mmc_card_can_sleep(host->mmc)) {
1317 err = mmc_card_sleep(host->mmc);
1319 clk_disable(host->fclk);
1320 mmc_release_host(host->mmc);
1323 new_state = CARDSLEEP;
1325 new_state = REGSLEEP;
1327 if (mmc_slot(host).set_sleep)
1328 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1329 new_state == CARDSLEEP);
1330 /* FIXME: turn off bus power and perhaps interrupts too */
1331 clk_disable(host->fclk);
1332 host->dpm_state = new_state;
1334 mmc_release_host(host->mmc);
1336 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1337 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1339 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1340 mmc_slot(host).card_detect ||
1341 (mmc_slot(host).get_cover_state &&
1342 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1343 return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1348 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1349 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1351 if (!mmc_try_claim_host(host->mmc))
1354 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1355 mmc_slot(host).card_detect ||
1356 (mmc_slot(host).get_cover_state &&
1357 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1358 mmc_release_host(host->mmc);
1362 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1364 host->power_mode = MMC_POWER_OFF;
1366 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1367 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1369 host->dpm_state = OFF;
1371 mmc_release_host(host->mmc);
1376 /* Handler for [DISABLED -> ENABLED] transition */
1377 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1381 err = clk_enable(host->fclk);
1385 omap_hsmmc_context_restore(host);
1386 host->dpm_state = ENABLED;
1388 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1393 /* Handler for [SLEEP -> ENABLED] transition */
1394 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1396 if (!mmc_try_claim_host(host->mmc))
1399 clk_enable(host->fclk);
1400 omap_hsmmc_context_restore(host);
1401 if (mmc_slot(host).set_sleep)
1402 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1403 host->vdd, host->dpm_state == CARDSLEEP);
1404 if (mmc_card_can_sleep(host->mmc))
1405 mmc_card_awake(host->mmc);
1407 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1408 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1410 host->dpm_state = ENABLED;
1412 mmc_release_host(host->mmc);
1417 /* Handler for [OFF -> ENABLED] transition */
1418 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1420 clk_enable(host->fclk);
1422 omap_hsmmc_context_restore(host);
1423 omap_hsmmc_conf_bus_power(host);
1424 mmc_power_restore_host(host->mmc);
1426 host->dpm_state = ENABLED;
1428 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1434 * Bring MMC host to ENABLED from any other PM state.
1436 static int omap_hsmmc_enable(struct mmc_host *mmc)
1438 struct omap_hsmmc_host *host = mmc_priv(mmc);
1440 switch (host->dpm_state) {
1442 return omap_hsmmc_disabled_to_enabled(host);
1445 return omap_hsmmc_sleep_to_enabled(host);
1447 return omap_hsmmc_off_to_enabled(host);
1449 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1455 * Bring MMC host in PM state (one level deeper).
1457 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1459 struct omap_hsmmc_host *host = mmc_priv(mmc);
1461 switch (host->dpm_state) {
1465 delay = omap_hsmmc_enabled_to_disabled(host);
1466 if (lazy || delay < 0)
1471 return omap_hsmmc_disabled_to_sleep(host);
1474 return omap_hsmmc_sleep_to_off(host);
1476 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1481 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1483 struct omap_hsmmc_host *host = mmc_priv(mmc);
1486 err = clk_enable(host->fclk);
1489 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1490 omap_hsmmc_context_restore(host);
1494 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1496 struct omap_hsmmc_host *host = mmc_priv(mmc);
1498 omap_hsmmc_context_save(host);
1499 clk_disable(host->fclk);
1500 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1504 static const struct mmc_host_ops omap_hsmmc_ops = {
1505 .enable = omap_hsmmc_enable_fclk,
1506 .disable = omap_hsmmc_disable_fclk,
1507 .request = omap_hsmmc_request,
1508 .set_ios = omap_hsmmc_set_ios,
1509 .get_cd = omap_hsmmc_get_cd,
1510 .get_ro = omap_hsmmc_get_ro,
1511 /* NYET -- enable_sdio_irq */
1514 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1515 .enable = omap_hsmmc_enable,
1516 .disable = omap_hsmmc_disable,
1517 .request = omap_hsmmc_request,
1518 .set_ios = omap_hsmmc_set_ios,
1519 .get_cd = omap_hsmmc_get_cd,
1520 .get_ro = omap_hsmmc_get_ro,
1521 /* NYET -- enable_sdio_irq */
1524 #ifdef CONFIG_DEBUG_FS
1526 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1528 struct mmc_host *mmc = s->private;
1529 struct omap_hsmmc_host *host = mmc_priv(mmc);
1530 int context_loss = 0;
1532 if (host->pdata->get_context_loss_count)
1533 context_loss = host->pdata->get_context_loss_count(host->dev);
1535 seq_printf(s, "mmc%d:\n"
1538 " nesting_cnt:\t%d\n"
1539 " ctx_loss:\t%d:%d\n"
1541 mmc->index, mmc->enabled ? 1 : 0,
1542 host->dpm_state, mmc->nesting_cnt,
1543 host->context_loss, context_loss);
1545 if (host->suspended || host->dpm_state == OFF) {
1546 seq_printf(s, "host suspended, can't read registers\n");
1550 if (clk_enable(host->fclk) != 0) {
1551 seq_printf(s, "can't read the regs\n");
1555 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1556 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1557 seq_printf(s, "CON:\t\t0x%08x\n",
1558 OMAP_HSMMC_READ(host->base, CON));
1559 seq_printf(s, "HCTL:\t\t0x%08x\n",
1560 OMAP_HSMMC_READ(host->base, HCTL));
1561 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1562 OMAP_HSMMC_READ(host->base, SYSCTL));
1563 seq_printf(s, "IE:\t\t0x%08x\n",
1564 OMAP_HSMMC_READ(host->base, IE));
1565 seq_printf(s, "ISE:\t\t0x%08x\n",
1566 OMAP_HSMMC_READ(host->base, ISE));
1567 seq_printf(s, "CAPA:\t\t0x%08x\n",
1568 OMAP_HSMMC_READ(host->base, CAPA));
1570 clk_disable(host->fclk);
1575 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1577 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1580 static const struct file_operations mmc_regs_fops = {
1581 .open = omap_hsmmc_regs_open,
1583 .llseek = seq_lseek,
1584 .release = single_release,
1587 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1589 if (mmc->debugfs_root)
1590 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1591 mmc, &mmc_regs_fops);
1596 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1602 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1604 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1605 struct mmc_host *mmc;
1606 struct omap_hsmmc_host *host = NULL;
1607 struct resource *res;
1610 if (pdata == NULL) {
1611 dev_err(&pdev->dev, "Platform Data is missing\n");
1615 if (pdata->nr_slots == 0) {
1616 dev_err(&pdev->dev, "No Slots\n");
1620 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1621 irq = platform_get_irq(pdev, 0);
1622 if (res == NULL || irq < 0)
1625 res = request_mem_region(res->start, res->end - res->start + 1,
1630 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1636 host = mmc_priv(mmc);
1638 host->pdata = pdata;
1639 host->dev = &pdev->dev;
1641 host->dev->dma_mask = &pdata->dma_mask;
1644 host->id = pdev->id;
1646 host->mapbase = res->start;
1647 host->base = ioremap(host->mapbase, SZ_4K);
1648 host->power_mode = -1;
1650 platform_set_drvdata(pdev, host);
1651 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1653 if (mmc_slot(host).power_saving)
1654 mmc->ops = &omap_hsmmc_ps_ops;
1656 mmc->ops = &omap_hsmmc_ops;
1658 mmc->f_min = 400000;
1659 mmc->f_max = 52000000;
1661 sema_init(&host->sem, 1);
1662 spin_lock_init(&host->irq_lock);
1664 host->iclk = clk_get(&pdev->dev, "ick");
1665 if (IS_ERR(host->iclk)) {
1666 ret = PTR_ERR(host->iclk);
1670 host->fclk = clk_get(&pdev->dev, "fck");
1671 if (IS_ERR(host->fclk)) {
1672 ret = PTR_ERR(host->fclk);
1674 clk_put(host->iclk);
1678 omap_hsmmc_context_save(host);
1680 mmc->caps |= MMC_CAP_DISABLE;
1681 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
1682 /* we start off in DISABLED state */
1683 host->dpm_state = DISABLED;
1685 if (mmc_host_enable(host->mmc) != 0) {
1686 clk_put(host->iclk);
1687 clk_put(host->fclk);
1691 if (clk_enable(host->iclk) != 0) {
1692 mmc_host_disable(host->mmc);
1693 clk_put(host->iclk);
1694 clk_put(host->fclk);
1698 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1700 * MMC can still work without debounce clock.
1702 if (IS_ERR(host->dbclk))
1703 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1705 if (clk_enable(host->dbclk) != 0)
1706 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1709 host->dbclk_enabled = 1;
1711 /* Since we do only SG emulation, we can have as many segs
1713 mmc->max_phys_segs = 1024;
1714 mmc->max_hw_segs = 1024;
1716 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1717 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1718 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1719 mmc->max_seg_size = mmc->max_req_size;
1721 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1722 MMC_CAP_WAIT_WHILE_BUSY;
1724 if (mmc_slot(host).wires >= 8)
1725 mmc->caps |= MMC_CAP_8_BIT_DATA;
1726 else if (mmc_slot(host).wires >= 4)
1727 mmc->caps |= MMC_CAP_4_BIT_DATA;
1729 if (mmc_slot(host).nonremovable)
1730 mmc->caps |= MMC_CAP_NONREMOVABLE;
1732 omap_hsmmc_conf_bus_power(host);
1734 /* Select DMA lines */
1736 case OMAP_MMC1_DEVID:
1737 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1738 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1740 case OMAP_MMC2_DEVID:
1741 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1742 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1744 case OMAP_MMC3_DEVID:
1745 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1746 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1749 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1753 /* Request IRQ for MMC operations */
1754 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
1755 mmc_hostname(mmc), host);
1757 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1761 /* initialize power supplies, gpios, etc */
1762 if (pdata->init != NULL) {
1763 if (pdata->init(&pdev->dev) != 0) {
1764 dev_dbg(mmc_dev(host->mmc),
1765 "Unable to configure MMC IRQs\n");
1766 goto err_irq_cd_init;
1769 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1771 /* Request IRQ for card detect */
1772 if ((mmc_slot(host).card_detect_irq)) {
1773 ret = request_irq(mmc_slot(host).card_detect_irq,
1774 omap_hsmmc_cd_handler,
1775 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1777 mmc_hostname(mmc), host);
1779 dev_dbg(mmc_dev(host->mmc),
1780 "Unable to grab MMC CD IRQ\n");
1785 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1786 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1788 mmc_host_lazy_disable(host->mmc);
1790 omap_hsmmc_protect_card(host);
1794 if (mmc_slot(host).name != NULL) {
1795 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1799 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1800 ret = device_create_file(&mmc->class_dev,
1801 &dev_attr_cover_switch);
1803 goto err_cover_switch;
1806 omap_hsmmc_debugfs(mmc);
1811 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1813 mmc_remove_host(mmc);
1815 free_irq(mmc_slot(host).card_detect_irq, host);
1817 free_irq(host->irq, host);
1819 mmc_host_disable(host->mmc);
1820 clk_disable(host->iclk);
1821 clk_put(host->fclk);
1822 clk_put(host->iclk);
1823 if (host->dbclk_enabled) {
1824 clk_disable(host->dbclk);
1825 clk_put(host->dbclk);
1829 iounmap(host->base);
1831 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1832 release_mem_region(res->start, res->end - res->start + 1);
1838 static int omap_hsmmc_remove(struct platform_device *pdev)
1840 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1841 struct resource *res;
1844 mmc_host_enable(host->mmc);
1845 mmc_remove_host(host->mmc);
1846 if (host->pdata->cleanup)
1847 host->pdata->cleanup(&pdev->dev);
1848 free_irq(host->irq, host);
1849 if (mmc_slot(host).card_detect_irq)
1850 free_irq(mmc_slot(host).card_detect_irq, host);
1851 flush_scheduled_work();
1853 mmc_host_disable(host->mmc);
1854 clk_disable(host->iclk);
1855 clk_put(host->fclk);
1856 clk_put(host->iclk);
1857 if (host->dbclk_enabled) {
1858 clk_disable(host->dbclk);
1859 clk_put(host->dbclk);
1862 mmc_free_host(host->mmc);
1863 iounmap(host->base);
1866 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1868 release_mem_region(res->start, res->end - res->start + 1);
1869 platform_set_drvdata(pdev, NULL);
1875 static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
1878 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1880 if (host && host->suspended)
1884 host->suspended = 1;
1885 if (host->pdata->suspend) {
1886 ret = host->pdata->suspend(&pdev->dev,
1889 dev_dbg(mmc_dev(host->mmc),
1890 "Unable to handle MMC board"
1891 " level suspend\n");
1892 host->suspended = 0;
1896 cancel_work_sync(&host->mmc_carddetect_work);
1897 mmc_host_enable(host->mmc);
1898 ret = mmc_suspend_host(host->mmc, state);
1900 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1901 OMAP_HSMMC_WRITE(host->base, IE, 0);
1904 OMAP_HSMMC_WRITE(host->base, HCTL,
1905 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1906 mmc_host_disable(host->mmc);
1907 clk_disable(host->iclk);
1908 clk_disable(host->dbclk);
1910 host->suspended = 0;
1911 if (host->pdata->resume) {
1912 ret = host->pdata->resume(&pdev->dev,
1915 dev_dbg(mmc_dev(host->mmc),
1916 "Unmask interrupt failed\n");
1918 mmc_host_disable(host->mmc);
1925 /* Routine to resume the MMC device */
1926 static int omap_hsmmc_resume(struct platform_device *pdev)
1929 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1931 if (host && !host->suspended)
1935 ret = clk_enable(host->iclk);
1939 if (clk_enable(host->dbclk) != 0)
1940 dev_dbg(mmc_dev(host->mmc),
1941 "Enabling debounce clk failed\n");
1943 if (mmc_host_enable(host->mmc) != 0) {
1944 clk_disable(host->iclk);
1948 omap_hsmmc_conf_bus_power(host);
1950 if (host->pdata->resume) {
1951 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1953 dev_dbg(mmc_dev(host->mmc),
1954 "Unmask interrupt failed\n");
1957 omap_hsmmc_protect_card(host);
1959 /* Notify the core to resume the host */
1960 ret = mmc_resume_host(host->mmc);
1962 host->suspended = 0;
1964 mmc_host_lazy_disable(host->mmc);
1970 dev_dbg(mmc_dev(host->mmc),
1971 "Failed to enable MMC clocks during resume\n");
1976 #define omap_hsmmc_suspend NULL
1977 #define omap_hsmmc_resume NULL
1980 static struct platform_driver omap_hsmmc_driver = {
1981 .remove = omap_hsmmc_remove,
1982 .suspend = omap_hsmmc_suspend,
1983 .resume = omap_hsmmc_resume,
1985 .name = DRIVER_NAME,
1986 .owner = THIS_MODULE,
1990 static int __init omap_hsmmc_init(void)
1992 /* Register the MMC driver */
1993 return platform_driver_register(&omap_hsmmc_driver);
1996 static void __exit omap_hsmmc_cleanup(void)
1998 /* Unregister MMC driver */
1999 platform_driver_unregister(&omap_hsmmc_driver);
2002 module_init(omap_hsmmc_init);
2003 module_exit(omap_hsmmc_cleanup);
2005 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2006 MODULE_LICENSE("GPL");
2007 MODULE_ALIAS("platform:" DRIVER_NAME);
2008 MODULE_AUTHOR("Texas Instruments Inc");