2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
114 enum radeon_combios_ddc {
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
149 struct radeon_device *rdev = dev->dev_private;
151 uint16_t offset = 0, check_offset;
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
161 offset = check_offset;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
166 offset = check_offset;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
171 offset = check_offset;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
176 offset = check_offset;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
181 offset = check_offset;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
186 offset = check_offset;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
191 offset = check_offset;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
196 offset = check_offset;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
201 offset = check_offset;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
206 offset = check_offset;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
211 offset = check_offset;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
216 offset = check_offset;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
221 offset = check_offset;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
226 offset = check_offset;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
231 offset = check_offset;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
236 offset = check_offset;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
241 offset = check_offset;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
246 offset = check_offset;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
251 offset = check_offset;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
256 offset = check_offset;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
261 offset = check_offset;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
266 offset = check_offset;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
271 offset = check_offset;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
276 offset = check_offset;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
281 offset = check_offset;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
286 offset = check_offset;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
291 offset = check_offset;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
296 offset = check_offset;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
301 offset = check_offset;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
306 offset = check_offset;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
311 offset = check_offset;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
316 offset = check_offset;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
321 offset = check_offset;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
326 offset = check_offset;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
333 rev = RBIOS8(check_offset);
335 check_offset = RBIOS16(check_offset + 0x3);
337 offset = check_offset;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
345 rev = RBIOS8(check_offset);
347 check_offset = RBIOS16(check_offset + 0x5);
349 offset = check_offset;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
357 rev = RBIOS8(check_offset);
359 check_offset = RBIOS16(check_offset + 0x7);
361 offset = check_offset;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
369 rev = RBIOS8(check_offset);
371 check_offset = RBIOS16(check_offset + 0x9);
373 offset = check_offset;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
381 while (RBIOS8(check_offset++));
384 offset = check_offset;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
391 check_offset = RBIOS16(check_offset + 0x11);
393 offset = check_offset;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
400 check_offset = RBIOS16(check_offset + 0x13);
402 offset = check_offset;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
409 check_offset = RBIOS16(check_offset + 0x15);
411 offset = check_offset;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
418 check_offset = RBIOS16(check_offset + 0x17);
420 offset = check_offset;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
427 check_offset = RBIOS16(check_offset + 0x2);
429 offset = check_offset;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
436 check_offset = RBIOS16(check_offset + 0x4);
438 offset = check_offset;
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
453 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
457 edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1),
462 memcpy((unsigned char *)edid,
463 (unsigned char *)(rdev->bios + edid_info), EDID_LENGTH);
465 if (!drm_edid_is_valid(edid)) {
470 rdev->mode_info.bios_hardcoded_edid = edid;
475 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
477 if (rdev->mode_info.bios_hardcoded_edid)
478 return rdev->mode_info.bios_hardcoded_edid;
482 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
485 struct radeon_i2c_bus_rec i2c;
487 if (ddc_line == RADEON_GPIOPAD_MASK) {
488 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
489 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
490 i2c.a_clk_reg = RADEON_GPIOPAD_A;
491 i2c.a_data_reg = RADEON_GPIOPAD_A;
492 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
493 i2c.en_data_reg = RADEON_GPIOPAD_EN;
494 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
495 i2c.y_data_reg = RADEON_GPIOPAD_Y;
496 } else if (ddc_line == RADEON_MDGPIO_MASK) {
497 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
498 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
499 i2c.a_clk_reg = RADEON_MDGPIO_A;
500 i2c.a_data_reg = RADEON_MDGPIO_A;
501 i2c.en_clk_reg = RADEON_MDGPIO_EN;
502 i2c.en_data_reg = RADEON_MDGPIO_EN;
503 i2c.y_clk_reg = RADEON_MDGPIO_Y;
504 i2c.y_data_reg = RADEON_MDGPIO_Y;
506 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
507 i2c.mask_data_mask = RADEON_GPIO_EN_0;
508 i2c.a_clk_mask = RADEON_GPIO_A_1;
509 i2c.a_data_mask = RADEON_GPIO_A_0;
510 i2c.en_clk_mask = RADEON_GPIO_EN_1;
511 i2c.en_data_mask = RADEON_GPIO_EN_0;
512 i2c.y_clk_mask = RADEON_GPIO_Y_1;
513 i2c.y_data_mask = RADEON_GPIO_Y_0;
515 i2c.mask_clk_reg = ddc_line;
516 i2c.mask_data_reg = ddc_line;
517 i2c.a_clk_reg = ddc_line;
518 i2c.a_data_reg = ddc_line;
519 i2c.en_clk_reg = ddc_line;
520 i2c.en_data_reg = ddc_line;
521 i2c.y_clk_reg = ddc_line;
522 i2c.y_data_reg = ddc_line;
525 switch (rdev->family) {
533 case RADEON_GPIO_DVI_DDC:
534 /* in theory this should be hw capable,
535 * but it doesn't seem to work
537 i2c.hw_capable = false;
540 i2c.hw_capable = false;
546 case RADEON_GPIO_DVI_DDC:
547 case RADEON_GPIO_MONID:
548 i2c.hw_capable = true;
551 i2c.hw_capable = false;
558 case RADEON_GPIO_VGA_DDC:
559 case RADEON_GPIO_DVI_DDC:
560 case RADEON_GPIO_CRT2_DDC:
561 i2c.hw_capable = true;
564 i2c.hw_capable = false;
571 case RADEON_GPIO_VGA_DDC:
572 case RADEON_GPIO_DVI_DDC:
573 i2c.hw_capable = true;
576 i2c.hw_capable = false;
585 case RADEON_GPIO_VGA_DDC:
586 case RADEON_GPIO_DVI_DDC:
587 i2c.hw_capable = true;
589 case RADEON_GPIO_MONID:
590 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
591 * reliably on some pre-r4xx hardware; not sure why.
593 i2c.hw_capable = false;
596 i2c.hw_capable = false;
601 i2c.hw_capable = false;
616 bool radeon_combios_get_clock_info(struct drm_device *dev)
618 struct radeon_device *rdev = dev->dev_private;
620 struct radeon_pll *p1pll = &rdev->clock.p1pll;
621 struct radeon_pll *p2pll = &rdev->clock.p2pll;
622 struct radeon_pll *spll = &rdev->clock.spll;
623 struct radeon_pll *mpll = &rdev->clock.mpll;
627 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
629 rev = RBIOS8(pll_info);
632 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
633 p1pll->reference_div = RBIOS16(pll_info + 0x10);
634 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
635 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
638 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
639 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
641 p1pll->pll_in_min = 40;
642 p1pll->pll_in_max = 500;
647 spll->reference_freq = RBIOS16(pll_info + 0x1a);
648 spll->reference_div = RBIOS16(pll_info + 0x1c);
649 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
650 spll->pll_out_max = RBIOS32(pll_info + 0x22);
653 spll->pll_in_min = RBIOS32(pll_info + 0x48);
654 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
657 spll->pll_in_min = 40;
658 spll->pll_in_max = 500;
662 mpll->reference_freq = RBIOS16(pll_info + 0x26);
663 mpll->reference_div = RBIOS16(pll_info + 0x28);
664 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
665 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
668 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
669 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
672 mpll->pll_in_min = 40;
673 mpll->pll_in_max = 500;
676 /* default sclk/mclk */
677 sclk = RBIOS16(pll_info + 0xa);
678 mclk = RBIOS16(pll_info + 0x8);
684 rdev->clock.default_sclk = sclk;
685 rdev->clock.default_mclk = mclk;
692 bool radeon_combios_sideport_present(struct radeon_device *rdev)
694 struct drm_device *dev = rdev->ddev;
697 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
700 if (RBIOS16(igp_info + 0x4))
706 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
707 0x00000808, /* r100 */
708 0x00000808, /* rv100 */
709 0x00000808, /* rs100 */
710 0x00000808, /* rv200 */
711 0x00000808, /* rs200 */
712 0x00000808, /* r200 */
713 0x00000808, /* rv250 */
714 0x00000000, /* rs300 */
715 0x00000808, /* rv280 */
716 0x00000808, /* r300 */
717 0x00000808, /* r350 */
718 0x00000808, /* rv350 */
719 0x00000808, /* rv380 */
720 0x00000808, /* r420 */
721 0x00000808, /* r423 */
722 0x00000808, /* rv410 */
723 0x00000000, /* rs400 */
724 0x00000000, /* rs480 */
727 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
728 struct radeon_encoder_primary_dac *p_dac)
730 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
734 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
738 struct drm_device *dev = encoder->base.dev;
739 struct radeon_device *rdev = dev->dev_private;
741 uint8_t rev, bg, dac;
742 struct radeon_encoder_primary_dac *p_dac = NULL;
745 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
751 /* check CRT table */
752 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
754 rev = RBIOS8(dac_info) & 0x3;
756 bg = RBIOS8(dac_info + 0x2) & 0xf;
757 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
758 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
760 bg = RBIOS8(dac_info + 0x2) & 0xf;
761 dac = RBIOS8(dac_info + 0x3) & 0xf;
762 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
767 if (!found) /* fallback to defaults */
768 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
774 radeon_combios_get_tv_info(struct radeon_device *rdev)
776 struct drm_device *dev = rdev->ddev;
778 enum radeon_tv_std tv_std = TV_STD_NTSC;
780 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
782 if (RBIOS8(tv_info + 6) == 'T') {
783 switch (RBIOS8(tv_info + 7) & 0xf) {
785 tv_std = TV_STD_NTSC;
786 DRM_INFO("Default TV standard: NTSC\n");
790 DRM_INFO("Default TV standard: PAL\n");
793 tv_std = TV_STD_PAL_M;
794 DRM_INFO("Default TV standard: PAL-M\n");
797 tv_std = TV_STD_PAL_60;
798 DRM_INFO("Default TV standard: PAL-60\n");
801 tv_std = TV_STD_NTSC_J;
802 DRM_INFO("Default TV standard: NTSC-J\n");
805 tv_std = TV_STD_SCART_PAL;
806 DRM_INFO("Default TV standard: SCART-PAL\n");
809 tv_std = TV_STD_NTSC;
811 ("Unknown TV standard; defaulting to NTSC\n");
815 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
817 DRM_INFO("29.498928713 MHz TV ref clk\n");
820 DRM_INFO("28.636360000 MHz TV ref clk\n");
823 DRM_INFO("14.318180000 MHz TV ref clk\n");
826 DRM_INFO("27.000000000 MHz TV ref clk\n");
836 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
837 0x00000000, /* r100 */
838 0x00280000, /* rv100 */
839 0x00000000, /* rs100 */
840 0x00880000, /* rv200 */
841 0x00000000, /* rs200 */
842 0x00000000, /* r200 */
843 0x00770000, /* rv250 */
844 0x00290000, /* rs300 */
845 0x00560000, /* rv280 */
846 0x00780000, /* r300 */
847 0x00770000, /* r350 */
848 0x00780000, /* rv350 */
849 0x00780000, /* rv380 */
850 0x01080000, /* r420 */
851 0x01080000, /* r423 */
852 0x01080000, /* rv410 */
853 0x00780000, /* rs400 */
854 0x00780000, /* rs480 */
857 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
858 struct radeon_encoder_tv_dac *tv_dac)
860 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
861 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
862 tv_dac->ps2_tvdac_adj = 0x00880000;
863 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
864 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
868 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
872 struct drm_device *dev = encoder->base.dev;
873 struct radeon_device *rdev = dev->dev_private;
875 uint8_t rev, bg, dac;
876 struct radeon_encoder_tv_dac *tv_dac = NULL;
879 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
883 /* first check TV table */
884 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
886 rev = RBIOS8(dac_info + 0x3);
888 bg = RBIOS8(dac_info + 0xc) & 0xf;
889 dac = RBIOS8(dac_info + 0xd) & 0xf;
890 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
892 bg = RBIOS8(dac_info + 0xe) & 0xf;
893 dac = RBIOS8(dac_info + 0xf) & 0xf;
894 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
896 bg = RBIOS8(dac_info + 0x10) & 0xf;
897 dac = RBIOS8(dac_info + 0x11) & 0xf;
898 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
900 } else if (rev > 1) {
901 bg = RBIOS8(dac_info + 0xc) & 0xf;
902 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
903 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
905 bg = RBIOS8(dac_info + 0xd) & 0xf;
906 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
907 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
909 bg = RBIOS8(dac_info + 0xe) & 0xf;
910 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
911 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
914 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
917 /* then check CRT table */
919 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
921 rev = RBIOS8(dac_info) & 0x3;
923 bg = RBIOS8(dac_info + 0x3) & 0xf;
924 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
925 tv_dac->ps2_tvdac_adj =
926 (bg << 16) | (dac << 20);
927 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
928 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
931 bg = RBIOS8(dac_info + 0x4) & 0xf;
932 dac = RBIOS8(dac_info + 0x5) & 0xf;
933 tv_dac->ps2_tvdac_adj =
934 (bg << 16) | (dac << 20);
935 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
936 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
940 DRM_INFO("No TV DAC info found in BIOS\n");
944 if (!found) /* fallback to defaults */
945 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
950 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
954 struct radeon_encoder_lvds *lvds = NULL;
955 uint32_t fp_vert_stretch, fp_horz_stretch;
956 uint32_t ppll_div_sel, ppll_val;
957 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
959 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
964 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
965 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
967 /* These should be fail-safe defaults, fingers crossed */
968 lvds->panel_pwr_delay = 200;
969 lvds->panel_vcc_delay = 2000;
971 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
972 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
973 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
975 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
976 lvds->native_mode.vdisplay =
977 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
978 RADEON_VERT_PANEL_SHIFT) + 1;
980 lvds->native_mode.vdisplay =
981 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
983 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
984 lvds->native_mode.hdisplay =
985 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
986 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
988 lvds->native_mode.hdisplay =
989 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
991 if ((lvds->native_mode.hdisplay < 640) ||
992 (lvds->native_mode.vdisplay < 480)) {
993 lvds->native_mode.hdisplay = 640;
994 lvds->native_mode.vdisplay = 480;
997 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
998 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
999 if ((ppll_val & 0x000707ff) == 0x1bb)
1000 lvds->use_bios_dividers = false;
1002 lvds->panel_ref_divider =
1003 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1004 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1005 lvds->panel_fb_divider = ppll_val & 0x7ff;
1007 if ((lvds->panel_ref_divider != 0) &&
1008 (lvds->panel_fb_divider > 3))
1009 lvds->use_bios_dividers = true;
1011 lvds->panel_vcc_delay = 200;
1013 DRM_INFO("Panel info derived from registers\n");
1014 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1015 lvds->native_mode.vdisplay);
1020 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1023 struct drm_device *dev = encoder->base.dev;
1024 struct radeon_device *rdev = dev->dev_private;
1026 uint32_t panel_setup;
1029 struct radeon_encoder_lvds *lvds = NULL;
1031 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1034 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1039 for (i = 0; i < 24; i++)
1040 stmp[i] = RBIOS8(lcd_info + i + 1);
1043 DRM_INFO("Panel ID String: %s\n", stmp);
1045 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1046 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1048 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1049 lvds->native_mode.vdisplay);
1051 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1052 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1054 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1055 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1056 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1058 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1059 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1060 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1061 if ((lvds->panel_ref_divider != 0) &&
1062 (lvds->panel_fb_divider > 3))
1063 lvds->use_bios_dividers = true;
1065 panel_setup = RBIOS32(lcd_info + 0x39);
1066 lvds->lvds_gen_cntl = 0xff00;
1067 if (panel_setup & 0x1)
1068 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1070 if ((panel_setup >> 4) & 0x1)
1071 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1073 switch ((panel_setup >> 8) & 0x7) {
1075 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1078 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1081 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1087 if ((panel_setup >> 16) & 0x1)
1088 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1090 if ((panel_setup >> 17) & 0x1)
1091 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1093 if ((panel_setup >> 18) & 0x1)
1094 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1096 if ((panel_setup >> 23) & 0x1)
1097 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1099 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1101 for (i = 0; i < 32; i++) {
1102 tmp = RBIOS16(lcd_info + 64 + i * 2);
1106 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1107 (RBIOS16(tmp + 2) ==
1108 lvds->native_mode.vdisplay)) {
1109 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1110 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1111 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1112 RBIOS16(tmp + 21)) * 8;
1114 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1115 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1116 lvds->native_mode.vsync_end =
1117 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1118 (RBIOS16(tmp + 28) & 0x7ff);
1120 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1121 lvds->native_mode.flags = 0;
1122 /* set crtc values */
1123 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1128 DRM_INFO("No panel info found in BIOS\n");
1129 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1133 encoder->native_mode = lvds->native_mode;
1137 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1138 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1139 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1140 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1141 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1142 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1143 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1144 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1145 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1146 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1147 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1148 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1149 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1150 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1151 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1152 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1153 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1154 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1155 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1158 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1159 struct radeon_encoder_int_tmds *tmds)
1161 struct drm_device *dev = encoder->base.dev;
1162 struct radeon_device *rdev = dev->dev_private;
1165 for (i = 0; i < 4; i++) {
1166 tmds->tmds_pll[i].value =
1167 default_tmds_pll[rdev->family][i].value;
1168 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1174 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1175 struct radeon_encoder_int_tmds *tmds)
1177 struct drm_device *dev = encoder->base.dev;
1178 struct radeon_device *rdev = dev->dev_private;
1183 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1186 ver = RBIOS8(tmds_info);
1187 DRM_INFO("DFP table revision: %d\n", ver);
1189 n = RBIOS8(tmds_info + 5) + 1;
1192 for (i = 0; i < n; i++) {
1193 tmds->tmds_pll[i].value =
1194 RBIOS32(tmds_info + i * 10 + 0x08);
1195 tmds->tmds_pll[i].freq =
1196 RBIOS16(tmds_info + i * 10 + 0x10);
1197 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1198 tmds->tmds_pll[i].freq,
1199 tmds->tmds_pll[i].value);
1201 } else if (ver == 4) {
1203 n = RBIOS8(tmds_info + 5) + 1;
1206 for (i = 0; i < n; i++) {
1207 tmds->tmds_pll[i].value =
1208 RBIOS32(tmds_info + stride + 0x08);
1209 tmds->tmds_pll[i].freq =
1210 RBIOS16(tmds_info + stride + 0x10);
1215 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1216 tmds->tmds_pll[i].freq,
1217 tmds->tmds_pll[i].value);
1221 DRM_INFO("No TMDS info found in BIOS\n");
1227 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1228 struct radeon_encoder_ext_tmds *tmds)
1230 struct drm_device *dev = encoder->base.dev;
1231 struct radeon_device *rdev = dev->dev_private;
1232 struct radeon_i2c_bus_rec i2c_bus;
1234 /* default for macs */
1235 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1236 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1238 /* XXX some macs have duallink chips */
1239 switch (rdev->mode_info.connector_table) {
1240 case CT_POWERBOOK_EXTERNAL:
1241 case CT_MINI_EXTERNAL:
1243 tmds->dvo_chip = DVO_SIL164;
1244 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1251 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1252 struct radeon_encoder_ext_tmds *tmds)
1254 struct drm_device *dev = encoder->base.dev;
1255 struct radeon_device *rdev = dev->dev_private;
1257 uint8_t ver, id, blocks, clk, data;
1259 enum radeon_combios_ddc gpio;
1260 struct radeon_i2c_bus_rec i2c_bus;
1262 tmds->i2c_bus = NULL;
1263 if (rdev->flags & RADEON_IS_IGP) {
1264 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1266 ver = RBIOS8(offset);
1267 DRM_INFO("GPIO Table revision: %d\n", ver);
1268 blocks = RBIOS8(offset + 2);
1269 for (i = 0; i < blocks; i++) {
1270 id = RBIOS8(offset + 3 + (i * 5) + 0);
1272 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1273 data = RBIOS8(offset + 3 + (i * 5) + 4);
1274 i2c_bus.valid = true;
1275 i2c_bus.mask_clk_mask = (1 << clk);
1276 i2c_bus.mask_data_mask = (1 << data);
1277 i2c_bus.a_clk_mask = (1 << clk);
1278 i2c_bus.a_data_mask = (1 << data);
1279 i2c_bus.en_clk_mask = (1 << clk);
1280 i2c_bus.en_data_mask = (1 << data);
1281 i2c_bus.y_clk_mask = (1 << clk);
1282 i2c_bus.y_data_mask = (1 << data);
1283 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1284 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1285 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1286 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1287 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1288 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1289 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1290 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1291 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1292 tmds->dvo_chip = DVO_SIL164;
1293 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1299 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1301 ver = RBIOS8(offset);
1302 DRM_INFO("External TMDS Table revision: %d\n", ver);
1303 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1304 tmds->slave_addr >>= 1; /* 7 bit addressing */
1305 gpio = RBIOS8(offset + 4 + 3);
1308 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1309 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1312 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1313 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1316 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1317 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1320 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1321 if (rdev->family >= CHIP_R300)
1322 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1324 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1325 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1327 case DDC_LCD: /* MM i2c */
1328 i2c_bus.valid = true;
1329 i2c_bus.hw_capable = true;
1330 i2c_bus.mm_i2c = true;
1331 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1334 DRM_ERROR("Unsupported gpio %d\n", gpio);
1340 if (!tmds->i2c_bus) {
1341 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1348 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1350 struct radeon_device *rdev = dev->dev_private;
1351 struct radeon_i2c_bus_rec ddc_i2c;
1352 struct radeon_hpd hpd;
1354 rdev->mode_info.connector_table = radeon_connector_table;
1355 if (rdev->mode_info.connector_table == CT_NONE) {
1356 #ifdef CONFIG_PPC_PMAC
1357 if (machine_is_compatible("PowerBook3,3")) {
1358 /* powerbook with VGA */
1359 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1360 } else if (machine_is_compatible("PowerBook3,4") ||
1361 machine_is_compatible("PowerBook3,5")) {
1362 /* powerbook with internal tmds */
1363 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1364 } else if (machine_is_compatible("PowerBook5,1") ||
1365 machine_is_compatible("PowerBook5,2") ||
1366 machine_is_compatible("PowerBook5,3") ||
1367 machine_is_compatible("PowerBook5,4") ||
1368 machine_is_compatible("PowerBook5,5")) {
1369 /* powerbook with external single link tmds (sil164) */
1370 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1371 } else if (machine_is_compatible("PowerBook5,6")) {
1372 /* powerbook with external dual or single link tmds */
1373 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1374 } else if (machine_is_compatible("PowerBook5,7") ||
1375 machine_is_compatible("PowerBook5,8") ||
1376 machine_is_compatible("PowerBook5,9")) {
1377 /* PowerBook6,2 ? */
1378 /* powerbook with external dual link tmds (sil1178?) */
1379 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1380 } else if (machine_is_compatible("PowerBook4,1") ||
1381 machine_is_compatible("PowerBook4,2") ||
1382 machine_is_compatible("PowerBook4,3") ||
1383 machine_is_compatible("PowerBook6,3") ||
1384 machine_is_compatible("PowerBook6,5") ||
1385 machine_is_compatible("PowerBook6,7")) {
1387 rdev->mode_info.connector_table = CT_IBOOK;
1388 } else if (machine_is_compatible("PowerMac4,4")) {
1390 rdev->mode_info.connector_table = CT_EMAC;
1391 } else if (machine_is_compatible("PowerMac10,1")) {
1392 /* mini with internal tmds */
1393 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1394 } else if (machine_is_compatible("PowerMac10,2")) {
1395 /* mini with external tmds */
1396 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1397 } else if (machine_is_compatible("PowerMac12,1")) {
1399 /* imac g5 isight */
1400 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1402 #endif /* CONFIG_PPC_PMAC */
1403 rdev->mode_info.connector_table = CT_GENERIC;
1406 switch (rdev->mode_info.connector_table) {
1408 DRM_INFO("Connector Table: %d (generic)\n",
1409 rdev->mode_info.connector_table);
1410 /* these are the most common settings */
1411 if (rdev->flags & RADEON_SINGLE_CRTC) {
1412 /* VGA - primary dac */
1413 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1414 hpd.hpd = RADEON_HPD_NONE;
1415 radeon_add_legacy_encoder(dev,
1416 radeon_get_encoder_id(dev,
1417 ATOM_DEVICE_CRT1_SUPPORT,
1419 ATOM_DEVICE_CRT1_SUPPORT);
1420 radeon_add_legacy_connector(dev, 0,
1421 ATOM_DEVICE_CRT1_SUPPORT,
1422 DRM_MODE_CONNECTOR_VGA,
1424 CONNECTOR_OBJECT_ID_VGA,
1426 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1428 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1429 hpd.hpd = RADEON_HPD_NONE;
1430 radeon_add_legacy_encoder(dev,
1431 radeon_get_encoder_id(dev,
1432 ATOM_DEVICE_LCD1_SUPPORT,
1434 ATOM_DEVICE_LCD1_SUPPORT);
1435 radeon_add_legacy_connector(dev, 0,
1436 ATOM_DEVICE_LCD1_SUPPORT,
1437 DRM_MODE_CONNECTOR_LVDS,
1439 CONNECTOR_OBJECT_ID_LVDS,
1442 /* VGA - primary dac */
1443 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1444 hpd.hpd = RADEON_HPD_NONE;
1445 radeon_add_legacy_encoder(dev,
1446 radeon_get_encoder_id(dev,
1447 ATOM_DEVICE_CRT1_SUPPORT,
1449 ATOM_DEVICE_CRT1_SUPPORT);
1450 radeon_add_legacy_connector(dev, 1,
1451 ATOM_DEVICE_CRT1_SUPPORT,
1452 DRM_MODE_CONNECTOR_VGA,
1454 CONNECTOR_OBJECT_ID_VGA,
1457 /* DVI-I - tv dac, int tmds */
1458 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1459 hpd.hpd = RADEON_HPD_1;
1460 radeon_add_legacy_encoder(dev,
1461 radeon_get_encoder_id(dev,
1462 ATOM_DEVICE_DFP1_SUPPORT,
1464 ATOM_DEVICE_DFP1_SUPPORT);
1465 radeon_add_legacy_encoder(dev,
1466 radeon_get_encoder_id(dev,
1467 ATOM_DEVICE_CRT2_SUPPORT,
1469 ATOM_DEVICE_CRT2_SUPPORT);
1470 radeon_add_legacy_connector(dev, 0,
1471 ATOM_DEVICE_DFP1_SUPPORT |
1472 ATOM_DEVICE_CRT2_SUPPORT,
1473 DRM_MODE_CONNECTOR_DVII,
1475 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1478 /* VGA - primary dac */
1479 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1480 hpd.hpd = RADEON_HPD_NONE;
1481 radeon_add_legacy_encoder(dev,
1482 radeon_get_encoder_id(dev,
1483 ATOM_DEVICE_CRT1_SUPPORT,
1485 ATOM_DEVICE_CRT1_SUPPORT);
1486 radeon_add_legacy_connector(dev, 1,
1487 ATOM_DEVICE_CRT1_SUPPORT,
1488 DRM_MODE_CONNECTOR_VGA,
1490 CONNECTOR_OBJECT_ID_VGA,
1494 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1496 ddc_i2c.valid = false;
1497 hpd.hpd = RADEON_HPD_NONE;
1498 radeon_add_legacy_encoder(dev,
1499 radeon_get_encoder_id(dev,
1500 ATOM_DEVICE_TV1_SUPPORT,
1502 ATOM_DEVICE_TV1_SUPPORT);
1503 radeon_add_legacy_connector(dev, 2,
1504 ATOM_DEVICE_TV1_SUPPORT,
1505 DRM_MODE_CONNECTOR_SVIDEO,
1507 CONNECTOR_OBJECT_ID_SVIDEO,
1512 DRM_INFO("Connector Table: %d (ibook)\n",
1513 rdev->mode_info.connector_table);
1515 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1516 hpd.hpd = RADEON_HPD_NONE;
1517 radeon_add_legacy_encoder(dev,
1518 radeon_get_encoder_id(dev,
1519 ATOM_DEVICE_LCD1_SUPPORT,
1521 ATOM_DEVICE_LCD1_SUPPORT);
1522 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1523 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1524 CONNECTOR_OBJECT_ID_LVDS,
1527 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1528 hpd.hpd = RADEON_HPD_NONE;
1529 radeon_add_legacy_encoder(dev,
1530 radeon_get_encoder_id(dev,
1531 ATOM_DEVICE_CRT2_SUPPORT,
1533 ATOM_DEVICE_CRT2_SUPPORT);
1534 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1535 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1536 CONNECTOR_OBJECT_ID_VGA,
1539 ddc_i2c.valid = false;
1540 hpd.hpd = RADEON_HPD_NONE;
1541 radeon_add_legacy_encoder(dev,
1542 radeon_get_encoder_id(dev,
1543 ATOM_DEVICE_TV1_SUPPORT,
1545 ATOM_DEVICE_TV1_SUPPORT);
1546 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1547 DRM_MODE_CONNECTOR_SVIDEO,
1549 CONNECTOR_OBJECT_ID_SVIDEO,
1552 case CT_POWERBOOK_EXTERNAL:
1553 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1554 rdev->mode_info.connector_table);
1556 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1557 hpd.hpd = RADEON_HPD_NONE;
1558 radeon_add_legacy_encoder(dev,
1559 radeon_get_encoder_id(dev,
1560 ATOM_DEVICE_LCD1_SUPPORT,
1562 ATOM_DEVICE_LCD1_SUPPORT);
1563 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1564 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1565 CONNECTOR_OBJECT_ID_LVDS,
1567 /* DVI-I - primary dac, ext tmds */
1568 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1569 hpd.hpd = RADEON_HPD_2; /* ??? */
1570 radeon_add_legacy_encoder(dev,
1571 radeon_get_encoder_id(dev,
1572 ATOM_DEVICE_DFP2_SUPPORT,
1574 ATOM_DEVICE_DFP2_SUPPORT);
1575 radeon_add_legacy_encoder(dev,
1576 radeon_get_encoder_id(dev,
1577 ATOM_DEVICE_CRT1_SUPPORT,
1579 ATOM_DEVICE_CRT1_SUPPORT);
1580 /* XXX some are SL */
1581 radeon_add_legacy_connector(dev, 1,
1582 ATOM_DEVICE_DFP2_SUPPORT |
1583 ATOM_DEVICE_CRT1_SUPPORT,
1584 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1585 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1588 ddc_i2c.valid = false;
1589 hpd.hpd = RADEON_HPD_NONE;
1590 radeon_add_legacy_encoder(dev,
1591 radeon_get_encoder_id(dev,
1592 ATOM_DEVICE_TV1_SUPPORT,
1594 ATOM_DEVICE_TV1_SUPPORT);
1595 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1596 DRM_MODE_CONNECTOR_SVIDEO,
1598 CONNECTOR_OBJECT_ID_SVIDEO,
1601 case CT_POWERBOOK_INTERNAL:
1602 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1603 rdev->mode_info.connector_table);
1605 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1606 hpd.hpd = RADEON_HPD_NONE;
1607 radeon_add_legacy_encoder(dev,
1608 radeon_get_encoder_id(dev,
1609 ATOM_DEVICE_LCD1_SUPPORT,
1611 ATOM_DEVICE_LCD1_SUPPORT);
1612 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1613 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1614 CONNECTOR_OBJECT_ID_LVDS,
1616 /* DVI-I - primary dac, int tmds */
1617 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1618 hpd.hpd = RADEON_HPD_1; /* ??? */
1619 radeon_add_legacy_encoder(dev,
1620 radeon_get_encoder_id(dev,
1621 ATOM_DEVICE_DFP1_SUPPORT,
1623 ATOM_DEVICE_DFP1_SUPPORT);
1624 radeon_add_legacy_encoder(dev,
1625 radeon_get_encoder_id(dev,
1626 ATOM_DEVICE_CRT1_SUPPORT,
1628 ATOM_DEVICE_CRT1_SUPPORT);
1629 radeon_add_legacy_connector(dev, 1,
1630 ATOM_DEVICE_DFP1_SUPPORT |
1631 ATOM_DEVICE_CRT1_SUPPORT,
1632 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1633 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1636 ddc_i2c.valid = false;
1637 hpd.hpd = RADEON_HPD_NONE;
1638 radeon_add_legacy_encoder(dev,
1639 radeon_get_encoder_id(dev,
1640 ATOM_DEVICE_TV1_SUPPORT,
1642 ATOM_DEVICE_TV1_SUPPORT);
1643 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1644 DRM_MODE_CONNECTOR_SVIDEO,
1646 CONNECTOR_OBJECT_ID_SVIDEO,
1649 case CT_POWERBOOK_VGA:
1650 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1651 rdev->mode_info.connector_table);
1653 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1654 hpd.hpd = RADEON_HPD_NONE;
1655 radeon_add_legacy_encoder(dev,
1656 radeon_get_encoder_id(dev,
1657 ATOM_DEVICE_LCD1_SUPPORT,
1659 ATOM_DEVICE_LCD1_SUPPORT);
1660 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1661 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1662 CONNECTOR_OBJECT_ID_LVDS,
1664 /* VGA - primary dac */
1665 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1666 hpd.hpd = RADEON_HPD_NONE;
1667 radeon_add_legacy_encoder(dev,
1668 radeon_get_encoder_id(dev,
1669 ATOM_DEVICE_CRT1_SUPPORT,
1671 ATOM_DEVICE_CRT1_SUPPORT);
1672 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1673 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1674 CONNECTOR_OBJECT_ID_VGA,
1677 ddc_i2c.valid = false;
1678 hpd.hpd = RADEON_HPD_NONE;
1679 radeon_add_legacy_encoder(dev,
1680 radeon_get_encoder_id(dev,
1681 ATOM_DEVICE_TV1_SUPPORT,
1683 ATOM_DEVICE_TV1_SUPPORT);
1684 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1685 DRM_MODE_CONNECTOR_SVIDEO,
1687 CONNECTOR_OBJECT_ID_SVIDEO,
1690 case CT_MINI_EXTERNAL:
1691 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1692 rdev->mode_info.connector_table);
1693 /* DVI-I - tv dac, ext tmds */
1694 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1695 hpd.hpd = RADEON_HPD_2; /* ??? */
1696 radeon_add_legacy_encoder(dev,
1697 radeon_get_encoder_id(dev,
1698 ATOM_DEVICE_DFP2_SUPPORT,
1700 ATOM_DEVICE_DFP2_SUPPORT);
1701 radeon_add_legacy_encoder(dev,
1702 radeon_get_encoder_id(dev,
1703 ATOM_DEVICE_CRT2_SUPPORT,
1705 ATOM_DEVICE_CRT2_SUPPORT);
1706 /* XXX are any DL? */
1707 radeon_add_legacy_connector(dev, 0,
1708 ATOM_DEVICE_DFP2_SUPPORT |
1709 ATOM_DEVICE_CRT2_SUPPORT,
1710 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1711 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1714 ddc_i2c.valid = false;
1715 hpd.hpd = RADEON_HPD_NONE;
1716 radeon_add_legacy_encoder(dev,
1717 radeon_get_encoder_id(dev,
1718 ATOM_DEVICE_TV1_SUPPORT,
1720 ATOM_DEVICE_TV1_SUPPORT);
1721 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1722 DRM_MODE_CONNECTOR_SVIDEO,
1724 CONNECTOR_OBJECT_ID_SVIDEO,
1727 case CT_MINI_INTERNAL:
1728 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1729 rdev->mode_info.connector_table);
1730 /* DVI-I - tv dac, int tmds */
1731 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1732 hpd.hpd = RADEON_HPD_1; /* ??? */
1733 radeon_add_legacy_encoder(dev,
1734 radeon_get_encoder_id(dev,
1735 ATOM_DEVICE_DFP1_SUPPORT,
1737 ATOM_DEVICE_DFP1_SUPPORT);
1738 radeon_add_legacy_encoder(dev,
1739 radeon_get_encoder_id(dev,
1740 ATOM_DEVICE_CRT2_SUPPORT,
1742 ATOM_DEVICE_CRT2_SUPPORT);
1743 radeon_add_legacy_connector(dev, 0,
1744 ATOM_DEVICE_DFP1_SUPPORT |
1745 ATOM_DEVICE_CRT2_SUPPORT,
1746 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1747 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1750 ddc_i2c.valid = false;
1751 hpd.hpd = RADEON_HPD_NONE;
1752 radeon_add_legacy_encoder(dev,
1753 radeon_get_encoder_id(dev,
1754 ATOM_DEVICE_TV1_SUPPORT,
1756 ATOM_DEVICE_TV1_SUPPORT);
1757 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1758 DRM_MODE_CONNECTOR_SVIDEO,
1760 CONNECTOR_OBJECT_ID_SVIDEO,
1763 case CT_IMAC_G5_ISIGHT:
1764 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1765 rdev->mode_info.connector_table);
1766 /* DVI-D - int tmds */
1767 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1768 hpd.hpd = RADEON_HPD_1; /* ??? */
1769 radeon_add_legacy_encoder(dev,
1770 radeon_get_encoder_id(dev,
1771 ATOM_DEVICE_DFP1_SUPPORT,
1773 ATOM_DEVICE_DFP1_SUPPORT);
1774 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1775 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1776 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1779 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1780 hpd.hpd = RADEON_HPD_NONE;
1781 radeon_add_legacy_encoder(dev,
1782 radeon_get_encoder_id(dev,
1783 ATOM_DEVICE_CRT2_SUPPORT,
1785 ATOM_DEVICE_CRT2_SUPPORT);
1786 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1787 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1788 CONNECTOR_OBJECT_ID_VGA,
1791 ddc_i2c.valid = false;
1792 hpd.hpd = RADEON_HPD_NONE;
1793 radeon_add_legacy_encoder(dev,
1794 radeon_get_encoder_id(dev,
1795 ATOM_DEVICE_TV1_SUPPORT,
1797 ATOM_DEVICE_TV1_SUPPORT);
1798 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1799 DRM_MODE_CONNECTOR_SVIDEO,
1801 CONNECTOR_OBJECT_ID_SVIDEO,
1805 DRM_INFO("Connector Table: %d (emac)\n",
1806 rdev->mode_info.connector_table);
1807 /* VGA - primary dac */
1808 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1809 hpd.hpd = RADEON_HPD_NONE;
1810 radeon_add_legacy_encoder(dev,
1811 radeon_get_encoder_id(dev,
1812 ATOM_DEVICE_CRT1_SUPPORT,
1814 ATOM_DEVICE_CRT1_SUPPORT);
1815 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1816 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1817 CONNECTOR_OBJECT_ID_VGA,
1820 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1821 hpd.hpd = RADEON_HPD_NONE;
1822 radeon_add_legacy_encoder(dev,
1823 radeon_get_encoder_id(dev,
1824 ATOM_DEVICE_CRT2_SUPPORT,
1826 ATOM_DEVICE_CRT2_SUPPORT);
1827 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1828 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1829 CONNECTOR_OBJECT_ID_VGA,
1832 ddc_i2c.valid = false;
1833 hpd.hpd = RADEON_HPD_NONE;
1834 radeon_add_legacy_encoder(dev,
1835 radeon_get_encoder_id(dev,
1836 ATOM_DEVICE_TV1_SUPPORT,
1838 ATOM_DEVICE_TV1_SUPPORT);
1839 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1840 DRM_MODE_CONNECTOR_SVIDEO,
1842 CONNECTOR_OBJECT_ID_SVIDEO,
1846 DRM_INFO("Connector table: %d (invalid)\n",
1847 rdev->mode_info.connector_table);
1851 radeon_link_encoder_connector(dev);
1856 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1858 enum radeon_combios_connector
1860 struct radeon_i2c_bus_rec *ddc_i2c,
1861 struct radeon_hpd *hpd)
1863 struct radeon_device *rdev = dev->dev_private;
1865 /* XPRESS DDC quirks */
1866 if ((rdev->family == CHIP_RS400 ||
1867 rdev->family == CHIP_RS480) &&
1868 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1869 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1870 else if ((rdev->family == CHIP_RS400 ||
1871 rdev->family == CHIP_RS480) &&
1872 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1873 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1874 ddc_i2c->mask_clk_mask = (0x20 << 8);
1875 ddc_i2c->mask_data_mask = 0x80;
1876 ddc_i2c->a_clk_mask = (0x20 << 8);
1877 ddc_i2c->a_data_mask = 0x80;
1878 ddc_i2c->en_clk_mask = (0x20 << 8);
1879 ddc_i2c->en_data_mask = 0x80;
1880 ddc_i2c->y_clk_mask = (0x20 << 8);
1881 ddc_i2c->y_data_mask = 0x80;
1884 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1885 if ((rdev->family >= CHIP_R300) &&
1886 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1887 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1889 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1890 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1891 if (dev->pdev->device == 0x515e &&
1892 dev->pdev->subsystem_vendor == 0x1014) {
1893 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1894 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1898 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1899 if (dev->pdev->device == 0x5159 &&
1900 dev->pdev->subsystem_vendor == 0x1002 &&
1901 dev->pdev->subsystem_device == 0x013a) {
1902 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1903 *legacy_connector = CONNECTOR_CRT_LEGACY;
1907 /* X300 card with extra non-existent DVI port */
1908 if (dev->pdev->device == 0x5B60 &&
1909 dev->pdev->subsystem_vendor == 0x17af &&
1910 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1911 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1918 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1920 /* Acer 5102 has non-existent TV port */
1921 if (dev->pdev->device == 0x5975 &&
1922 dev->pdev->subsystem_vendor == 0x1025 &&
1923 dev->pdev->subsystem_device == 0x009f)
1926 /* HP dc5750 has non-existent TV port */
1927 if (dev->pdev->device == 0x5974 &&
1928 dev->pdev->subsystem_vendor == 0x103c &&
1929 dev->pdev->subsystem_device == 0x280a)
1932 /* MSI S270 has non-existent TV port */
1933 if (dev->pdev->device == 0x5955 &&
1934 dev->pdev->subsystem_vendor == 0x1462 &&
1935 dev->pdev->subsystem_device == 0x0131)
1941 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1943 struct radeon_device *rdev = dev->dev_private;
1944 uint32_t ext_tmds_info;
1946 if (rdev->flags & RADEON_IS_IGP) {
1948 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1950 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1952 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1953 if (ext_tmds_info) {
1954 uint8_t rev = RBIOS8(ext_tmds_info);
1955 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1958 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1960 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1964 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1966 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1971 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1973 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1976 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1978 struct radeon_device *rdev = dev->dev_private;
1979 uint32_t conn_info, entry, devices;
1980 uint16_t tmp, connector_object_id;
1981 enum radeon_combios_ddc ddc_type;
1982 enum radeon_combios_connector connector;
1984 struct radeon_i2c_bus_rec ddc_i2c;
1985 struct radeon_hpd hpd;
1987 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1989 for (i = 0; i < 4; i++) {
1990 entry = conn_info + 2 + i * 2;
1992 if (!RBIOS16(entry))
1995 tmp = RBIOS16(entry);
1997 connector = (tmp >> 12) & 0xf;
1999 ddc_type = (tmp >> 8) & 0xf;
2003 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
2007 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2011 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2015 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2021 switch (connector) {
2022 case CONNECTOR_PROPRIETARY_LEGACY:
2023 case CONNECTOR_DVI_I_LEGACY:
2024 case CONNECTOR_DVI_D_LEGACY:
2025 if ((tmp >> 4) & 0x1)
2026 hpd.hpd = RADEON_HPD_2;
2028 hpd.hpd = RADEON_HPD_1;
2031 hpd.hpd = RADEON_HPD_NONE;
2035 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2039 switch (connector) {
2040 case CONNECTOR_PROPRIETARY_LEGACY:
2041 if ((tmp >> 4) & 0x1)
2042 devices = ATOM_DEVICE_DFP2_SUPPORT;
2044 devices = ATOM_DEVICE_DFP1_SUPPORT;
2045 radeon_add_legacy_encoder(dev,
2046 radeon_get_encoder_id
2049 radeon_add_legacy_connector(dev, i, devices,
2050 legacy_connector_convert
2053 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2056 case CONNECTOR_CRT_LEGACY:
2058 devices = ATOM_DEVICE_CRT2_SUPPORT;
2059 radeon_add_legacy_encoder(dev,
2060 radeon_get_encoder_id
2062 ATOM_DEVICE_CRT2_SUPPORT,
2064 ATOM_DEVICE_CRT2_SUPPORT);
2066 devices = ATOM_DEVICE_CRT1_SUPPORT;
2067 radeon_add_legacy_encoder(dev,
2068 radeon_get_encoder_id
2070 ATOM_DEVICE_CRT1_SUPPORT,
2072 ATOM_DEVICE_CRT1_SUPPORT);
2074 radeon_add_legacy_connector(dev,
2077 legacy_connector_convert
2080 CONNECTOR_OBJECT_ID_VGA,
2083 case CONNECTOR_DVI_I_LEGACY:
2086 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2087 radeon_add_legacy_encoder(dev,
2088 radeon_get_encoder_id
2090 ATOM_DEVICE_CRT2_SUPPORT,
2092 ATOM_DEVICE_CRT2_SUPPORT);
2094 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2095 radeon_add_legacy_encoder(dev,
2096 radeon_get_encoder_id
2098 ATOM_DEVICE_CRT1_SUPPORT,
2100 ATOM_DEVICE_CRT1_SUPPORT);
2102 if ((tmp >> 4) & 0x1) {
2103 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2104 radeon_add_legacy_encoder(dev,
2105 radeon_get_encoder_id
2107 ATOM_DEVICE_DFP2_SUPPORT,
2109 ATOM_DEVICE_DFP2_SUPPORT);
2110 connector_object_id = combios_check_dl_dvi(dev, 0);
2112 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2113 radeon_add_legacy_encoder(dev,
2114 radeon_get_encoder_id
2116 ATOM_DEVICE_DFP1_SUPPORT,
2118 ATOM_DEVICE_DFP1_SUPPORT);
2119 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2121 radeon_add_legacy_connector(dev,
2124 legacy_connector_convert
2127 connector_object_id,
2130 case CONNECTOR_DVI_D_LEGACY:
2131 if ((tmp >> 4) & 0x1) {
2132 devices = ATOM_DEVICE_DFP2_SUPPORT;
2133 connector_object_id = combios_check_dl_dvi(dev, 1);
2135 devices = ATOM_DEVICE_DFP1_SUPPORT;
2136 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2138 radeon_add_legacy_encoder(dev,
2139 radeon_get_encoder_id
2142 radeon_add_legacy_connector(dev, i, devices,
2143 legacy_connector_convert
2146 connector_object_id,
2149 case CONNECTOR_CTV_LEGACY:
2150 case CONNECTOR_STV_LEGACY:
2151 radeon_add_legacy_encoder(dev,
2152 radeon_get_encoder_id
2154 ATOM_DEVICE_TV1_SUPPORT,
2156 ATOM_DEVICE_TV1_SUPPORT);
2157 radeon_add_legacy_connector(dev, i,
2158 ATOM_DEVICE_TV1_SUPPORT,
2159 legacy_connector_convert
2162 CONNECTOR_OBJECT_ID_SVIDEO,
2166 DRM_ERROR("Unknown connector type: %d\n",
2173 uint16_t tmds_info =
2174 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2176 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2178 radeon_add_legacy_encoder(dev,
2179 radeon_get_encoder_id(dev,
2180 ATOM_DEVICE_CRT1_SUPPORT,
2182 ATOM_DEVICE_CRT1_SUPPORT);
2183 radeon_add_legacy_encoder(dev,
2184 radeon_get_encoder_id(dev,
2185 ATOM_DEVICE_DFP1_SUPPORT,
2187 ATOM_DEVICE_DFP1_SUPPORT);
2189 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2190 hpd.hpd = RADEON_HPD_NONE;
2191 radeon_add_legacy_connector(dev,
2193 ATOM_DEVICE_CRT1_SUPPORT |
2194 ATOM_DEVICE_DFP1_SUPPORT,
2195 DRM_MODE_CONNECTOR_DVII,
2197 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2201 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2202 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2204 radeon_add_legacy_encoder(dev,
2205 radeon_get_encoder_id(dev,
2206 ATOM_DEVICE_CRT1_SUPPORT,
2208 ATOM_DEVICE_CRT1_SUPPORT);
2209 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2210 hpd.hpd = RADEON_HPD_NONE;
2211 radeon_add_legacy_connector(dev,
2213 ATOM_DEVICE_CRT1_SUPPORT,
2214 DRM_MODE_CONNECTOR_VGA,
2216 CONNECTOR_OBJECT_ID_VGA,
2219 DRM_DEBUG("No connector info found\n");
2225 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2227 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2229 uint16_t lcd_ddc_info =
2230 combios_get_table_offset(dev,
2231 COMBIOS_LCD_DDC_INFO_TABLE);
2233 radeon_add_legacy_encoder(dev,
2234 radeon_get_encoder_id(dev,
2235 ATOM_DEVICE_LCD1_SUPPORT,
2237 ATOM_DEVICE_LCD1_SUPPORT);
2240 ddc_type = RBIOS8(lcd_ddc_info + 2);
2244 combios_setup_i2c_bus
2245 (rdev, RADEON_GPIO_MONID);
2249 combios_setup_i2c_bus
2250 (rdev, RADEON_GPIO_DVI_DDC);
2254 combios_setup_i2c_bus
2255 (rdev, RADEON_GPIO_VGA_DDC);
2259 combios_setup_i2c_bus
2260 (rdev, RADEON_GPIO_CRT2_DDC);
2264 combios_setup_i2c_bus
2265 (rdev, RADEON_GPIOPAD_MASK);
2266 ddc_i2c.mask_clk_mask =
2267 RBIOS32(lcd_ddc_info + 3);
2268 ddc_i2c.mask_data_mask =
2269 RBIOS32(lcd_ddc_info + 7);
2270 ddc_i2c.a_clk_mask =
2271 RBIOS32(lcd_ddc_info + 3);
2272 ddc_i2c.a_data_mask =
2273 RBIOS32(lcd_ddc_info + 7);
2274 ddc_i2c.en_clk_mask =
2275 RBIOS32(lcd_ddc_info + 3);
2276 ddc_i2c.en_data_mask =
2277 RBIOS32(lcd_ddc_info + 7);
2278 ddc_i2c.y_clk_mask =
2279 RBIOS32(lcd_ddc_info + 3);
2280 ddc_i2c.y_data_mask =
2281 RBIOS32(lcd_ddc_info + 7);
2285 combios_setup_i2c_bus
2286 (rdev, RADEON_MDGPIO_MASK);
2287 ddc_i2c.mask_clk_mask =
2288 RBIOS32(lcd_ddc_info + 3);
2289 ddc_i2c.mask_data_mask =
2290 RBIOS32(lcd_ddc_info + 7);
2291 ddc_i2c.a_clk_mask =
2292 RBIOS32(lcd_ddc_info + 3);
2293 ddc_i2c.a_data_mask =
2294 RBIOS32(lcd_ddc_info + 7);
2295 ddc_i2c.en_clk_mask =
2296 RBIOS32(lcd_ddc_info + 3);
2297 ddc_i2c.en_data_mask =
2298 RBIOS32(lcd_ddc_info + 7);
2299 ddc_i2c.y_clk_mask =
2300 RBIOS32(lcd_ddc_info + 3);
2301 ddc_i2c.y_data_mask =
2302 RBIOS32(lcd_ddc_info + 7);
2305 ddc_i2c.valid = false;
2308 DRM_DEBUG("LCD DDC Info Table found!\n");
2310 ddc_i2c.valid = false;
2312 hpd.hpd = RADEON_HPD_NONE;
2313 radeon_add_legacy_connector(dev,
2315 ATOM_DEVICE_LCD1_SUPPORT,
2316 DRM_MODE_CONNECTOR_LVDS,
2318 CONNECTOR_OBJECT_ID_LVDS,
2323 /* check TV table */
2324 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2326 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2328 if (RBIOS8(tv_info + 6) == 'T') {
2329 if (radeon_apply_legacy_tv_quirks(dev)) {
2330 hpd.hpd = RADEON_HPD_NONE;
2331 radeon_add_legacy_encoder(dev,
2332 radeon_get_encoder_id
2334 ATOM_DEVICE_TV1_SUPPORT,
2336 ATOM_DEVICE_TV1_SUPPORT);
2337 radeon_add_legacy_connector(dev, 6,
2338 ATOM_DEVICE_TV1_SUPPORT,
2339 DRM_MODE_CONNECTOR_SVIDEO,
2341 CONNECTOR_OBJECT_ID_SVIDEO,
2348 radeon_link_encoder_connector(dev);
2353 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2355 struct drm_device *dev = rdev->ddev;
2356 u16 offset, misc, misc2 = 0;
2357 u8 rev, blocks, tmp;
2358 int state_index = 0;
2360 rdev->pm.default_power_state = NULL;
2362 if (rdev->flags & RADEON_IS_MOBILITY) {
2363 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2365 rev = RBIOS8(offset);
2366 blocks = RBIOS8(offset + 0x2);
2367 /* power mode 0 tends to be the only valid one */
2368 rdev->pm.power_state[state_index].num_clock_modes = 1;
2369 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2370 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2371 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2372 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2374 /* skip overclock modes for now */
2375 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
2376 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
2377 (rdev->pm.power_state[state_index].clock_info[0].sclk >
2378 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
2380 rdev->pm.power_state[state_index].type =
2381 POWER_STATE_TYPE_BATTERY;
2382 misc = RBIOS16(offset + 0x5 + 0x0);
2384 misc2 = RBIOS16(offset + 0x5 + 0xe);
2386 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2388 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2391 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2393 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2395 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2396 RBIOS16(offset + 0x5 + 0xb) * 4;
2397 tmp = RBIOS8(offset + 0x5 + 0xd);
2398 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2400 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2401 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2402 if (entries && voltage_table_offset) {
2403 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2404 RBIOS16(voltage_table_offset) * 4;
2405 tmp = RBIOS8(voltage_table_offset + 0x2);
2406 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2408 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2410 switch ((misc2 & 0x700) >> 8) {
2413 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2416 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2419 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2422 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2425 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2429 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2431 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
2432 RBIOS8(offset + 0x5 + 0x10);
2435 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2438 /* XXX figure out some good default low power mode for desktop cards */
2442 /* add the default mode */
2443 rdev->pm.power_state[state_index].type =
2444 POWER_STATE_TYPE_DEFAULT;
2445 rdev->pm.power_state[state_index].num_clock_modes = 1;
2446 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2447 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2448 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2449 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2450 if (rdev->asic->get_pcie_lanes)
2451 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
2453 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
2454 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
2455 rdev->pm.num_power_states = state_index + 1;
2457 rdev->pm.current_power_state = rdev->pm.default_power_state;
2458 rdev->pm.current_clock_mode =
2459 rdev->pm.default_power_state->default_clock_mode;
2462 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2464 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2465 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2470 switch (tmds->dvo_chip) {
2473 radeon_i2c_put_byte(tmds->i2c_bus,
2476 radeon_i2c_put_byte(tmds->i2c_bus,
2479 radeon_i2c_put_byte(tmds->i2c_bus,
2482 radeon_i2c_put_byte(tmds->i2c_bus,
2485 radeon_i2c_put_byte(tmds->i2c_bus,
2490 /* sil 1178 - untested */
2509 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2511 struct drm_device *dev = encoder->dev;
2512 struct radeon_device *rdev = dev->dev_private;
2513 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2515 uint8_t blocks, slave_addr, rev;
2517 uint32_t reg, val, and_mask, or_mask;
2518 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2523 if (rdev->flags & RADEON_IS_IGP) {
2524 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2525 rev = RBIOS8(offset);
2527 rev = RBIOS8(offset);
2529 blocks = RBIOS8(offset + 3);
2531 while (blocks > 0) {
2532 id = RBIOS16(index);
2536 reg = (id & 0x1fff) * 4;
2537 val = RBIOS32(index);
2542 reg = (id & 0x1fff) * 4;
2543 and_mask = RBIOS32(index);
2545 or_mask = RBIOS32(index);
2548 val = (val & and_mask) | or_mask;
2552 val = RBIOS16(index);
2557 val = RBIOS16(index);
2562 slave_addr = id & 0xff;
2563 slave_addr >>= 1; /* 7 bit addressing */
2565 reg = RBIOS8(index);
2567 val = RBIOS8(index);
2569 radeon_i2c_put_byte(tmds->i2c_bus,
2574 DRM_ERROR("Unknown id %d\n", id >> 13);
2583 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2585 index = offset + 10;
2586 id = RBIOS16(index);
2587 while (id != 0xffff) {
2591 reg = (id & 0x1fff) * 4;
2592 val = RBIOS32(index);
2596 reg = (id & 0x1fff) * 4;
2597 and_mask = RBIOS32(index);
2599 or_mask = RBIOS32(index);
2602 val = (val & and_mask) | or_mask;
2606 val = RBIOS16(index);
2612 and_mask = RBIOS32(index);
2614 or_mask = RBIOS32(index);
2616 val = RREG32_PLL(reg);
2617 val = (val & and_mask) | or_mask;
2618 WREG32_PLL(reg, val);
2622 val = RBIOS8(index);
2624 radeon_i2c_put_byte(tmds->i2c_bus,
2629 DRM_ERROR("Unknown id %d\n", id >> 13);
2632 id = RBIOS16(index);
2640 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2642 struct radeon_device *rdev = dev->dev_private;
2645 while (RBIOS16(offset)) {
2646 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2647 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2648 uint32_t val, and_mask, or_mask;
2654 val = RBIOS32(offset);
2659 val = RBIOS32(offset);
2664 and_mask = RBIOS32(offset);
2666 or_mask = RBIOS32(offset);
2674 and_mask = RBIOS32(offset);
2676 or_mask = RBIOS32(offset);
2684 val = RBIOS16(offset);
2689 val = RBIOS16(offset);
2696 (RADEON_CLK_PWRMGT_CNTL) &
2703 if ((RREG32(RADEON_MC_STATUS) &
2719 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2721 struct radeon_device *rdev = dev->dev_private;
2724 while (RBIOS8(offset)) {
2725 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2726 uint8_t addr = (RBIOS8(offset) & 0x3f);
2727 uint32_t val, shift, tmp;
2728 uint32_t and_mask, or_mask;
2733 val = RBIOS32(offset);
2735 WREG32_PLL(addr, val);
2738 shift = RBIOS8(offset) * 8;
2740 and_mask = RBIOS8(offset) << shift;
2741 and_mask |= ~(0xff << shift);
2743 or_mask = RBIOS8(offset) << shift;
2745 tmp = RREG32_PLL(addr);
2748 WREG32_PLL(addr, tmp);
2764 (RADEON_CLK_PWRMGT_CNTL) &
2772 (RADEON_CLK_PWRMGT_CNTL) &
2779 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2780 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2782 uint32_t mclk_cntl =
2785 mclk_cntl &= 0xffff0000;
2786 /*mclk_cntl |= 0x00001111;*//* ??? */
2787 WREG32_PLL(RADEON_MCLK_CNTL,
2792 (RADEON_CLK_PWRMGT_CNTL,
2794 ~RADEON_CG_NO1_DEBUG_0);
2809 static void combios_parse_ram_reset_table(struct drm_device *dev,
2812 struct radeon_device *rdev = dev->dev_private;
2816 uint8_t val = RBIOS8(offset);
2817 while (val != 0xff) {
2821 uint32_t channel_complete_mask;
2823 if (ASIC_IS_R300(rdev))
2824 channel_complete_mask =
2825 R300_MEM_PWRUP_COMPLETE;
2827 channel_complete_mask =
2828 RADEON_MEM_PWRUP_COMPLETE;
2831 if ((RREG32(RADEON_MEM_STR_CNTL) &
2832 channel_complete_mask) ==
2833 channel_complete_mask)
2837 uint32_t or_mask = RBIOS16(offset);
2840 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2841 tmp &= RADEON_SDRAM_MODE_MASK;
2843 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2845 or_mask = val << 24;
2846 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2847 tmp &= RADEON_B3MEM_RESET_MASK;
2849 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2851 val = RBIOS8(offset);
2856 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2857 int mem_addr_mapping)
2859 struct radeon_device *rdev = dev->dev_private;
2864 mem_cntl = RREG32(RADEON_MEM_CNTL);
2865 if (mem_cntl & RV100_HALF_MODE)
2868 mem_cntl &= ~(0xff << 8);
2869 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2870 WREG32(RADEON_MEM_CNTL, mem_cntl);
2871 RREG32(RADEON_MEM_CNTL);
2875 /* something like this???? */
2877 addr = ram * 1024 * 1024;
2878 /* write to each page */
2879 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2880 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2881 /* read back and verify */
2882 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2883 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2890 static void combios_write_ram_size(struct drm_device *dev)
2892 struct radeon_device *rdev = dev->dev_private;
2895 uint32_t mem_size = 0;
2896 uint32_t mem_cntl = 0;
2898 /* should do something smarter here I guess... */
2899 if (rdev->flags & RADEON_IS_IGP)
2902 /* first check detected mem table */
2903 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2905 rev = RBIOS8(offset);
2907 mem_cntl = RBIOS32(offset + 1);
2908 mem_size = RBIOS16(offset + 5);
2909 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2910 ((dev->pdev->device != 0x515e)
2911 && (dev->pdev->device != 0x5969)))
2912 WREG32(RADEON_MEM_CNTL, mem_cntl);
2918 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2920 rev = RBIOS8(offset - 1);
2922 if (((rdev->flags & RADEON_FAMILY_MASK) <
2924 && ((dev->pdev->device != 0x515e)
2925 && (dev->pdev->device != 0x5969))) {
2927 int mem_addr_mapping = 0;
2929 while (RBIOS8(offset)) {
2930 ram = RBIOS8(offset);
2933 if (mem_addr_mapping != 0x25)
2936 combios_detect_ram(dev, ram,
2943 mem_size = RBIOS8(offset);
2945 mem_size = RBIOS8(offset);
2946 mem_size *= 2; /* convert to MB */
2951 mem_size *= (1024 * 1024); /* convert to bytes */
2952 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2955 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2957 uint16_t dyn_clk_info =
2958 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2961 combios_parse_pll_table(dev, dyn_clk_info);
2964 void radeon_combios_asic_init(struct drm_device *dev)
2966 struct radeon_device *rdev = dev->dev_private;
2969 /* port hardcoded mac stuff from radeonfb */
2970 if (rdev->bios == NULL)
2974 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2976 combios_parse_mmio_table(dev, table);
2979 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2981 combios_parse_pll_table(dev, table);
2984 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2986 combios_parse_mmio_table(dev, table);
2988 if (!(rdev->flags & RADEON_IS_IGP)) {
2991 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2993 combios_parse_mmio_table(dev, table);
2996 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2998 combios_parse_ram_reset_table(dev, table);
3002 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3004 combios_parse_mmio_table(dev, table);
3006 /* write CONFIG_MEMSIZE */
3007 combios_write_ram_size(dev);
3011 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3013 combios_parse_pll_table(dev, table);
3017 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3019 struct radeon_device *rdev = dev->dev_private;
3020 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3022 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3023 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3024 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3026 /* let the bios control the backlight */
3027 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3029 /* tell the bios not to handle mode switching */
3030 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3031 RADEON_ACC_MODE_CHANGE);
3033 /* tell the bios a driver is loaded */
3034 bios_7_scratch |= RADEON_DRV_LOADED;
3036 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3037 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3038 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3041 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3043 struct drm_device *dev = encoder->dev;
3044 struct radeon_device *rdev = dev->dev_private;
3045 uint32_t bios_6_scratch;
3047 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3050 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3052 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3054 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3058 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3059 struct drm_encoder *encoder,
3062 struct drm_device *dev = connector->dev;
3063 struct radeon_device *rdev = dev->dev_private;
3064 struct radeon_connector *radeon_connector =
3065 to_radeon_connector(connector);
3066 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3067 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3068 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3070 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3071 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3073 DRM_DEBUG("TV1 connected\n");
3075 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3076 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3077 bios_5_scratch |= RADEON_TV1_ON;
3078 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3080 DRM_DEBUG("TV1 disconnected\n");
3081 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3082 bios_5_scratch &= ~RADEON_TV1_ON;
3083 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3086 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3087 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3089 DRM_DEBUG("LCD1 connected\n");
3090 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3091 bios_5_scratch |= RADEON_LCD1_ON;
3092 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3094 DRM_DEBUG("LCD1 disconnected\n");
3095 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3096 bios_5_scratch &= ~RADEON_LCD1_ON;
3097 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3100 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3101 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3103 DRM_DEBUG("CRT1 connected\n");
3104 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3105 bios_5_scratch |= RADEON_CRT1_ON;
3106 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3108 DRM_DEBUG("CRT1 disconnected\n");
3109 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3110 bios_5_scratch &= ~RADEON_CRT1_ON;
3111 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3114 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3115 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3117 DRM_DEBUG("CRT2 connected\n");
3118 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3119 bios_5_scratch |= RADEON_CRT2_ON;
3120 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3122 DRM_DEBUG("CRT2 disconnected\n");
3123 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3124 bios_5_scratch &= ~RADEON_CRT2_ON;
3125 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3128 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3129 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3131 DRM_DEBUG("DFP1 connected\n");
3132 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3133 bios_5_scratch |= RADEON_DFP1_ON;
3134 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3136 DRM_DEBUG("DFP1 disconnected\n");
3137 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3138 bios_5_scratch &= ~RADEON_DFP1_ON;
3139 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3142 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3143 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3145 DRM_DEBUG("DFP2 connected\n");
3146 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3147 bios_5_scratch |= RADEON_DFP2_ON;
3148 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3150 DRM_DEBUG("DFP2 disconnected\n");
3151 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3152 bios_5_scratch &= ~RADEON_DFP2_ON;
3153 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3156 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3157 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3161 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3163 struct drm_device *dev = encoder->dev;
3164 struct radeon_device *rdev = dev->dev_private;
3165 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3166 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3168 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3169 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3170 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3172 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3173 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3174 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3176 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3177 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3178 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3180 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3181 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3182 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3184 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3185 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3186 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3188 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3189 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3190 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3192 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3196 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3198 struct drm_device *dev = encoder->dev;
3199 struct radeon_device *rdev = dev->dev_private;
3200 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3201 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3203 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3205 bios_6_scratch |= RADEON_TV_DPMS_ON;
3207 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3209 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3211 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3213 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3215 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3217 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3219 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3221 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3223 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3225 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3227 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);