2 * Moorestown platform Langwell chip GPIO driver
4 * Copyright (c) 2008 - 2009, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * Moorestown platform Langwell chip.
22 * Medfield platform Penwell chip.
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/kernel.h>
30 #include <linux/delay.h>
31 #include <linux/stddef.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/irq.h>
36 #include <linux/gpio.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
41 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
42 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
43 * registers to control them, so we only define the order here instead of a
44 * structure, to get a bit offset for a pin (use GPDR as an example):
49 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
51 * so the bit of reg_addr is to control pin offset's GPDR feature
55 GPLR = 0, /* pin level read-only */
56 GPDR, /* pin direction */
59 GRER, /* rising edge detect */
60 GFER, /* falling edge detect */
61 GEDR, /* edge detect result */
65 struct gpio_chip chip;
72 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
73 enum GPIO_REG reg_type)
75 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
76 unsigned nreg = chip->ngpio / 32;
80 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
84 static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
86 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
88 return readl(gplr) & BIT(offset % 32);
91 static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
93 void __iomem *gpsr, *gpcr;
96 gpsr = gpio_reg(chip, offset, GPSR);
97 writel(BIT(offset % 32), gpsr);
99 gpcr = gpio_reg(chip, offset, GPCR);
100 writel(BIT(offset % 32), gpcr);
104 static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
106 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
107 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
112 pm_runtime_get(&lnw->pdev->dev);
114 spin_lock_irqsave(&lnw->lock, flags);
116 value &= ~BIT(offset % 32);
118 spin_unlock_irqrestore(&lnw->lock, flags);
121 pm_runtime_put(&lnw->pdev->dev);
126 static int lnw_gpio_direction_output(struct gpio_chip *chip,
127 unsigned offset, int value)
129 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
130 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
133 lnw_gpio_set(chip, offset, value);
136 pm_runtime_get(&lnw->pdev->dev);
138 spin_lock_irqsave(&lnw->lock, flags);
140 value |= BIT(offset % 32);
142 spin_unlock_irqrestore(&lnw->lock, flags);
145 pm_runtime_put(&lnw->pdev->dev);
150 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
152 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
153 return lnw->irq_base + offset;
156 static int lnw_irq_type(struct irq_data *d, unsigned type)
158 struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
159 u32 gpio = d->irq - lnw->irq_base;
162 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
163 void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
165 if (gpio >= lnw->chip.ngpio)
169 pm_runtime_get(&lnw->pdev->dev);
171 spin_lock_irqsave(&lnw->lock, flags);
172 if (type & IRQ_TYPE_EDGE_RISING)
173 value = readl(grer) | BIT(gpio % 32);
175 value = readl(grer) & (~BIT(gpio % 32));
178 if (type & IRQ_TYPE_EDGE_FALLING)
179 value = readl(gfer) | BIT(gpio % 32);
181 value = readl(gfer) & (~BIT(gpio % 32));
183 spin_unlock_irqrestore(&lnw->lock, flags);
186 pm_runtime_put(&lnw->pdev->dev);
191 static void lnw_irq_unmask(struct irq_data *d)
195 static void lnw_irq_mask(struct irq_data *d)
199 static struct irq_chip lnw_irqchip = {
201 .irq_mask = lnw_irq_mask,
202 .irq_unmask = lnw_irq_unmask,
203 .irq_set_type = lnw_irq_type,
206 static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
207 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
208 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
209 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
212 MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
214 static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
216 struct irq_data *data = irq_desc_get_irq_data(desc);
217 struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
218 struct irq_chip *chip = irq_data_get_irq_chip(data);
219 u32 base, gpio, mask;
220 unsigned long pending;
223 /* check GPIO controller to check which pin triggered the interrupt */
224 for (base = 0; base < lnw->chip.ngpio; base += 32) {
225 gedr = gpio_reg(&lnw->chip, base, GEDR);
226 pending = readl(gedr);
228 gpio = __ffs(pending);
231 /* Clear before handling so we can't lose an edge */
233 generic_handle_irq(lnw->irq_base + base + gpio);
241 static int lnw_gpio_runtime_resume(struct device *dev)
246 static int lnw_gpio_runtime_suspend(struct device *dev)
251 static int lnw_gpio_runtime_idle(struct device *dev)
253 int err = pm_schedule_suspend(dev, 500);
262 #define lnw_gpio_runtime_suspend NULL
263 #define lnw_gpio_runtime_resume NULL
264 #define lnw_gpio_runtime_idle NULL
267 static const struct dev_pm_ops lnw_gpio_pm_ops = {
268 .runtime_suspend = lnw_gpio_runtime_suspend,
269 .runtime_resume = lnw_gpio_runtime_resume,
270 .runtime_idle = lnw_gpio_runtime_idle,
273 static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
274 const struct pci_device_id *id)
278 resource_size_t start, len;
279 struct lnw_gpio *lnw;
284 retval = pci_enable_device(pdev);
288 retval = pci_request_regions(pdev, "langwell_gpio");
290 dev_err(&pdev->dev, "error requesting resources\n");
293 /* get the irq_base from bar1 */
294 start = pci_resource_start(pdev, 1);
295 len = pci_resource_len(pdev, 1);
296 base = ioremap_nocache(start, len);
298 dev_err(&pdev->dev, "error mapping bar1\n");
301 irq_base = *(u32 *)base;
302 gpio_base = *((u32 *)base + 1);
303 /* release the IO mapping, since we already get the info from bar1 */
305 /* get the register base from bar0 */
306 start = pci_resource_start(pdev, 0);
307 len = pci_resource_len(pdev, 0);
308 base = ioremap_nocache(start, len);
310 dev_err(&pdev->dev, "error mapping bar0\n");
315 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
317 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
321 lnw->reg_base = base;
322 lnw->irq_base = irq_base;
323 lnw->chip.label = dev_name(&pdev->dev);
324 lnw->chip.direction_input = lnw_gpio_direction_input;
325 lnw->chip.direction_output = lnw_gpio_direction_output;
326 lnw->chip.get = lnw_gpio_get;
327 lnw->chip.set = lnw_gpio_set;
328 lnw->chip.to_irq = lnw_gpio_to_irq;
329 lnw->chip.base = gpio_base;
330 lnw->chip.ngpio = id->driver_data;
331 lnw->chip.can_sleep = 0;
333 pci_set_drvdata(pdev, lnw);
334 retval = gpiochip_add(&lnw->chip);
336 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
339 irq_set_handler_data(pdev->irq, lnw);
340 irq_set_chained_handler(pdev->irq, lnw_irq_handler);
341 for (i = 0; i < lnw->chip.ngpio; i++) {
342 irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
343 handle_simple_irq, "demux");
344 irq_set_chip_data(i + lnw->irq_base, lnw);
347 spin_lock_init(&lnw->lock);
349 pm_runtime_put_noidle(&pdev->dev);
350 pm_runtime_allow(&pdev->dev);
358 pci_release_regions(pdev);
360 pci_disable_device(pdev);
365 static struct pci_driver lnw_gpio_driver = {
366 .name = "langwell_gpio",
367 .id_table = lnw_gpio_ids,
368 .probe = lnw_gpio_probe,
370 .pm = &lnw_gpio_pm_ops,
375 static int __devinit wp_gpio_probe(struct platform_device *pdev)
377 struct lnw_gpio *lnw;
378 struct gpio_chip *gc;
382 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
386 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
389 "can't allocate whitneypoint_gpio chip data\n");
392 lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
393 if (lnw->reg_base == NULL) {
397 spin_lock_init(&lnw->lock);
399 gc->label = dev_name(&pdev->dev);
400 gc->owner = THIS_MODULE;
401 gc->direction_input = lnw_gpio_direction_input;
402 gc->direction_output = lnw_gpio_direction_output;
403 gc->get = lnw_gpio_get;
404 gc->set = lnw_gpio_set;
409 retval = gpiochip_add(gc);
411 dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
415 platform_set_drvdata(pdev, lnw);
418 iounmap(lnw->reg_base);
424 static int __devexit wp_gpio_remove(struct platform_device *pdev)
426 struct lnw_gpio *lnw = platform_get_drvdata(pdev);
428 err = gpiochip_remove(&lnw->chip);
430 dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
431 iounmap(lnw->reg_base);
433 platform_set_drvdata(pdev, NULL);
437 static struct platform_driver wp_gpio_driver = {
438 .probe = wp_gpio_probe,
439 .remove = __devexit_p(wp_gpio_remove),
442 .owner = THIS_MODULE,
446 static int __init lnw_gpio_init(void)
449 ret = pci_register_driver(&lnw_gpio_driver);
452 ret = platform_driver_register(&wp_gpio_driver);
454 pci_unregister_driver(&lnw_gpio_driver);
458 device_initcall(lnw_gpio_init);