1 /* linux/arch/arm/mach-exynos4/mct.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 MCT(Multi-Core Timer) support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/percpu.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_address.h>
25 #include <linux/clocksource.h>
27 #include <asm/arch_timer.h>
28 #include <asm/localtimer.h>
33 #include <mach/irqs.h>
34 #include <asm/mach/time.h>
36 #define EXYNOS4_MCTREG(x) (x)
37 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
38 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
39 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
40 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
41 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
42 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
43 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
44 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
45 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
46 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
47 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
48 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
49 #define EXYNOS4_MCT_L_MASK (0xffffff00)
51 #define MCT_L_TCNTB_OFFSET (0x00)
52 #define MCT_L_ICNTB_OFFSET (0x08)
53 #define MCT_L_TCON_OFFSET (0x20)
54 #define MCT_L_INT_CSTAT_OFFSET (0x30)
55 #define MCT_L_INT_ENB_OFFSET (0x34)
56 #define MCT_L_WSTAT_OFFSET (0x40)
57 #define MCT_G_TCON_START (1 << 8)
58 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
59 #define MCT_G_TCON_COMP0_ENABLE (1 << 0)
60 #define MCT_L_TCON_INTERVAL_MODE (1 << 2)
61 #define MCT_L_TCON_INT_START (1 << 1)
62 #define MCT_L_TCON_TIMER_START (1 << 0)
64 #define TICK_BASE_CNT 1
83 static void __iomem *reg_base;
84 static unsigned long clk_rate;
85 static unsigned int mct_int_type;
86 static int mct_irqs[MCT_NR_IRQS];
88 struct mct_clock_event_device {
89 struct clock_event_device *evt;
94 static void exynos4_mct_write(unsigned int value, unsigned long offset)
96 unsigned long stat_addr;
100 __raw_writel(value, reg_base + offset);
102 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
103 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
104 switch (offset & EXYNOS4_MCT_L_MASK) {
105 case MCT_L_TCON_OFFSET:
106 mask = 1 << 3; /* L_TCON write status */
108 case MCT_L_ICNTB_OFFSET:
109 mask = 1 << 1; /* L_ICNTB write status */
111 case MCT_L_TCNTB_OFFSET:
112 mask = 1 << 0; /* L_TCNTB write status */
119 case EXYNOS4_MCT_G_TCON:
120 stat_addr = EXYNOS4_MCT_G_WSTAT;
121 mask = 1 << 16; /* G_TCON write status */
123 case EXYNOS4_MCT_G_COMP0_L:
124 stat_addr = EXYNOS4_MCT_G_WSTAT;
125 mask = 1 << 0; /* G_COMP0_L write status */
127 case EXYNOS4_MCT_G_COMP0_U:
128 stat_addr = EXYNOS4_MCT_G_WSTAT;
129 mask = 1 << 1; /* G_COMP0_U write status */
131 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
132 stat_addr = EXYNOS4_MCT_G_WSTAT;
133 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
135 case EXYNOS4_MCT_G_CNT_L:
136 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
137 mask = 1 << 0; /* G_CNT_L write status */
139 case EXYNOS4_MCT_G_CNT_U:
140 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
141 mask = 1 << 1; /* G_CNT_U write status */
148 /* Wait maximum 1 ms until written values are applied */
149 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
150 if (__raw_readl(reg_base + stat_addr) & mask) {
151 __raw_writel(mask, reg_base + stat_addr);
155 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
158 /* Clocksource handling */
159 static void exynos4_mct_frc_start(u32 hi, u32 lo)
163 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
164 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
166 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
167 reg |= MCT_G_TCON_START;
168 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
171 static cycle_t exynos4_frc_read(struct clocksource *cs)
174 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
178 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
179 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
182 return ((cycle_t)hi << 32) | lo;
185 static void exynos4_frc_resume(struct clocksource *cs)
187 exynos4_mct_frc_start(0, 0);
190 struct clocksource mct_frc = {
193 .read = exynos4_frc_read,
194 .mask = CLOCKSOURCE_MASK(64),
195 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
196 .resume = exynos4_frc_resume,
199 static void __init exynos4_clocksource_init(void)
201 exynos4_mct_frc_start(0, 0);
203 if (clocksource_register_hz(&mct_frc, clk_rate))
204 panic("%s: can't register clocksource\n", mct_frc.name);
207 static void exynos4_mct_comp0_stop(void)
211 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
212 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
214 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
215 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
218 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
219 unsigned long cycles)
224 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
226 if (mode == CLOCK_EVT_MODE_PERIODIC) {
227 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
228 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
231 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
232 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
233 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
235 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
237 tcon |= MCT_G_TCON_COMP0_ENABLE;
238 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
241 static int exynos4_comp_set_next_event(unsigned long cycles,
242 struct clock_event_device *evt)
244 exynos4_mct_comp0_start(evt->mode, cycles);
249 static void exynos4_comp_set_mode(enum clock_event_mode mode,
250 struct clock_event_device *evt)
252 unsigned long cycles_per_jiffy;
253 exynos4_mct_comp0_stop();
256 case CLOCK_EVT_MODE_PERIODIC:
258 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
259 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
262 case CLOCK_EVT_MODE_ONESHOT:
263 case CLOCK_EVT_MODE_UNUSED:
264 case CLOCK_EVT_MODE_SHUTDOWN:
265 case CLOCK_EVT_MODE_RESUME:
270 static struct clock_event_device mct_comp_device = {
272 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
274 .set_next_event = exynos4_comp_set_next_event,
275 .set_mode = exynos4_comp_set_mode,
278 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
280 struct clock_event_device *evt = dev_id;
282 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
284 evt->event_handler(evt);
289 static struct irqaction mct_comp_event_irq = {
290 .name = "mct_comp_irq",
291 .flags = IRQF_TIMER | IRQF_IRQPOLL,
292 .handler = exynos4_mct_comp_isr,
293 .dev_id = &mct_comp_device,
296 static void exynos4_clockevent_init(void)
298 mct_comp_device.cpumask = cpumask_of(0);
299 clockevents_config_and_register(&mct_comp_device, clk_rate,
301 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
304 #ifdef CONFIG_LOCAL_TIMERS
306 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
308 /* Clock event handling */
309 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
312 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
313 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
315 tmp = __raw_readl(reg_base + offset);
318 exynos4_mct_write(tmp, offset);
322 static void exynos4_mct_tick_start(unsigned long cycles,
323 struct mct_clock_event_device *mevt)
327 exynos4_mct_tick_stop(mevt);
329 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
331 /* update interrupt count buffer */
332 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
334 /* enable MCT tick interrupt */
335 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
337 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
338 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
339 MCT_L_TCON_INTERVAL_MODE;
340 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
343 static int exynos4_tick_set_next_event(unsigned long cycles,
344 struct clock_event_device *evt)
346 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
348 exynos4_mct_tick_start(cycles, mevt);
353 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
354 struct clock_event_device *evt)
356 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
357 unsigned long cycles_per_jiffy;
359 exynos4_mct_tick_stop(mevt);
362 case CLOCK_EVT_MODE_PERIODIC:
364 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
365 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
368 case CLOCK_EVT_MODE_ONESHOT:
369 case CLOCK_EVT_MODE_UNUSED:
370 case CLOCK_EVT_MODE_SHUTDOWN:
371 case CLOCK_EVT_MODE_RESUME:
376 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
378 struct clock_event_device *evt = mevt->evt;
381 * This is for supporting oneshot mode.
382 * Mct would generate interrupt periodically
383 * without explicit stopping.
385 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
386 exynos4_mct_tick_stop(mevt);
388 /* Clear the MCT tick interrupt */
389 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
390 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
397 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
399 struct mct_clock_event_device *mevt = dev_id;
400 struct clock_event_device *evt = mevt->evt;
402 exynos4_mct_tick_clear(mevt);
404 evt->event_handler(evt);
409 static struct irqaction mct_tick0_event_irq = {
410 .name = "mct_tick0_irq",
411 .flags = IRQF_TIMER | IRQF_NOBALANCING,
412 .handler = exynos4_mct_tick_isr,
415 static struct irqaction mct_tick1_event_irq = {
416 .name = "mct_tick1_irq",
417 .flags = IRQF_TIMER | IRQF_NOBALANCING,
418 .handler = exynos4_mct_tick_isr,
421 static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
423 struct mct_clock_event_device *mevt;
424 unsigned int cpu = smp_processor_id();
426 mevt = this_cpu_ptr(&percpu_mct_tick);
429 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
430 sprintf(mevt->name, "mct_tick%d", cpu);
432 evt->name = mevt->name;
433 evt->cpumask = cpumask_of(cpu);
434 evt->set_next_event = exynos4_tick_set_next_event;
435 evt->set_mode = exynos4_tick_set_mode;
436 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
438 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
441 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
443 if (mct_int_type == MCT_INT_SPI) {
445 mct_tick0_event_irq.dev_id = mevt;
446 evt->irq = mct_irqs[MCT_L0_IRQ];
447 setup_irq(evt->irq, &mct_tick0_event_irq);
449 mct_tick1_event_irq.dev_id = mevt;
450 evt->irq = mct_irqs[MCT_L1_IRQ];
451 setup_irq(evt->irq, &mct_tick1_event_irq);
452 irq_set_affinity(evt->irq, cpumask_of(1));
455 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
461 static void exynos4_local_timer_stop(struct clock_event_device *evt)
463 unsigned int cpu = smp_processor_id();
464 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
465 if (mct_int_type == MCT_INT_SPI)
467 remove_irq(evt->irq, &mct_tick0_event_irq);
469 remove_irq(evt->irq, &mct_tick1_event_irq);
471 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
474 static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
475 .setup = exynos4_local_timer_setup,
476 .stop = exynos4_local_timer_stop,
478 #endif /* CONFIG_LOCAL_TIMERS */
480 static void __init exynos4_timer_resources(void __iomem *base)
483 mct_clk = clk_get(NULL, "xtal");
485 clk_rate = clk_get_rate(mct_clk);
489 panic("%s: unable to ioremap mct address space\n", __func__);
491 #ifdef CONFIG_LOCAL_TIMERS
492 if (mct_int_type == MCT_INT_PPI) {
495 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
496 exynos4_mct_tick_isr, "MCT",
498 WARN(err, "MCT: can't request IRQ %d (%d)\n",
499 mct_irqs[MCT_L0_IRQ], err);
502 local_timer_register(&exynos4_mct_tick_ops);
503 #endif /* CONFIG_LOCAL_TIMERS */
506 void __init mct_init(void)
508 if (soc_is_exynos4210()) {
509 mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
510 mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
511 mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
512 mct_int_type = MCT_INT_SPI;
514 panic("unable to determine mct controller type\n");
517 exynos4_timer_resources(S5P_VA_SYSTIMER);
518 exynos4_clocksource_init();
519 exynos4_clockevent_init();
522 static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
526 mct_int_type = int_type;
528 /* This driver uses only one global timer interrupt */
529 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
532 * Find out the number of local irqs specified. The local
533 * timer irqs are specified after the four global timer
534 * irqs are specified.
536 nr_irqs = of_irq_count(np);
537 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
538 mct_irqs[i] = irq_of_parse_and_map(np, i);
540 exynos4_timer_resources(of_iomap(np, 0));
541 exynos4_clocksource_init();
542 exynos4_clockevent_init();
546 static void __init mct_init_spi(struct device_node *np)
548 return mct_init_dt(np, MCT_INT_SPI);
551 static void __init mct_init_ppi(struct device_node *np)
553 return mct_init_dt(np, MCT_INT_PPI);
555 CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
556 CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);