1 // SPDX-License-Identifier: GPL-2.0+
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
6 * Copyright 2013 Freescale Semiconductor, Inc.
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux-vf610.h>
13 #include <asm/arch/ddrmc-vf610.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/clock.h>
18 #include <environment.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 static struct ddrmc_cr_setting pcm052_cr_settings[] = {
24 /* not in the datasheets, but in the original code */
28 { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
29 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
30 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
31 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
32 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
33 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
34 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
35 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
36 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
37 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
38 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
39 { DDRMC_CR126_PHY_RDLAT(11), 126 },
40 { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
41 { DDRMC_CR137_PHYCTL_DL(2), 137 },
42 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
43 DDRMC_CR139_PHY_WRLV_DLL(3) |
44 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
45 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
46 DDRMC_CR154_PAD_ZQ_MODE(1) |
47 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
48 DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
49 { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
50 { DDRMC_CR158_TWR(6), 158 },
51 { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
52 DDRMC_CR161_TODTH_WR(6), 161 },
57 /* PHY settings -- most of them differ from default in imx-regs.h */
59 #define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213
60 #define PCM052_DDRMC_PHY_CTRL 0x00290000
61 #define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00
62 #define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020
64 static struct ddrmc_phy_setting pcm052_phy_settings[] = {
65 { PCM052_DDRMC_PHY_DQ_TIMING, 0 },
66 { PCM052_DDRMC_PHY_DQ_TIMING, 16 },
67 { PCM052_DDRMC_PHY_DQ_TIMING, 32 },
68 { PCM052_DDRMC_PHY_DQ_TIMING, 48 },
69 { DDRMC_PHY_DQS_TIMING, 1 },
70 { DDRMC_PHY_DQS_TIMING, 17 },
71 { DDRMC_PHY_DQS_TIMING, 33 },
72 { DDRMC_PHY_DQS_TIMING, 49 },
73 { PCM052_DDRMC_PHY_CTRL, 2 },
74 { PCM052_DDRMC_PHY_CTRL, 18 },
75 { PCM052_DDRMC_PHY_CTRL, 34 },
76 { DDRMC_PHY_MASTER_CTRL, 3 },
77 { DDRMC_PHY_MASTER_CTRL, 19 },
78 { DDRMC_PHY_MASTER_CTRL, 35 },
79 { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 },
80 { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
81 { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
82 { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
83 { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
91 #if defined(CONFIG_TARGET_PCM052)
93 static const struct ddr3_jedec_timings pcm052_ddr_timings = {
96 .cke_inactive = 200000,
102 .tbst_int_interval = 4,
144 const int row_diff = 2;
146 #elif defined(CONFIG_TARGET_BK4R1)
148 static const struct ddr3_jedec_timings pcm052_ddr_timings = {
151 .cke_inactive = 200000,
157 .tbst_int_interval = 0,
199 const int row_diff = 1;
201 #else /* Unknown PCM052 variant */
203 #error DDR characteristics undefined for this target. Please define them.
207 ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
208 pcm052_phy_settings, 1, row_diff);
210 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
215 static void clock_init(void)
217 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
218 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
220 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
221 CCM_CCGR0_UART1_CTRL_MASK);
222 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
223 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
224 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
225 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
226 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
227 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
228 CCM_CCGR2_QSPI0_CTRL_MASK);
229 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
230 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
231 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
232 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
233 CCM_CCGR4_GPC_CTRL_MASK);
234 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
235 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
236 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
237 CCM_CCGR7_SDHC1_CTRL_MASK);
238 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
239 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
240 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
241 CCM_CCGR10_NFC_CTRL_MASK);
243 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
244 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
245 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
246 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
248 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
249 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
250 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
251 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
252 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
253 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
254 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
255 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
256 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
257 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
258 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
259 CCM_CACRR_ARM_CLK_DIV(0));
260 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
261 CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
262 CCM_CSCMR1_QSPI0_CLK_SEL(3) |
263 CCM_CSCMR1_NFC_CLK_SEL(0));
264 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
265 CCM_CSCDR1_RMII_CLK_EN);
266 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
267 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
269 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
270 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
271 CCM_CSCDR3_QSPI0_X2_DIV(1) |
272 CCM_CSCDR3_QSPI0_X4_DIV(3) |
273 CCM_CSCDR3_NFC_PRE_DIV(5));
274 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
275 CCM_CSCMR2_RMII_CLK_SEL(0));
278 static void mscm_init(void)
280 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
283 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
284 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
287 int board_early_init_f(void)
297 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
299 /* address of boot parameters */
300 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
303 * Enable external 32K Oscillator
305 * The internal clock experiences significant drift
306 * so we must use the external oscillator in order
307 * to maintain correct time in the hwclock
309 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
314 #ifdef CONFIG_TARGET_BK4R1
315 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
317 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
318 struct fuse_bank *bank = &ocotp->bank[4];
319 struct fuse_bank4_regs *fuse =
320 (struct fuse_bank4_regs *)bank->fuse_regs;
324 * BK4 has different layout of stored MAC address
325 * than one used in imx_get_mac_from_fuse() @ generic.c
330 value = readl(&fuse->mac_addr1);
335 value = readl(&fuse->mac_addr0);
336 mac[2] = value >> 24;
337 mac[3] = value >> 16;
342 value = readl(&fuse->mac_addr2);
344 mac[0] = value >> 24;
345 mac[1] = value >> 16;
349 value = readl(&fuse->mac_addr1);
350 mac[4] = value >> 24;
351 mac[5] = value >> 16;
356 int board_late_init(void)
358 struct src *psrc = (struct src *)SRC_BASE_ADDR;
361 if (IS_ENABLED(CONFIG_LED))
365 * BK4r1 handle emergency/service SD card boot
366 * Checking the SBMR1 register BOOTCFG1 byte:
368 * bit [2] - NAND data width - 16
369 * bit [5] - NAND fast boot
370 * bit [7] = 1 - NAND as a source of booting
372 * bit [4] = 0 - SD card source
373 * bit [6] = 1 - SD/MMC source
376 reg = readl(&psrc->sbmr1);
377 if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
378 !(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
379 printf("------ SD card boot -------\n");
380 env_set_default("!LVFBootloader", 0);
382 "run prepare_install_bk4r1_envs; run install_bk4r1rs");
391 #define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f
392 #define RMII_50MHz_CLOCK 0x8180
394 int board_phy_config(struct phy_device *phydev)
396 /* Set 50 MHz reference clock */
397 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
400 return genphy_config(phydev);
402 #endif /* CONFIG_TARGET_BK4R1 */
406 #ifdef CONFIG_TARGET_BK4R1
407 puts("Board: BK4r1 (L333)\n");
409 puts("Board: PCM-052\n");