1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/sysdev.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/slab.h>
8 #include <linux/hpet.h>
9 #include <linux/init.h>
10 #include <linux/cpu.h>
14 #include <asm/fixmap.h>
15 #include <asm/i8253.h>
18 #define HPET_MASK CLOCKSOURCE_MASK(32)
23 #define FSEC_PER_NSEC 1000000L
25 #define HPET_DEV_USED_BIT 2
26 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
27 #define HPET_DEV_VALID 0x8
28 #define HPET_DEV_FSB_CAP 0x1000
29 #define HPET_DEV_PERI_CAP 0x2000
31 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
34 * HPET address is set in acpi/boot.c, when an ACPI entry exists
36 unsigned long hpet_address;
37 u8 hpet_blockid; /* OS timer block num */
42 static unsigned long hpet_num_timers;
44 static void __iomem *hpet_virt_address;
47 struct clock_event_device evt;
55 inline unsigned int hpet_readl(unsigned int a)
57 return readl(hpet_virt_address + a);
60 static inline void hpet_writel(unsigned int d, unsigned int a)
62 writel(d, hpet_virt_address + a);
66 #include <asm/pgtable.h>
69 static inline void hpet_set_mapping(void)
71 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
73 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
77 static inline void hpet_clear_mapping(void)
79 iounmap(hpet_virt_address);
80 hpet_virt_address = NULL;
84 * HPET command line enable / disable
86 static int boot_hpet_disable;
88 static int hpet_verbose;
90 static int __init hpet_setup(char *str)
93 if (!strncmp("disable", str, 7))
94 boot_hpet_disable = 1;
95 if (!strncmp("force", str, 5))
97 if (!strncmp("verbose", str, 7))
102 __setup("hpet=", hpet_setup);
104 static int __init disable_hpet(char *str)
106 boot_hpet_disable = 1;
109 __setup("nohpet", disable_hpet);
111 static inline int is_hpet_capable(void)
113 return !boot_hpet_disable && hpet_address;
117 * HPET timer interrupt enable / disable
119 static int hpet_legacy_int_enabled;
122 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
124 int is_hpet_enabled(void)
126 return is_hpet_capable() && hpet_legacy_int_enabled;
128 EXPORT_SYMBOL_GPL(is_hpet_enabled);
130 static void _hpet_print_config(const char *function, int line)
133 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
134 l = hpet_readl(HPET_ID);
135 h = hpet_readl(HPET_PERIOD);
136 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
137 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
138 l = hpet_readl(HPET_CFG);
139 h = hpet_readl(HPET_STATUS);
140 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
141 l = hpet_readl(HPET_COUNTER);
142 h = hpet_readl(HPET_COUNTER+4);
143 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
145 for (i = 0; i < timers; i++) {
146 l = hpet_readl(HPET_Tn_CFG(i));
147 h = hpet_readl(HPET_Tn_CFG(i)+4);
148 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
150 l = hpet_readl(HPET_Tn_CMP(i));
151 h = hpet_readl(HPET_Tn_CMP(i)+4);
152 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
154 l = hpet_readl(HPET_Tn_ROUTE(i));
155 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
156 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
161 #define hpet_print_config() \
164 _hpet_print_config(__FUNCTION__, __LINE__); \
168 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
169 * timer 0 and timer 1 in case of RTC emulation.
173 static void hpet_reserve_msi_timers(struct hpet_data *hd);
175 static void hpet_reserve_platform_timers(unsigned int id)
177 struct hpet __iomem *hpet = hpet_virt_address;
178 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
179 unsigned int nrtimers, i;
182 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
184 memset(&hd, 0, sizeof(hd));
185 hd.hd_phys_address = hpet_address;
186 hd.hd_address = hpet;
187 hd.hd_nirqs = nrtimers;
188 hpet_reserve_timer(&hd, 0);
190 #ifdef CONFIG_HPET_EMULATE_RTC
191 hpet_reserve_timer(&hd, 1);
195 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
196 * is wrong for i8259!) not the output IRQ. Many BIOS writers
197 * don't bother configuring *any* comparator interrupts.
199 hd.hd_irq[0] = HPET_LEGACY_8254;
200 hd.hd_irq[1] = HPET_LEGACY_RTC;
202 for (i = 2; i < nrtimers; timer++, i++) {
203 hd.hd_irq[i] = (readl(&timer->hpet_config) &
204 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
207 hpet_reserve_msi_timers(&hd);
213 static void hpet_reserve_platform_timers(unsigned int id) { }
219 static unsigned long hpet_period;
221 static void hpet_legacy_set_mode(enum clock_event_mode mode,
222 struct clock_event_device *evt);
223 static int hpet_legacy_next_event(unsigned long delta,
224 struct clock_event_device *evt);
227 * The hpet clock event device
229 static struct clock_event_device hpet_clockevent = {
231 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
232 .set_mode = hpet_legacy_set_mode,
233 .set_next_event = hpet_legacy_next_event,
239 static void hpet_stop_counter(void)
241 unsigned long cfg = hpet_readl(HPET_CFG);
242 cfg &= ~HPET_CFG_ENABLE;
243 hpet_writel(cfg, HPET_CFG);
246 static void hpet_reset_counter(void)
248 hpet_writel(0, HPET_COUNTER);
249 hpet_writel(0, HPET_COUNTER + 4);
252 static void hpet_start_counter(void)
254 unsigned int cfg = hpet_readl(HPET_CFG);
255 cfg |= HPET_CFG_ENABLE;
256 hpet_writel(cfg, HPET_CFG);
259 static void hpet_restart_counter(void)
262 hpet_reset_counter();
263 hpet_start_counter();
266 static void hpet_resume_device(void)
271 static void hpet_resume_counter(struct clocksource *cs)
273 hpet_resume_device();
274 hpet_restart_counter();
277 static void hpet_enable_legacy_int(void)
279 unsigned int cfg = hpet_readl(HPET_CFG);
281 cfg |= HPET_CFG_LEGACY;
282 hpet_writel(cfg, HPET_CFG);
283 hpet_legacy_int_enabled = 1;
286 static void hpet_legacy_clockevent_register(void)
288 /* Start HPET legacy interrupts */
289 hpet_enable_legacy_int();
292 * The mult factor is defined as (include/linux/clockchips.h)
293 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
294 * hpet_period is in units of femtoseconds (per cycle), so
295 * mult/2^shift = cyc/ns = 10^6/hpet_period
296 * mult = (10^6 * 2^shift)/hpet_period
297 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
299 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
300 hpet_period, hpet_clockevent.shift);
301 /* Calculate the min / max delta */
302 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
304 /* 5 usec minimum reprogramming delta. */
305 hpet_clockevent.min_delta_ns = 5000;
308 * Start hpet with the boot cpu mask and make it
309 * global after the IO_APIC has been initialized.
311 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
312 clockevents_register_device(&hpet_clockevent);
313 global_clock_event = &hpet_clockevent;
314 printk(KERN_DEBUG "hpet clockevent registered\n");
317 static int hpet_setup_msi_irq(unsigned int irq);
319 static void hpet_set_mode(enum clock_event_mode mode,
320 struct clock_event_device *evt, int timer)
322 unsigned int cfg, cmp, now;
326 case CLOCK_EVT_MODE_PERIODIC:
328 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
329 delta >>= evt->shift;
330 now = hpet_readl(HPET_COUNTER);
331 cmp = now + (unsigned int) delta;
332 cfg = hpet_readl(HPET_Tn_CFG(timer));
333 /* Make sure we use edge triggered interrupts */
334 cfg &= ~HPET_TN_LEVEL;
335 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
336 HPET_TN_SETVAL | HPET_TN_32BIT;
337 hpet_writel(cfg, HPET_Tn_CFG(timer));
338 hpet_writel(cmp, HPET_Tn_CMP(timer));
341 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
342 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
343 * bit is automatically cleared after the first write.
344 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
345 * Publication # 24674)
347 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
348 hpet_start_counter();
352 case CLOCK_EVT_MODE_ONESHOT:
353 cfg = hpet_readl(HPET_Tn_CFG(timer));
354 cfg &= ~HPET_TN_PERIODIC;
355 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
356 hpet_writel(cfg, HPET_Tn_CFG(timer));
359 case CLOCK_EVT_MODE_UNUSED:
360 case CLOCK_EVT_MODE_SHUTDOWN:
361 cfg = hpet_readl(HPET_Tn_CFG(timer));
362 cfg &= ~HPET_TN_ENABLE;
363 hpet_writel(cfg, HPET_Tn_CFG(timer));
366 case CLOCK_EVT_MODE_RESUME:
368 hpet_enable_legacy_int();
370 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
371 hpet_setup_msi_irq(hdev->irq);
372 disable_irq(hdev->irq);
373 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
374 enable_irq(hdev->irq);
381 static int hpet_next_event(unsigned long delta,
382 struct clock_event_device *evt, int timer)
386 cnt = hpet_readl(HPET_COUNTER);
388 hpet_writel(cnt, HPET_Tn_CMP(timer));
391 * We need to read back the CMP register on certain HPET
392 * implementations (ATI chipsets) which seem to delay the
393 * transfer of the compare register into the internal compare
394 * logic. With small deltas this might actually be too late as
395 * the counter could already be higher than the compare value
396 * at that point and we would wait for the next hpet interrupt
397 * forever. We found out that reading the CMP register back
398 * forces the transfer so we can rely on the comparison with
399 * the counter register below.
401 * That works fine on those ATI chipsets, but on newer Intel
402 * chipsets (ICH9...) this triggers due to an erratum: Reading
403 * the comparator immediately following a write is returning
406 * We restrict the read back to the affected ATI chipsets (set
407 * by quirks) and also run it with hpet=verbose for debugging
410 if (hpet_readback_cmp || hpet_verbose) {
411 u32 cmp = hpet_readl(HPET_Tn_CMP(timer));
414 printk_once(KERN_WARNING
415 "hpet: compare register read back failed.\n");
418 return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
421 static void hpet_legacy_set_mode(enum clock_event_mode mode,
422 struct clock_event_device *evt)
424 hpet_set_mode(mode, evt, 0);
427 static int hpet_legacy_next_event(unsigned long delta,
428 struct clock_event_device *evt)
430 return hpet_next_event(delta, evt, 0);
436 #ifdef CONFIG_PCI_MSI
438 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
439 static struct hpet_dev *hpet_devs;
441 void hpet_msi_unmask(unsigned int irq)
443 struct hpet_dev *hdev = get_irq_data(irq);
447 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
449 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
452 void hpet_msi_mask(unsigned int irq)
455 struct hpet_dev *hdev = get_irq_data(irq);
458 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
460 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
463 void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
465 struct hpet_dev *hdev = get_irq_data(irq);
467 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
468 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
471 void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
473 struct hpet_dev *hdev = get_irq_data(irq);
475 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
476 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
480 static void hpet_msi_set_mode(enum clock_event_mode mode,
481 struct clock_event_device *evt)
483 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
484 hpet_set_mode(mode, evt, hdev->num);
487 static int hpet_msi_next_event(unsigned long delta,
488 struct clock_event_device *evt)
490 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
491 return hpet_next_event(delta, evt, hdev->num);
494 static int hpet_setup_msi_irq(unsigned int irq)
496 if (arch_setup_hpet_msi(irq, hpet_blockid)) {
503 static int hpet_assign_irq(struct hpet_dev *dev)
511 set_irq_data(irq, dev);
513 if (hpet_setup_msi_irq(irq))
520 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
522 struct hpet_dev *dev = (struct hpet_dev *)data;
523 struct clock_event_device *hevt = &dev->evt;
525 if (!hevt->event_handler) {
526 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
531 hevt->event_handler(hevt);
535 static int hpet_setup_irq(struct hpet_dev *dev)
538 if (request_irq(dev->irq, hpet_interrupt_handler,
539 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
543 disable_irq(dev->irq);
544 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
545 enable_irq(dev->irq);
547 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
548 dev->name, dev->irq);
553 /* This should be called in specific @cpu */
554 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
556 struct clock_event_device *evt = &hdev->evt;
559 WARN_ON(cpu != smp_processor_id());
560 if (!(hdev->flags & HPET_DEV_VALID))
563 if (hpet_setup_msi_irq(hdev->irq))
567 per_cpu(cpu_hpet_dev, cpu) = hdev;
568 evt->name = hdev->name;
569 hpet_setup_irq(hdev);
570 evt->irq = hdev->irq;
573 evt->features = CLOCK_EVT_FEAT_ONESHOT;
574 if (hdev->flags & HPET_DEV_PERI_CAP)
575 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
577 evt->set_mode = hpet_msi_set_mode;
578 evt->set_next_event = hpet_msi_next_event;
582 * The period is a femto seconds value. We need to calculate the
583 * scaled math multiplication factor for nanosecond to hpet tick
586 hpet_freq = 1000000000000000ULL;
587 do_div(hpet_freq, hpet_period);
588 evt->mult = div_sc((unsigned long) hpet_freq,
589 NSEC_PER_SEC, evt->shift);
590 /* Calculate the max delta */
591 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
592 /* 5 usec minimum reprogramming delta. */
593 evt->min_delta_ns = 5000;
595 evt->cpumask = cpumask_of(hdev->cpu);
596 clockevents_register_device(evt);
600 /* Reserve at least one timer for userspace (/dev/hpet) */
601 #define RESERVE_TIMERS 1
603 #define RESERVE_TIMERS 0
606 static void hpet_msi_capability_lookup(unsigned int start_timer)
609 unsigned int num_timers;
610 unsigned int num_timers_used = 0;
613 if (hpet_msi_disable)
616 if (boot_cpu_has(X86_FEATURE_ARAT))
618 id = hpet_readl(HPET_ID);
620 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
621 num_timers++; /* Value read out starts from 0 */
624 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
628 hpet_num_timers = num_timers;
630 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
631 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
632 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
634 /* Only consider HPET timer with MSI support */
635 if (!(cfg & HPET_TN_FSB_CAP))
639 if (cfg & HPET_TN_PERIODIC_CAP)
640 hdev->flags |= HPET_DEV_PERI_CAP;
643 sprintf(hdev->name, "hpet%d", i);
644 if (hpet_assign_irq(hdev))
647 hdev->flags |= HPET_DEV_FSB_CAP;
648 hdev->flags |= HPET_DEV_VALID;
650 if (num_timers_used == num_possible_cpus())
654 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
655 num_timers, num_timers_used);
659 static void hpet_reserve_msi_timers(struct hpet_data *hd)
666 for (i = 0; i < hpet_num_timers; i++) {
667 struct hpet_dev *hdev = &hpet_devs[i];
669 if (!(hdev->flags & HPET_DEV_VALID))
672 hd->hd_irq[hdev->num] = hdev->irq;
673 hpet_reserve_timer(hd, hdev->num);
678 static struct hpet_dev *hpet_get_unused_timer(void)
685 for (i = 0; i < hpet_num_timers; i++) {
686 struct hpet_dev *hdev = &hpet_devs[i];
688 if (!(hdev->flags & HPET_DEV_VALID))
690 if (test_and_set_bit(HPET_DEV_USED_BIT,
691 (unsigned long *)&hdev->flags))
698 struct hpet_work_struct {
699 struct delayed_work work;
700 struct completion complete;
703 static void hpet_work(struct work_struct *w)
705 struct hpet_dev *hdev;
706 int cpu = smp_processor_id();
707 struct hpet_work_struct *hpet_work;
709 hpet_work = container_of(w, struct hpet_work_struct, work.work);
711 hdev = hpet_get_unused_timer();
713 init_one_hpet_msi_clockevent(hdev, cpu);
715 complete(&hpet_work->complete);
718 static int hpet_cpuhp_notify(struct notifier_block *n,
719 unsigned long action, void *hcpu)
721 unsigned long cpu = (unsigned long)hcpu;
722 struct hpet_work_struct work;
723 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
725 switch (action & 0xf) {
727 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
728 init_completion(&work.complete);
729 /* FIXME: add schedule_work_on() */
730 schedule_delayed_work_on(cpu, &work.work, 0);
731 wait_for_completion(&work.complete);
732 destroy_timer_on_stack(&work.work.timer);
736 free_irq(hdev->irq, hdev);
737 hdev->flags &= ~HPET_DEV_USED;
738 per_cpu(cpu_hpet_dev, cpu) = NULL;
746 static int hpet_setup_msi_irq(unsigned int irq)
750 static void hpet_msi_capability_lookup(unsigned int start_timer)
756 static void hpet_reserve_msi_timers(struct hpet_data *hd)
762 static int hpet_cpuhp_notify(struct notifier_block *n,
763 unsigned long action, void *hcpu)
771 * Clock source related code
773 static cycle_t read_hpet(struct clocksource *cs)
775 return (cycle_t)hpet_readl(HPET_COUNTER);
779 static cycle_t __vsyscall_fn vread_hpet(void)
781 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
785 static struct clocksource clocksource_hpet = {
791 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
792 .resume = hpet_resume_counter,
798 static int hpet_clocksource_register(void)
803 /* Start the counter */
804 hpet_restart_counter();
806 /* Verify whether hpet counter works */
807 t1 = hpet_readl(HPET_COUNTER);
811 * We don't know the TSC frequency yet, but waiting for
812 * 200000 TSC cycles is safe:
819 } while ((now - start) < 200000UL);
821 if (t1 == hpet_readl(HPET_COUNTER)) {
823 "HPET counter not counting. HPET disabled\n");
828 * The definition of mult is (include/linux/clocksource.h)
829 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
830 * so we first need to convert hpet_period to ns/cyc units:
831 * mult/2^shift = ns/cyc = hpet_period/10^6
832 * mult = (hpet_period * 2^shift)/10^6
833 * mult = (hpet_period << shift)/FSEC_PER_NSEC
835 clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
837 clocksource_register(&clocksource_hpet);
843 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
845 int __init hpet_enable(void)
850 if (!is_hpet_capable())
856 * Read the period and check for a sane value:
858 hpet_period = hpet_readl(HPET_PERIOD);
861 * AMD SB700 based systems with spread spectrum enabled use a
862 * SMM based HPET emulation to provide proper frequency
863 * setting. The SMM code is initialized with the first HPET
864 * register access and takes some time to complete. During
865 * this time the config register reads 0xffffffff. We check
866 * for max. 1000 loops whether the config register reads a non
867 * 0xffffffff value to make sure that HPET is up and running
868 * before we go further. A counting loop is safe, as the HPET
869 * access takes thousands of CPU cycles. On non SB700 based
870 * machines this check is only done once and has no side
873 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
876 "HPET config register value = 0xFFFFFFFF. "
882 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
886 * Read the HPET ID register to retrieve the IRQ routing
887 * information and the number of channels
889 id = hpet_readl(HPET_ID);
892 #ifdef CONFIG_HPET_EMULATE_RTC
894 * The legacy routing mode needs at least two channels, tick timer
895 * and the rtc emulation channel.
897 if (!(id & HPET_ID_NUMBER))
901 if (hpet_clocksource_register())
904 if (id & HPET_ID_LEGSUP) {
905 hpet_legacy_clockevent_register();
911 hpet_clear_mapping();
917 * Needs to be late, as the reserve_timer code calls kalloc !
919 * Not a problem on i386 as hpet_enable is called from late_time_init,
920 * but on x86_64 it is necessary !
922 static __init int hpet_late_init(void)
926 if (boot_hpet_disable)
930 if (!force_hpet_address)
933 hpet_address = force_hpet_address;
937 if (!hpet_virt_address)
940 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
941 hpet_msi_capability_lookup(2);
943 hpet_msi_capability_lookup(0);
945 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
948 if (hpet_msi_disable)
951 if (boot_cpu_has(X86_FEATURE_ARAT))
954 for_each_online_cpu(cpu) {
955 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
958 /* This notifier should be called after workqueue is ready */
959 hotcpu_notifier(hpet_cpuhp_notify, -20);
963 fs_initcall(hpet_late_init);
965 void hpet_disable(void)
967 if (is_hpet_capable()) {
968 unsigned int cfg = hpet_readl(HPET_CFG);
970 if (hpet_legacy_int_enabled) {
971 cfg &= ~HPET_CFG_LEGACY;
972 hpet_legacy_int_enabled = 0;
974 cfg &= ~HPET_CFG_ENABLE;
975 hpet_writel(cfg, HPET_CFG);
979 #ifdef CONFIG_HPET_EMULATE_RTC
981 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
982 * is enabled, we support RTC interrupt functionality in software.
983 * RTC has 3 kinds of interrupts:
984 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
986 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
987 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
988 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
989 * (1) and (2) above are implemented using polling at a frequency of
990 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
991 * overhead. (DEFAULT_RTC_INT_FREQ)
992 * For (3), we use interrupts at 64Hz or user specified periodic
993 * frequency, whichever is higher.
995 #include <linux/mc146818rtc.h>
996 #include <linux/rtc.h>
999 #define DEFAULT_RTC_INT_FREQ 64
1000 #define DEFAULT_RTC_SHIFT 6
1001 #define RTC_NUM_INTS 1
1003 static unsigned long hpet_rtc_flags;
1004 static int hpet_prev_update_sec;
1005 static struct rtc_time hpet_alarm_time;
1006 static unsigned long hpet_pie_count;
1007 static u32 hpet_t1_cmp;
1008 static u32 hpet_default_delta;
1009 static u32 hpet_pie_delta;
1010 static unsigned long hpet_pie_limit;
1012 static rtc_irq_handler irq_handler;
1015 * Check that the hpet counter c1 is ahead of the c2
1017 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1019 return (s32)(c2 - c1) < 0;
1023 * Registers a IRQ handler.
1025 int hpet_register_irq_handler(rtc_irq_handler handler)
1027 if (!is_hpet_enabled())
1032 irq_handler = handler;
1036 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1039 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1042 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1044 if (!is_hpet_enabled())
1050 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1053 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1054 * is not supported by all HPET implementations for timer 1.
1056 * hpet_rtc_timer_init() is called when the rtc is initialized.
1058 int hpet_rtc_timer_init(void)
1060 unsigned int cfg, cnt, delta;
1061 unsigned long flags;
1063 if (!is_hpet_enabled())
1066 if (!hpet_default_delta) {
1069 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1070 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1071 hpet_default_delta = clc;
1074 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1075 delta = hpet_default_delta;
1077 delta = hpet_pie_delta;
1079 local_irq_save(flags);
1081 cnt = delta + hpet_readl(HPET_COUNTER);
1082 hpet_writel(cnt, HPET_T1_CMP);
1085 cfg = hpet_readl(HPET_T1_CFG);
1086 cfg &= ~HPET_TN_PERIODIC;
1087 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1088 hpet_writel(cfg, HPET_T1_CFG);
1090 local_irq_restore(flags);
1094 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1097 * The functions below are called from rtc driver.
1098 * Return 0 if HPET is not being used.
1099 * Otherwise do the necessary changes and return 1.
1101 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1103 if (!is_hpet_enabled())
1106 hpet_rtc_flags &= ~bit_mask;
1109 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1111 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1113 unsigned long oldbits = hpet_rtc_flags;
1115 if (!is_hpet_enabled())
1118 hpet_rtc_flags |= bit_mask;
1120 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1121 hpet_prev_update_sec = -1;
1124 hpet_rtc_timer_init();
1128 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1130 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1133 if (!is_hpet_enabled())
1136 hpet_alarm_time.tm_hour = hrs;
1137 hpet_alarm_time.tm_min = min;
1138 hpet_alarm_time.tm_sec = sec;
1142 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1144 int hpet_set_periodic_freq(unsigned long freq)
1148 if (!is_hpet_enabled())
1151 if (freq <= DEFAULT_RTC_INT_FREQ)
1152 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1154 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1156 clc >>= hpet_clockevent.shift;
1157 hpet_pie_delta = clc;
1162 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1164 int hpet_rtc_dropped_irq(void)
1166 return is_hpet_enabled();
1168 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1170 static void hpet_rtc_timer_reinit(void)
1172 unsigned int cfg, delta;
1175 if (unlikely(!hpet_rtc_flags)) {
1176 cfg = hpet_readl(HPET_T1_CFG);
1177 cfg &= ~HPET_TN_ENABLE;
1178 hpet_writel(cfg, HPET_T1_CFG);
1182 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1183 delta = hpet_default_delta;
1185 delta = hpet_pie_delta;
1188 * Increment the comparator value until we are ahead of the
1192 hpet_t1_cmp += delta;
1193 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1195 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1198 if (hpet_rtc_flags & RTC_PIE)
1199 hpet_pie_count += lost_ints;
1200 if (printk_ratelimit())
1201 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1206 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1208 struct rtc_time curr_time;
1209 unsigned long rtc_int_flag = 0;
1211 hpet_rtc_timer_reinit();
1212 memset(&curr_time, 0, sizeof(struct rtc_time));
1214 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1215 get_rtc_time(&curr_time);
1217 if (hpet_rtc_flags & RTC_UIE &&
1218 curr_time.tm_sec != hpet_prev_update_sec) {
1219 if (hpet_prev_update_sec >= 0)
1220 rtc_int_flag = RTC_UF;
1221 hpet_prev_update_sec = curr_time.tm_sec;
1224 if (hpet_rtc_flags & RTC_PIE &&
1225 ++hpet_pie_count >= hpet_pie_limit) {
1226 rtc_int_flag |= RTC_PF;
1230 if (hpet_rtc_flags & RTC_AIE &&
1231 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1232 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1233 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1234 rtc_int_flag |= RTC_AF;
1237 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1239 irq_handler(rtc_int_flag, dev_id);
1243 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);