4 select PPC_HAVE_PMU_SUPPORT
6 This option selects whether a 32-bit or a 64-bit kernel
9 menu "Processor support"
11 prompt "Processor Type"
14 There are five families of 32 bit PowerPC chips supported.
15 The most common ones are the desktop and server CPUs (601, 603,
16 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their
17 embedded 512x/52xx/82xx/83xx/86xx counterparts.
18 The other embeeded parts, namely 4xx, 8xx, e200 (55xx) and e500
19 (85xx) each form a family of their own that is not compatible
22 If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx.
25 bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx"
67 depends on PPC_BOOK3S_32 || PPC_BOOK3S_64
70 bool "Optimize for POWER4"
71 depends on PPC64 && PPC_BOOK3S
74 Cause the compiler to optimize for POWER4/POWER5/PPC970 processors.
75 The resulting binary will not work on POWER3 or RS64 processors
76 when compiled with binutils 2.15 or later.
80 depends on PPC32 && PPC_BOOK3S
81 select PPC_HAVE_PMU_SUPPORT
85 depends on PPC64 && PPC_BOOK3S
86 default y if !POWER4_ONLY
89 depends on PPC64 && PPC_BOOK3S
93 bool "Optimize for Cell Broadband Engine"
94 depends on PPC64 && PPC_BOOK3S
96 Cause the compiler to optimize for the PPE of the Cell Broadband
97 Engine. This will make the code run considerably faster on Cell
98 but somewhat slower on other machines. This option only changes
99 the scheduling of instructions, not the selection of instructions
100 itself, so the resulting kernel will keep running on all other
101 machines. When building a kernel that is supposed to run only
102 on Cell, you should also select the POWER4_ONLY option.
104 # this is temp to handle compat with arch=ppc
109 select FSL_EMB_PERFMON
113 bool "e500mc Support"
123 depends on 40x || 44x
128 depends on E200 || E500 || 44x
133 depends on E200 || E500
136 config FSL_EMB_PERFMON
137 bool "Freescale Embedded Perfmon"
138 depends on E500 || PPC_83xx
140 This is the Performance Monitor support found on the e500 core
141 and some e300 cores (c3 and c4). Select this only if your
142 core supports the Embedded Performance Monitor APU
146 depends on 44x || E500 || PPC_86xx
147 default y if PHYS_64BIT
150 bool 'Large physical address support' if E500 || PPC_86xx
151 depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx
153 This option enables kernel support for larger than 32-bit physical
154 addresses. This feature may not be available on all cores.
156 If you have more than 3.5GB of RAM or so, you also need to enable
157 SWIOTLB under Kernel Options for this to work. The actual number
158 is platform-dependent.
160 If in doubt, say N here.
163 bool "AltiVec Support"
164 depends on 6xx || POWER4
166 This option enables kernel support for the Altivec extensions to the
167 PowerPC processor. The kernel currently supports saving and restoring
168 altivec registers, and turning on the 'altivec enable' bit so user
169 processes can execute altivec instructions.
171 This option is only usefully if you have a processor that supports
172 altivec (G4, otherwise known as 74xx series), but does not have
173 any affect on a non-altivec cpu (it does, however add code to the
176 If in doubt, say Y here.
180 depends on POWER4 && ALTIVEC && PPC_FPU
183 This option enables kernel support for the Vector Scaler extensions
184 to the PowerPC processor. The kernel currently supports saving and
185 restoring VSX registers, and turning on the 'VSX enable' bit so user
186 processes can execute VSX instructions.
188 This option is only useful if you have a processor that supports
189 VSX (P7 and above), but does not have any affect on a non-VSX
190 CPUs (it does, however add code to the kernel).
192 If in doubt, say Y here.
196 depends on E200 || (E500 && !PPC_E500MC)
199 This option enables kernel support for the Signal Processing
200 Extensions (SPE) to the PowerPC processor. The kernel currently
201 supports saving and restoring SPE registers, and turning on the
202 'spe enable' bit so user processes can execute SPE instructions.
204 This option is only useful if you have a processor that supports
205 SPE (e500, otherwise known as 85xx series), but does not have any
206 effect on a non-spe cpu (it does, however add code to the kernel).
208 If in doubt, say Y here.
212 depends on PPC_BOOK3S
214 config PPC_STD_MMU_32
216 depends on PPC_STD_MMU && PPC32
218 config PPC_STD_MMU_64
220 depends on PPC_STD_MMU && PPC64
222 config PPC_MMU_NOHASH
224 depends on !PPC_STD_MMU
226 config PPC_BOOK3E_MMU
232 default y if HUGETLB_PAGE || (PPC_STD_MMU_64 && PPC_64K_PAGES)
235 config VIRT_CPU_ACCOUNTING
236 bool "Deterministic task and CPU time accounting"
240 Select this option to enable more accurate task and CPU time
241 accounting. This is done by reading a CPU counter on each
242 kernel entry and exit and on transitions within the kernel
243 between system, softirq and hardirq state, so there is a
244 small performance impact. This also enables accounting of
245 stolen time on logically-partitioned systems running on
246 IBM POWER5-based machines.
248 If in doubt, say Y here.
250 config PPC_HAVE_PMU_SUPPORT
255 depends on PERF_COUNTERS && PPC_HAVE_PMU_SUPPORT
257 This enables the powerpc-specific perf_counter back-end.
260 depends on PPC_STD_MMU || FSL_BOOKE
261 bool "Symmetric multi-processing support"
263 This enables support for systems with more than one CPU. If you have
264 a system with only one CPU, say N. If you have a system with more
265 than one CPU, say Y. Note that the kernel does not currently
266 support SMP machines with 603/603e/603ev or PPC750 ("G3") processors
267 since they have inadequate hardware support for multiprocessor
270 If you say N here, the kernel will run on single and multiprocessor
271 machines, but will use only one CPU of a multiprocessor machine. If
272 you say Y here, the kernel will run on single-processor machines.
273 On a single-processor machine, the kernel will run faster if you say
276 If you don't know what to do here, say N.
279 int "Maximum number of CPUs (2-8192)"
282 default "32" if PPC64
285 config NOT_COHERENT_CACHE
287 depends on 4xx || 8xx || E200 || PPC_MPC512x
290 config CHECK_CACHE_COHERENCY