2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
33 #include <asm/firmware.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only = 1;
43 int pci_assign_all_buses = 0;
45 #ifdef CONFIG_PPC_MULTIPLATFORM
46 static void fixup_resource(struct resource *res, struct pci_dev *dev);
47 static void do_bus_setup(struct pci_bus *bus);
48 static void phbs_remap_io(void);
51 /* pci_io_base -- the base address from which io bars are offsets.
52 * This is the lowest I/O base address (so bar values are always positive),
53 * and it *must* be the start of ISA space if an ISA bus exists because
54 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
55 * page is mapped and isa_io_limit prevents access to it.
57 unsigned long isa_io_base; /* NULL if no ISA bus */
58 EXPORT_SYMBOL(isa_io_base);
59 unsigned long pci_io_base;
60 EXPORT_SYMBOL(pci_io_base);
62 void iSeries_pcibios_init(void);
66 struct dma_mapping_ops pci_dma_ops;
67 EXPORT_SYMBOL(pci_dma_ops);
69 int global_phb_number; /* Global phb counter */
71 /* Cached ISA bridge dev. */
72 struct pci_dev *ppc64_isabridge_dev = NULL;
73 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev);
75 static void fixup_broken_pcnet32(struct pci_dev* dev)
77 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
78 dev->vendor = PCI_VENDOR_ID_AMD;
79 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
82 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
84 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
87 unsigned long offset = 0;
88 struct pci_controller *hose = pci_bus_to_host(dev->bus);
93 if (res->flags & IORESOURCE_IO)
94 offset = (unsigned long)hose->io_base_virt - pci_io_base;
96 if (res->flags & IORESOURCE_MEM)
97 offset = hose->pci_mem_offset;
99 region->start = res->start - offset;
100 region->end = res->end - offset;
103 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
104 struct pci_bus_region *region)
106 unsigned long offset = 0;
107 struct pci_controller *hose = pci_bus_to_host(dev->bus);
112 if (res->flags & IORESOURCE_IO)
113 offset = (unsigned long)hose->io_base_virt - pci_io_base;
115 if (res->flags & IORESOURCE_MEM)
116 offset = hose->pci_mem_offset;
118 res->start = region->start + offset;
119 res->end = region->end + offset;
122 #ifdef CONFIG_HOTPLUG
123 EXPORT_SYMBOL(pcibios_resource_to_bus);
124 EXPORT_SYMBOL(pcibios_bus_to_resource);
128 * We need to avoid collisions with `mirrored' VGA ports
129 * and other strange ISA hardware, so we always want the
130 * addresses to be allocated in the 0x000-0x0ff region
133 * Why? Because some silly external IO cards only decode
134 * the low 10 bits of the IO address. The 0x00-0xff region
135 * is reserved for motherboard devices that decode all 16
136 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
137 * but we want to try to avoid allocating at 0x2900-0x2bff
138 * which might have be mirrored at 0x0100-0x03ff..
140 void pcibios_align_resource(void *data, struct resource *res,
141 resource_size_t size, resource_size_t align)
143 struct pci_dev *dev = data;
144 struct pci_controller *hose = pci_bus_to_host(dev->bus);
145 resource_size_t start = res->start;
146 unsigned long alignto;
148 if (res->flags & IORESOURCE_IO) {
149 unsigned long offset = (unsigned long)hose->io_base_virt -
151 /* Make sure we start at our min on all hoses */
152 if (start - offset < PCIBIOS_MIN_IO)
153 start = PCIBIOS_MIN_IO + offset;
156 * Put everything into 0x00-0xff region modulo 0x400
159 start = (start + 0x3ff) & ~0x3ff;
161 } else if (res->flags & IORESOURCE_MEM) {
162 /* Make sure we start at our min on all hoses */
163 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
164 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
166 /* Align to multiple of size of minimum base. */
167 alignto = max(0x1000UL, align);
168 start = ALIGN(start, alignto);
174 static DEFINE_SPINLOCK(hose_spinlock);
177 * pci_controller(phb) initialized common variables.
179 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
181 memset(hose, 0, sizeof(struct pci_controller));
183 spin_lock(&hose_spinlock);
184 hose->global_number = global_phb_number++;
185 list_add_tail(&hose->list_node, &hose_list);
186 spin_unlock(&hose_spinlock);
189 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
191 struct pci_controller *phb;
194 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
196 phb = alloc_bootmem(sizeof (struct pci_controller));
199 pci_setup_pci_controller(phb);
200 phb->arch_data = dev;
201 phb->is_dynamic = mem_init_done;
203 int nid = of_node_to_nid(dev);
205 if (nid < 0 || !node_online(nid))
208 PHB_SET_NODE(phb, nid);
213 void pcibios_free_controller(struct pci_controller *phb)
219 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
222 struct pci_bus *child_bus;
224 list_for_each_entry(dev, &b->devices, bus_list) {
227 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
228 struct resource *r = &dev->resource[i];
230 if (r->parent || !r->start || !r->flags)
232 pci_claim_resource(dev, i);
236 list_for_each_entry(child_bus, &b->children, node)
237 pcibios_claim_one_bus(child_bus);
239 #ifdef CONFIG_HOTPLUG
240 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
243 static void __init pcibios_claim_of_setup(void)
247 if (firmware_has_feature(FW_FEATURE_ISERIES))
250 list_for_each_entry(b, &pci_root_buses, node)
251 pcibios_claim_one_bus(b);
254 #ifdef CONFIG_PPC_MULTIPLATFORM
255 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
260 prop = get_property(np, name, &len);
261 if (prop && len >= 4)
266 static unsigned int pci_parse_of_flags(u32 addr0)
268 unsigned int flags = 0;
270 if (addr0 & 0x02000000) {
271 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
272 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
273 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
274 if (addr0 & 0x40000000)
275 flags |= IORESOURCE_PREFETCH
276 | PCI_BASE_ADDRESS_MEM_PREFETCH;
277 } else if (addr0 & 0x01000000)
278 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
282 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
284 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
288 struct resource *res;
293 addrs = get_property(node, "assigned-addresses", &proplen);
296 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
297 for (; proplen >= 20; proplen -= 20, addrs += 5) {
298 flags = pci_parse_of_flags(addrs[0]);
301 base = GET_64BIT(addrs, 1);
302 size = GET_64BIT(addrs, 3);
306 DBG(" base: %llx, size: %llx, i: %x\n",
307 (unsigned long long)base, (unsigned long long)size, i);
309 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
310 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
311 } else if (i == dev->rom_base_reg) {
312 res = &dev->resource[PCI_ROM_RESOURCE];
313 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
315 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
319 res->end = base + size - 1;
321 res->name = pci_name(dev);
322 fixup_resource(res, dev);
326 struct pci_dev *of_create_pci_dev(struct device_node *node,
327 struct pci_bus *bus, int devfn)
332 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
335 type = get_property(node, "device_type", NULL);
339 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
341 memset(dev, 0, sizeof(struct pci_dev));
344 dev->dev.parent = bus->bridge;
345 dev->dev.bus = &pci_bus_type;
347 dev->multifunction = 0; /* maybe a lie? */
349 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
350 dev->device = get_int_prop(node, "device-id", 0xffff);
351 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
352 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
354 dev->cfg_size = pci_cfg_space_size(dev);
356 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
357 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
358 dev->class = get_int_prop(node, "class-code", 0);
360 DBG(" class: 0x%x\n", dev->class);
362 dev->current_state = 4; /* unknown power state */
364 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
365 /* a PCI-PCI bridge */
366 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
367 dev->rom_base_reg = PCI_ROM_ADDRESS1;
368 } else if (!strcmp(type, "cardbus")) {
369 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
371 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
372 dev->rom_base_reg = PCI_ROM_ADDRESS;
373 /* Maybe do a default OF mapping here */
377 pci_parse_of_addrs(node, dev);
379 DBG(" adding to system ...\n");
381 pci_device_add(dev, bus);
383 /* XXX pci_scan_msi_device(dev); */
387 EXPORT_SYMBOL(of_create_pci_dev);
389 void __devinit of_scan_bus(struct device_node *node,
392 struct device_node *child = NULL;
397 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
399 while ((child = of_get_next_child(node, child)) != NULL) {
400 DBG(" * %s\n", child->full_name);
401 reg = get_property(child, "reg", ®len);
402 if (reg == NULL || reglen < 20)
404 devfn = (reg[0] >> 8) & 0xff;
406 /* create a new pci_dev for this device */
407 dev = of_create_pci_dev(child, bus, devfn);
410 DBG("dev header type: %x\n", dev->hdr_type);
412 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
413 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
414 of_scan_pci_bridge(child, dev);
419 EXPORT_SYMBOL(of_scan_bus);
421 void __devinit of_scan_pci_bridge(struct device_node *node,
425 const u32 *busrange, *ranges;
427 struct resource *res;
431 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
433 /* parse bus-range property */
434 busrange = get_property(node, "bus-range", &len);
435 if (busrange == NULL || len != 8) {
436 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
440 ranges = get_property(node, "ranges", &len);
441 if (ranges == NULL) {
442 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
447 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
449 printk(KERN_ERR "Failed to create pci bus for %s\n",
454 bus->primary = dev->bus->number;
455 bus->subordinate = busrange[1];
459 /* parse ranges property */
460 /* PCI #address-cells == 3 and #size-cells == 2 always */
461 res = &dev->resource[PCI_BRIDGE_RESOURCES];
462 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
464 bus->resource[i] = res;
468 for (; len >= 32; len -= 32, ranges += 8) {
469 flags = pci_parse_of_flags(ranges[0]);
470 size = GET_64BIT(ranges, 6);
471 if (flags == 0 || size == 0)
473 if (flags & IORESOURCE_IO) {
474 res = bus->resource[0];
476 printk(KERN_ERR "PCI: ignoring extra I/O range"
477 " for bridge %s\n", node->full_name);
481 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
482 printk(KERN_ERR "PCI: too many memory ranges"
483 " for bridge %s\n", node->full_name);
486 res = bus->resource[i];
489 res->start = GET_64BIT(ranges, 1);
490 res->end = res->start + size - 1;
492 fixup_resource(res, dev);
494 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
496 DBG(" bus name: %s\n", bus->name);
498 mode = PCI_PROBE_NORMAL;
499 if (ppc_md.pci_probe_mode)
500 mode = ppc_md.pci_probe_mode(bus);
501 DBG(" probe mode: %d\n", mode);
503 if (mode == PCI_PROBE_DEVTREE)
504 of_scan_bus(node, bus);
505 else if (mode == PCI_PROBE_NORMAL)
506 pci_scan_child_bus(bus);
508 EXPORT_SYMBOL(of_scan_pci_bridge);
509 #endif /* CONFIG_PPC_MULTIPLATFORM */
511 void __devinit scan_phb(struct pci_controller *hose)
514 struct device_node *node = hose->arch_data;
516 struct resource *res;
518 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
520 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
522 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
523 hose->global_number);
526 bus->secondary = hose->first_busno;
529 bus->resource[0] = res = &hose->io_resource;
530 if (res->flags && request_resource(&ioport_resource, res))
531 printk(KERN_ERR "Failed to request PCI IO region "
532 "on PCI domain %04x\n", hose->global_number);
534 for (i = 0; i < 3; ++i) {
535 res = &hose->mem_resources[i];
536 bus->resource[i+1] = res;
537 if (res->flags && request_resource(&iomem_resource, res))
538 printk(KERN_ERR "Failed to request PCI memory region "
539 "on PCI domain %04x\n", hose->global_number);
542 mode = PCI_PROBE_NORMAL;
543 #ifdef CONFIG_PPC_MULTIPLATFORM
544 if (node && ppc_md.pci_probe_mode)
545 mode = ppc_md.pci_probe_mode(bus);
546 DBG(" probe mode: %d\n", mode);
547 if (mode == PCI_PROBE_DEVTREE) {
548 bus->subordinate = hose->last_busno;
549 of_scan_bus(node, bus);
551 #endif /* CONFIG_PPC_MULTIPLATFORM */
552 if (mode == PCI_PROBE_NORMAL)
553 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
556 static int __init pcibios_init(void)
558 struct pci_controller *hose, *tmp;
560 /* For now, override phys_mem_access_prot. If we need it,
561 * later, we may move that initialization to each ppc_md
563 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
565 if (firmware_has_feature(FW_FEATURE_ISERIES))
566 iSeries_pcibios_init();
568 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
570 /* Scan all of the recorded PCI controllers. */
571 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
573 pci_bus_add_devices(hose->bus);
576 if (!firmware_has_feature(FW_FEATURE_ISERIES)) {
578 pcibios_claim_of_setup();
580 /* FIXME: `else' will be removed when
581 pci_assign_unassigned_resources() is able to work
582 correctly with [partially] allocated PCI tree. */
583 pci_assign_unassigned_resources();
586 /* Call machine dependent final fixup */
587 if (ppc_md.pcibios_fixup)
588 ppc_md.pcibios_fixup();
590 /* Cache the location of the ISA bridge (if we have one) */
591 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
592 if (ppc64_isabridge_dev != NULL)
593 printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
595 #ifdef CONFIG_PPC_MULTIPLATFORM
596 if (!firmware_has_feature(FW_FEATURE_ISERIES))
597 /* map in PCI I/O space */
601 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
606 subsys_initcall(pcibios_init);
608 char __init *pcibios_setup(char *str)
613 int pcibios_enable_device(struct pci_dev *dev, int mask)
618 pci_read_config_word(dev, PCI_COMMAND, &cmd);
621 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
622 struct resource *res = &dev->resource[i];
624 /* Only set up the requested stuff */
625 if (!(mask & (1<<i)))
628 if (res->flags & IORESOURCE_IO)
629 cmd |= PCI_COMMAND_IO;
630 if (res->flags & IORESOURCE_MEM)
631 cmd |= PCI_COMMAND_MEMORY;
635 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
637 /* Enable the appropriate bits in the PCI command register. */
638 pci_write_config_word(dev, PCI_COMMAND, cmd);
644 * Return the domain number for this bus.
646 int pci_domain_nr(struct pci_bus *bus)
648 if (firmware_has_feature(FW_FEATURE_ISERIES))
651 struct pci_controller *hose = pci_bus_to_host(bus);
653 return hose->global_number;
657 EXPORT_SYMBOL(pci_domain_nr);
659 /* Decide whether to display the domain number in /proc */
660 int pci_proc_domain(struct pci_bus *bus)
662 if (firmware_has_feature(FW_FEATURE_ISERIES))
665 struct pci_controller *hose = pci_bus_to_host(bus);
671 * Platform support for /proc/bus/pci/X/Y mmap()s,
672 * modelled on the sparc64 implementation by Dave Miller.
677 * Adjust vm_pgoff of VMA such that it is the physical page offset
678 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
680 * Basically, the user finds the base address for his device which he wishes
681 * to mmap. They read the 32-bit value from the config space base register,
682 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
683 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
685 * Returns negative error code on failure, zero on success.
687 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
688 unsigned long *offset,
689 enum pci_mmap_state mmap_state)
691 struct pci_controller *hose = pci_bus_to_host(dev->bus);
692 unsigned long io_offset = 0;
696 return NULL; /* should never happen */
698 /* If memory, add on the PCI bridge address offset */
699 if (mmap_state == pci_mmap_mem) {
700 *offset += hose->pci_mem_offset;
701 res_bit = IORESOURCE_MEM;
703 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
704 *offset += io_offset;
705 res_bit = IORESOURCE_IO;
709 * Check that the offset requested corresponds to one of the
710 * resources of the device.
712 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
713 struct resource *rp = &dev->resource[i];
714 int flags = rp->flags;
716 /* treat ROM as memory (should be already) */
717 if (i == PCI_ROM_RESOURCE)
718 flags |= IORESOURCE_MEM;
720 /* Active and same type? */
721 if ((flags & res_bit) == 0)
724 /* In the range of this resource? */
725 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
728 /* found it! construct the final physical address */
729 if (mmap_state == pci_mmap_io)
730 *offset += hose->io_base_phys - io_offset;
738 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
741 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
743 enum pci_mmap_state mmap_state,
746 unsigned long prot = pgprot_val(protection);
748 /* Write combine is always 0 on non-memory space mappings. On
749 * memory space, if the user didn't pass 1, we check for a
750 * "prefetchable" resource. This is a bit hackish, but we use
751 * this to workaround the inability of /sysfs to provide a write
754 if (mmap_state != pci_mmap_mem)
756 else if (write_combine == 0) {
757 if (rp->flags & IORESOURCE_PREFETCH)
761 /* XXX would be nice to have a way to ask for write-through */
762 prot |= _PAGE_NO_CACHE;
764 prot &= ~_PAGE_GUARDED;
766 prot |= _PAGE_GUARDED;
768 printk(KERN_DEBUG "PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
771 return __pgprot(prot);
775 * This one is used by /dev/mem and fbdev who have no clue about the
776 * PCI device, it tries to find the PCI device first and calls the
779 pgprot_t pci_phys_mem_access_prot(struct file *file,
784 struct pci_dev *pdev = NULL;
785 struct resource *found = NULL;
786 unsigned long prot = pgprot_val(protection);
787 unsigned long offset = pfn << PAGE_SHIFT;
790 if (page_is_ram(pfn))
791 return __pgprot(prot);
793 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
795 for_each_pci_dev(pdev) {
796 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
797 struct resource *rp = &pdev->resource[i];
798 int flags = rp->flags;
800 /* Active and same type? */
801 if ((flags & IORESOURCE_MEM) == 0)
803 /* In the range of this resource? */
804 if (offset < (rp->start & PAGE_MASK) ||
814 if (found->flags & IORESOURCE_PREFETCH)
815 prot &= ~_PAGE_GUARDED;
819 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
821 return __pgprot(prot);
826 * Perform the actual remap of the pages for a PCI device mapping, as
827 * appropriate for this architecture. The region in the process to map
828 * is described by vm_start and vm_end members of VMA, the base physical
829 * address is found in vm_pgoff.
830 * The pci device structure is provided so that architectures may make mapping
831 * decisions on a per-device or per-bus basis.
833 * Returns a negative error code on failure, zero on success.
835 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
836 enum pci_mmap_state mmap_state, int write_combine)
838 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
842 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
846 vma->vm_pgoff = offset >> PAGE_SHIFT;
847 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
849 mmap_state, write_combine);
851 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
852 vma->vm_end - vma->vm_start, vma->vm_page_prot);
857 static ssize_t pci_show_devspec(struct device *dev,
858 struct device_attribute *attr, char *buf)
860 struct pci_dev *pdev;
861 struct device_node *np;
863 pdev = to_pci_dev (dev);
864 np = pci_device_to_OF_node(pdev);
865 if (np == NULL || np->full_name == NULL)
867 return sprintf(buf, "%s", np->full_name);
869 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
871 void pcibios_add_platform_entries(struct pci_dev *pdev)
873 device_create_file(&pdev->dev, &dev_attr_devspec);
876 #ifdef CONFIG_PPC_MULTIPLATFORM
878 #define ISA_SPACE_MASK 0x1
879 #define ISA_SPACE_IO 0x1
881 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
882 unsigned long phb_io_base_phys,
883 void __iomem * phb_io_base_virt)
885 /* Remove these asap */
899 struct isa_address isa_addr;
900 struct pci_address pci_addr;
904 const struct isa_range *range;
905 unsigned long pci_addr;
906 unsigned int isa_addr;
910 range = get_property(isa_node, "ranges", &rlen);
911 if (range == NULL || (rlen < sizeof(struct isa_range))) {
912 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
914 __ioremap_explicit(phb_io_base_phys,
915 (unsigned long)phb_io_base_virt,
916 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
920 /* From "ISA Binding to 1275"
921 * The ranges property is laid out as an array of elements,
922 * each of which comprises:
923 * cells 0 - 1: an ISA address
924 * cells 2 - 4: a PCI address
925 * (size depending on dev->n_addr_cells)
926 * cell 5: the size of the range
928 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
929 isa_addr = range->isa_addr.a_lo;
930 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
931 range->pci_addr.a_lo;
933 /* Assume these are both zero */
934 if ((pci_addr != 0) || (isa_addr != 0)) {
935 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
940 size = PAGE_ALIGN(range->size);
942 __ioremap_explicit(phb_io_base_phys,
943 (unsigned long) phb_io_base_virt,
944 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
948 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
949 struct device_node *dev, int prim)
951 const unsigned int *ranges;
952 unsigned int pci_space;
956 struct resource *res;
957 int np, na = prom_n_addr_cells(dev);
958 unsigned long pci_addr, cpu_phys_addr;
962 /* From "PCI Binding to 1275"
963 * The ranges property is laid out as an array of elements,
964 * each of which comprises:
965 * cells 0 - 2: a PCI address
966 * cells 3 or 3+4: a CPU physical address
967 * (size depending on dev->n_addr_cells)
968 * cells 4+5 or 5+6: the size of the range
970 ranges = get_property(dev, "ranges", &rlen);
973 hose->io_base_phys = 0;
974 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
976 pci_space = ranges[0];
977 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
979 cpu_phys_addr = ranges[3];
981 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
983 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
988 /* Now consume following elements while they are contiguous */
989 while (rlen >= np * sizeof(unsigned int)) {
990 unsigned long addr, phys;
992 if (ranges[0] != pci_space)
994 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
997 phys = (phys << 32) | ranges[4];
998 if (addr != pci_addr + size ||
999 phys != cpu_phys_addr + size)
1002 size += ((unsigned long)ranges[na+3] << 32)
1005 rlen -= np * sizeof(unsigned int);
1008 switch ((pci_space >> 24) & 0x3) {
1009 case 1: /* I/O space */
1010 hose->io_base_phys = cpu_phys_addr;
1011 hose->pci_io_size = size;
1013 res = &hose->io_resource;
1014 res->flags = IORESOURCE_IO;
1015 res->start = pci_addr;
1016 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
1017 res->start, res->start + size - 1);
1019 case 2: /* memory space */
1021 while (memno < 3 && hose->mem_resources[memno].flags)
1025 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
1027 res = &hose->mem_resources[memno];
1028 res->flags = IORESOURCE_MEM;
1029 res->start = cpu_phys_addr;
1030 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
1031 res->start, res->start + size - 1);
1036 res->name = dev->full_name;
1037 res->end = res->start + size - 1;
1039 res->sibling = NULL;
1045 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
1047 unsigned long size = hose->pci_io_size;
1048 unsigned long io_virt_offset;
1049 struct resource *res;
1050 struct device_node *isa_dn;
1052 hose->io_base_virt = reserve_phb_iospace(size);
1053 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1054 hose->global_number, hose->io_base_phys,
1055 (unsigned long) hose->io_base_virt);
1058 pci_io_base = (unsigned long)hose->io_base_virt;
1059 isa_dn = of_find_node_by_type(NULL, "isa");
1061 isa_io_base = pci_io_base;
1062 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1063 hose->io_base_virt);
1064 of_node_put(isa_dn);
1068 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1069 res = &hose->io_resource;
1070 res->start += io_virt_offset;
1071 res->end += io_virt_offset;
1074 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1077 unsigned long size = hose->pci_io_size;
1078 unsigned long io_virt_offset;
1079 struct resource *res;
1081 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
1082 _PAGE_NO_CACHE | _PAGE_GUARDED);
1083 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1084 hose->global_number, hose->io_base_phys,
1085 (unsigned long) hose->io_base_virt);
1088 pci_io_base = (unsigned long)hose->io_base_virt;
1090 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1091 res = &hose->io_resource;
1092 res->start += io_virt_offset;
1093 res->end += io_virt_offset;
1097 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1098 unsigned long *start_virt, unsigned long *size)
1100 struct pci_controller *hose = pci_bus_to_host(bus);
1101 struct pci_bus_region region;
1102 struct resource *res;
1105 res = bus->resource[0];
1106 pcibios_resource_to_bus(bus->self, ®ion, res);
1107 *start_phys = hose->io_base_phys + region.start;
1108 *start_virt = (unsigned long) hose->io_base_virt +
1110 if (region.end > region.start)
1111 *size = region.end - region.start + 1;
1113 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1114 __FUNCTION__, region.start, region.end);
1120 res = &hose->io_resource;
1121 *start_phys = hose->io_base_phys;
1122 *start_virt = (unsigned long) hose->io_base_virt;
1123 if (res->end > res->start)
1124 *size = res->end - res->start + 1;
1126 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1127 __FUNCTION__, res->start, res->end);
1135 int unmap_bus_range(struct pci_bus *bus)
1137 unsigned long start_phys;
1138 unsigned long start_virt;
1142 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1146 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1148 if (iounmap_explicit((void __iomem *) start_virt, size))
1153 EXPORT_SYMBOL(unmap_bus_range);
1155 int remap_bus_range(struct pci_bus *bus)
1157 unsigned long start_phys;
1158 unsigned long start_virt;
1162 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1167 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1169 if (start_phys == 0)
1171 printk(KERN_DEBUG "mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1172 if (__ioremap_explicit(start_phys, start_virt, size,
1173 _PAGE_NO_CACHE | _PAGE_GUARDED))
1178 EXPORT_SYMBOL(remap_bus_range);
1180 static void phbs_remap_io(void)
1182 struct pci_controller *hose, *tmp;
1184 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1185 remap_bus_range(hose->bus);
1188 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1190 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1191 unsigned long offset;
1193 if (res->flags & IORESOURCE_IO) {
1194 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1196 res->start += offset;
1198 } else if (res->flags & IORESOURCE_MEM) {
1199 res->start += hose->pci_mem_offset;
1200 res->end += hose->pci_mem_offset;
1204 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1205 struct pci_bus *bus)
1207 /* Update device resources. */
1210 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1211 if (dev->resource[i].flags)
1212 fixup_resource(&dev->resource[i], dev);
1214 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1217 static void __devinit do_bus_setup(struct pci_bus *bus)
1219 struct pci_dev *dev;
1221 ppc_md.iommu_bus_setup(bus);
1223 list_for_each_entry(dev, &bus->devices, bus_list)
1224 ppc_md.iommu_dev_setup(dev);
1226 if (ppc_md.irq_bus_setup)
1227 ppc_md.irq_bus_setup(bus);
1230 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1232 struct pci_dev *dev = bus->self;
1234 if (dev && pci_probe_only &&
1235 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1236 /* This is a subordinate bridge */
1238 pci_read_bridge_bases(bus);
1239 pcibios_fixup_device_resources(dev, bus);
1244 if (!pci_probe_only)
1247 list_for_each_entry(dev, &bus->devices, bus_list)
1248 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1249 pcibios_fixup_device_resources(dev, bus);
1251 EXPORT_SYMBOL(pcibios_fixup_bus);
1254 * Reads the interrupt pin to determine if interrupt is use by card.
1255 * If the interrupt is used, then gets the interrupt line from the
1256 * openfirmware and sets it in the pci_dev and pci_config line.
1258 int pci_read_irq_line(struct pci_dev *pci_dev)
1263 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1266 memset(&oirq, 0xff, sizeof(oirq));
1268 /* Try to get a mapping from the device-tree */
1269 if (of_irq_map_pci(pci_dev, &oirq)) {
1272 /* If that fails, lets fallback to what is in the config
1273 * space and map that through the default controller. We
1274 * also set the type to level low since that's what PCI
1275 * interrupts are. If your platform does differently, then
1276 * either provide a proper interrupt tree or don't use this
1279 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
1283 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
1287 DBG(" -> no map ! Using irq line %d from PCI config\n", line);
1289 virq = irq_create_mapping(NULL, line);
1291 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
1293 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
1294 oirq.size, oirq.specifier[0], oirq.specifier[1],
1295 oirq.controller->full_name);
1297 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
1300 if(virq == NO_IRQ) {
1301 DBG(" -> failed to map !\n");
1305 DBG(" -> mapped to linux irq %d\n", virq);
1307 pci_dev->irq = virq;
1308 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
1312 EXPORT_SYMBOL(pci_read_irq_line);
1314 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1315 const struct resource *rsrc,
1316 u64 *start, u64 *end)
1318 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1319 unsigned long offset = 0;
1324 if (rsrc->flags & IORESOURCE_IO)
1325 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1328 *start = rsrc->start + offset;
1329 *end = rsrc->end + offset;
1332 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
1337 struct pci_controller *hose, *tmp;
1338 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1339 if (hose->arch_data == node)
1341 node = node->parent;
1346 #endif /* CONFIG_PPC_MULTIPLATFORM */
1348 unsigned long pci_address_to_pio(phys_addr_t address)
1350 struct pci_controller *hose, *tmp;
1352 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1353 if (address >= hose->io_base_phys &&
1354 address < (hose->io_base_phys + hose->pci_io_size)) {
1355 unsigned long base =
1356 (unsigned long)hose->io_base_virt - pci_io_base;
1357 return base + (address - hose->io_base_phys);
1360 return (unsigned int)-1;
1362 EXPORT_SYMBOL_GPL(pci_address_to_pio);
1365 #define IOBASE_BRIDGE_NUMBER 0
1366 #define IOBASE_MEMORY 1
1368 #define IOBASE_ISA_IO 3
1369 #define IOBASE_ISA_MEM 4
1371 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1372 unsigned long in_devfn)
1374 struct pci_controller* hose;
1375 struct list_head *ln;
1376 struct pci_bus *bus = NULL;
1377 struct device_node *hose_node;
1379 /* Argh ! Please forgive me for that hack, but that's the
1380 * simplest way to get existing XFree to not lockup on some
1381 * G5 machines... So when something asks for bus 0 io base
1382 * (bus 0 is HT root), we return the AGP one instead.
1384 if (machine_is_compatible("MacRISC4"))
1388 /* That syscall isn't quite compatible with PCI domains, but it's
1389 * used on pre-domains setup. We return the first match
1392 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1393 bus = pci_bus_b(ln);
1394 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1398 if (bus == NULL || bus->sysdata == NULL)
1401 hose_node = (struct device_node *)bus->sysdata;
1402 hose = PCI_DN(hose_node)->phb;
1405 case IOBASE_BRIDGE_NUMBER:
1406 return (long)hose->first_busno;
1408 return (long)hose->pci_mem_offset;
1410 return (long)hose->io_base_phys;
1412 return (long)isa_io_base;
1413 case IOBASE_ISA_MEM:
1421 int pcibus_to_node(struct pci_bus *bus)
1423 struct pci_controller *phb = pci_bus_to_host(bus);
1426 EXPORT_SYMBOL(pcibus_to_node);