2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
25 #include <asm/processor.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
36 #define DBG(fmt...) printk(fmt)
41 unsigned long pci_probe_only = 1;
42 int pci_assign_all_buses = 0;
44 #ifdef CONFIG_PPC_MULTIPLATFORM
45 static void fixup_resource(struct resource *res, struct pci_dev *dev);
46 static void do_bus_setup(struct pci_bus *bus);
47 static void phbs_remap_io(void);
50 /* pci_io_base -- the base address from which io bars are offsets.
51 * This is the lowest I/O base address (so bar values are always positive),
52 * and it *must* be the start of ISA space if an ISA bus exists because
53 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
54 * page is mapped and isa_io_limit prevents access to it.
56 unsigned long isa_io_base; /* NULL if no ISA bus */
57 EXPORT_SYMBOL(isa_io_base);
58 unsigned long pci_io_base;
59 EXPORT_SYMBOL(pci_io_base);
61 void iSeries_pcibios_init(void);
65 struct dma_mapping_ops pci_dma_ops;
66 EXPORT_SYMBOL(pci_dma_ops);
68 int global_phb_number; /* Global phb counter */
70 /* Cached ISA bridge dev. */
71 struct pci_dev *ppc64_isabridge_dev = NULL;
72 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev);
74 static void fixup_broken_pcnet32(struct pci_dev* dev)
76 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
77 dev->vendor = PCI_VENDOR_ID_AMD;
78 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
81 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
83 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
86 unsigned long offset = 0;
87 struct pci_controller *hose = pci_bus_to_host(dev->bus);
92 if (res->flags & IORESOURCE_IO)
93 offset = (unsigned long)hose->io_base_virt - pci_io_base;
95 if (res->flags & IORESOURCE_MEM)
96 offset = hose->pci_mem_offset;
98 region->start = res->start - offset;
99 region->end = res->end - offset;
102 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
103 struct pci_bus_region *region)
105 unsigned long offset = 0;
106 struct pci_controller *hose = pci_bus_to_host(dev->bus);
111 if (res->flags & IORESOURCE_IO)
112 offset = (unsigned long)hose->io_base_virt - pci_io_base;
114 if (res->flags & IORESOURCE_MEM)
115 offset = hose->pci_mem_offset;
117 res->start = region->start + offset;
118 res->end = region->end + offset;
121 #ifdef CONFIG_HOTPLUG
122 EXPORT_SYMBOL(pcibios_resource_to_bus);
123 EXPORT_SYMBOL(pcibios_bus_to_resource);
127 * We need to avoid collisions with `mirrored' VGA ports
128 * and other strange ISA hardware, so we always want the
129 * addresses to be allocated in the 0x000-0x0ff region
132 * Why? Because some silly external IO cards only decode
133 * the low 10 bits of the IO address. The 0x00-0xff region
134 * is reserved for motherboard devices that decode all 16
135 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
136 * but we want to try to avoid allocating at 0x2900-0x2bff
137 * which might have be mirrored at 0x0100-0x03ff..
139 void pcibios_align_resource(void *data, struct resource *res,
140 resource_size_t size, resource_size_t align)
142 struct pci_dev *dev = data;
143 struct pci_controller *hose = pci_bus_to_host(dev->bus);
144 resource_size_t start = res->start;
145 unsigned long alignto;
147 if (res->flags & IORESOURCE_IO) {
148 unsigned long offset = (unsigned long)hose->io_base_virt -
150 /* Make sure we start at our min on all hoses */
151 if (start - offset < PCIBIOS_MIN_IO)
152 start = PCIBIOS_MIN_IO + offset;
155 * Put everything into 0x00-0xff region modulo 0x400
158 start = (start + 0x3ff) & ~0x3ff;
160 } else if (res->flags & IORESOURCE_MEM) {
161 /* Make sure we start at our min on all hoses */
162 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
163 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
165 /* Align to multiple of size of minimum base. */
166 alignto = max(0x1000UL, align);
167 start = ALIGN(start, alignto);
173 static DEFINE_SPINLOCK(hose_spinlock);
176 * pci_controller(phb) initialized common variables.
178 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
180 memset(hose, 0, sizeof(struct pci_controller));
182 spin_lock(&hose_spinlock);
183 hose->global_number = global_phb_number++;
184 list_add_tail(&hose->list_node, &hose_list);
185 spin_unlock(&hose_spinlock);
188 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
190 struct pci_controller *phb;
193 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
195 phb = alloc_bootmem(sizeof (struct pci_controller));
198 pci_setup_pci_controller(phb);
199 phb->arch_data = dev;
200 phb->is_dynamic = mem_init_done;
202 PHB_SET_NODE(phb, of_node_to_nid(dev));
206 void pcibios_free_controller(struct pci_controller *phb)
212 #ifndef CONFIG_PPC_ISERIES
213 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
216 struct pci_bus *child_bus;
218 list_for_each_entry(dev, &b->devices, bus_list) {
221 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
222 struct resource *r = &dev->resource[i];
224 if (r->parent || !r->start || !r->flags)
226 pci_claim_resource(dev, i);
230 list_for_each_entry(child_bus, &b->children, node)
231 pcibios_claim_one_bus(child_bus);
233 #ifdef CONFIG_HOTPLUG
234 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
237 static void __init pcibios_claim_of_setup(void)
241 list_for_each_entry(b, &pci_root_buses, node)
242 pcibios_claim_one_bus(b);
246 #ifdef CONFIG_PPC_MULTIPLATFORM
247 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
252 prop = (u32 *) get_property(np, name, &len);
253 if (prop && len >= 4)
258 static unsigned int pci_parse_of_flags(u32 addr0)
260 unsigned int flags = 0;
262 if (addr0 & 0x02000000) {
263 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
264 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
265 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
266 if (addr0 & 0x40000000)
267 flags |= IORESOURCE_PREFETCH
268 | PCI_BASE_ADDRESS_MEM_PREFETCH;
269 } else if (addr0 & 0x01000000)
270 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
274 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
276 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
280 struct resource *res;
284 addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
287 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
288 for (; proplen >= 20; proplen -= 20, addrs += 5) {
289 flags = pci_parse_of_flags(addrs[0]);
292 base = GET_64BIT(addrs, 1);
293 size = GET_64BIT(addrs, 3);
297 DBG(" base: %llx, size: %llx, i: %x\n",
298 (unsigned long long)base, (unsigned long long)size, i);
300 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
301 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
302 } else if (i == dev->rom_base_reg) {
303 res = &dev->resource[PCI_ROM_RESOURCE];
304 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
306 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
310 res->end = base + size - 1;
312 res->name = pci_name(dev);
313 fixup_resource(res, dev);
317 struct pci_dev *of_create_pci_dev(struct device_node *node,
318 struct pci_bus *bus, int devfn)
323 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
326 type = get_property(node, "device_type", NULL);
330 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
332 memset(dev, 0, sizeof(struct pci_dev));
335 dev->dev.parent = bus->bridge;
336 dev->dev.bus = &pci_bus_type;
338 dev->multifunction = 0; /* maybe a lie? */
340 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
341 dev->device = get_int_prop(node, "device-id", 0xffff);
342 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
343 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
345 dev->cfg_size = pci_cfg_space_size(dev);
347 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
348 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
349 dev->class = get_int_prop(node, "class-code", 0);
351 DBG(" class: 0x%x\n", dev->class);
353 dev->current_state = 4; /* unknown power state */
355 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
356 /* a PCI-PCI bridge */
357 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
358 dev->rom_base_reg = PCI_ROM_ADDRESS1;
359 } else if (!strcmp(type, "cardbus")) {
360 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
362 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
363 dev->rom_base_reg = PCI_ROM_ADDRESS;
364 /* Maybe do a default OF mapping here */
368 pci_parse_of_addrs(node, dev);
370 DBG(" adding to system ...\n");
372 pci_device_add(dev, bus);
374 /* XXX pci_scan_msi_device(dev); */
378 EXPORT_SYMBOL(of_create_pci_dev);
380 void __devinit of_scan_bus(struct device_node *node,
383 struct device_node *child = NULL;
388 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
390 while ((child = of_get_next_child(node, child)) != NULL) {
391 DBG(" * %s\n", child->full_name);
392 reg = (u32 *) get_property(child, "reg", ®len);
393 if (reg == NULL || reglen < 20)
395 devfn = (reg[0] >> 8) & 0xff;
397 /* create a new pci_dev for this device */
398 dev = of_create_pci_dev(child, bus, devfn);
401 DBG("dev header type: %x\n", dev->hdr_type);
403 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
404 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
405 of_scan_pci_bridge(child, dev);
410 EXPORT_SYMBOL(of_scan_bus);
412 void __devinit of_scan_pci_bridge(struct device_node *node,
416 u32 *busrange, *ranges;
418 struct resource *res;
422 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
424 /* parse bus-range property */
425 busrange = (u32 *) get_property(node, "bus-range", &len);
426 if (busrange == NULL || len != 8) {
427 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
431 ranges = (u32 *) get_property(node, "ranges", &len);
432 if (ranges == NULL) {
433 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
438 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
440 printk(KERN_ERR "Failed to create pci bus for %s\n",
445 bus->primary = dev->bus->number;
446 bus->subordinate = busrange[1];
450 /* parse ranges property */
451 /* PCI #address-cells == 3 and #size-cells == 2 always */
452 res = &dev->resource[PCI_BRIDGE_RESOURCES];
453 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
455 bus->resource[i] = res;
459 for (; len >= 32; len -= 32, ranges += 8) {
460 flags = pci_parse_of_flags(ranges[0]);
461 size = GET_64BIT(ranges, 6);
462 if (flags == 0 || size == 0)
464 if (flags & IORESOURCE_IO) {
465 res = bus->resource[0];
467 printk(KERN_ERR "PCI: ignoring extra I/O range"
468 " for bridge %s\n", node->full_name);
472 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
473 printk(KERN_ERR "PCI: too many memory ranges"
474 " for bridge %s\n", node->full_name);
477 res = bus->resource[i];
480 res->start = GET_64BIT(ranges, 1);
481 res->end = res->start + size - 1;
483 fixup_resource(res, dev);
485 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
487 DBG(" bus name: %s\n", bus->name);
489 mode = PCI_PROBE_NORMAL;
490 if (ppc_md.pci_probe_mode)
491 mode = ppc_md.pci_probe_mode(bus);
492 DBG(" probe mode: %d\n", mode);
494 if (mode == PCI_PROBE_DEVTREE)
495 of_scan_bus(node, bus);
496 else if (mode == PCI_PROBE_NORMAL)
497 pci_scan_child_bus(bus);
499 EXPORT_SYMBOL(of_scan_pci_bridge);
500 #endif /* CONFIG_PPC_MULTIPLATFORM */
502 void __devinit scan_phb(struct pci_controller *hose)
505 struct device_node *node = hose->arch_data;
507 struct resource *res;
509 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
511 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
513 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
514 hose->global_number);
517 bus->secondary = hose->first_busno;
520 bus->resource[0] = res = &hose->io_resource;
521 if (res->flags && request_resource(&ioport_resource, res))
522 printk(KERN_ERR "Failed to request PCI IO region "
523 "on PCI domain %04x\n", hose->global_number);
525 for (i = 0; i < 3; ++i) {
526 res = &hose->mem_resources[i];
527 bus->resource[i+1] = res;
528 if (res->flags && request_resource(&iomem_resource, res))
529 printk(KERN_ERR "Failed to request PCI memory region "
530 "on PCI domain %04x\n", hose->global_number);
533 mode = PCI_PROBE_NORMAL;
534 #ifdef CONFIG_PPC_MULTIPLATFORM
535 if (node && ppc_md.pci_probe_mode)
536 mode = ppc_md.pci_probe_mode(bus);
537 DBG(" probe mode: %d\n", mode);
538 if (mode == PCI_PROBE_DEVTREE) {
539 bus->subordinate = hose->last_busno;
540 of_scan_bus(node, bus);
542 #endif /* CONFIG_PPC_MULTIPLATFORM */
543 if (mode == PCI_PROBE_NORMAL)
544 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
547 static int __init pcibios_init(void)
549 struct pci_controller *hose, *tmp;
551 /* For now, override phys_mem_access_prot. If we need it,
552 * later, we may move that initialization to each ppc_md
554 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
556 #ifdef CONFIG_PPC_ISERIES
557 iSeries_pcibios_init();
560 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
562 /* Scan all of the recorded PCI controllers. */
563 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
565 pci_bus_add_devices(hose->bus);
568 #ifndef CONFIG_PPC_ISERIES
570 pcibios_claim_of_setup();
572 /* FIXME: `else' will be removed when
573 pci_assign_unassigned_resources() is able to work
574 correctly with [partially] allocated PCI tree. */
575 pci_assign_unassigned_resources();
576 #endif /* !CONFIG_PPC_ISERIES */
578 /* Call machine dependent final fixup */
579 if (ppc_md.pcibios_fixup)
580 ppc_md.pcibios_fixup();
582 /* Cache the location of the ISA bridge (if we have one) */
583 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
584 if (ppc64_isabridge_dev != NULL)
585 printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
587 #ifdef CONFIG_PPC_MULTIPLATFORM
588 /* map in PCI I/O space */
592 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
597 subsys_initcall(pcibios_init);
599 char __init *pcibios_setup(char *str)
604 int pcibios_enable_device(struct pci_dev *dev, int mask)
609 pci_read_config_word(dev, PCI_COMMAND, &cmd);
612 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
613 struct resource *res = &dev->resource[i];
615 /* Only set up the requested stuff */
616 if (!(mask & (1<<i)))
619 if (res->flags & IORESOURCE_IO)
620 cmd |= PCI_COMMAND_IO;
621 if (res->flags & IORESOURCE_MEM)
622 cmd |= PCI_COMMAND_MEMORY;
626 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
628 /* Enable the appropriate bits in the PCI command register. */
629 pci_write_config_word(dev, PCI_COMMAND, cmd);
635 * Return the domain number for this bus.
637 int pci_domain_nr(struct pci_bus *bus)
639 #ifdef CONFIG_PPC_ISERIES
642 struct pci_controller *hose = pci_bus_to_host(bus);
644 return hose->global_number;
648 EXPORT_SYMBOL(pci_domain_nr);
650 /* Decide whether to display the domain number in /proc */
651 int pci_proc_domain(struct pci_bus *bus)
653 #ifdef CONFIG_PPC_ISERIES
656 struct pci_controller *hose = pci_bus_to_host(bus);
662 * Platform support for /proc/bus/pci/X/Y mmap()s,
663 * modelled on the sparc64 implementation by Dave Miller.
668 * Adjust vm_pgoff of VMA such that it is the physical page offset
669 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
671 * Basically, the user finds the base address for his device which he wishes
672 * to mmap. They read the 32-bit value from the config space base register,
673 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
674 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
676 * Returns negative error code on failure, zero on success.
678 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
679 unsigned long *offset,
680 enum pci_mmap_state mmap_state)
682 struct pci_controller *hose = pci_bus_to_host(dev->bus);
683 unsigned long io_offset = 0;
687 return NULL; /* should never happen */
689 /* If memory, add on the PCI bridge address offset */
690 if (mmap_state == pci_mmap_mem) {
691 *offset += hose->pci_mem_offset;
692 res_bit = IORESOURCE_MEM;
694 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
695 *offset += io_offset;
696 res_bit = IORESOURCE_IO;
700 * Check that the offset requested corresponds to one of the
701 * resources of the device.
703 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
704 struct resource *rp = &dev->resource[i];
705 int flags = rp->flags;
707 /* treat ROM as memory (should be already) */
708 if (i == PCI_ROM_RESOURCE)
709 flags |= IORESOURCE_MEM;
711 /* Active and same type? */
712 if ((flags & res_bit) == 0)
715 /* In the range of this resource? */
716 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
719 /* found it! construct the final physical address */
720 if (mmap_state == pci_mmap_io)
721 *offset += hose->io_base_phys - io_offset;
729 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
732 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
734 enum pci_mmap_state mmap_state,
737 unsigned long prot = pgprot_val(protection);
739 /* Write combine is always 0 on non-memory space mappings. On
740 * memory space, if the user didn't pass 1, we check for a
741 * "prefetchable" resource. This is a bit hackish, but we use
742 * this to workaround the inability of /sysfs to provide a write
745 if (mmap_state != pci_mmap_mem)
747 else if (write_combine == 0) {
748 if (rp->flags & IORESOURCE_PREFETCH)
752 /* XXX would be nice to have a way to ask for write-through */
753 prot |= _PAGE_NO_CACHE;
755 prot &= ~_PAGE_GUARDED;
757 prot |= _PAGE_GUARDED;
759 printk(KERN_DEBUG "PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
762 return __pgprot(prot);
766 * This one is used by /dev/mem and fbdev who have no clue about the
767 * PCI device, it tries to find the PCI device first and calls the
770 pgprot_t pci_phys_mem_access_prot(struct file *file,
775 struct pci_dev *pdev = NULL;
776 struct resource *found = NULL;
777 unsigned long prot = pgprot_val(protection);
778 unsigned long offset = pfn << PAGE_SHIFT;
781 if (page_is_ram(pfn))
782 return __pgprot(prot);
784 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
786 for_each_pci_dev(pdev) {
787 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
788 struct resource *rp = &pdev->resource[i];
789 int flags = rp->flags;
791 /* Active and same type? */
792 if ((flags & IORESOURCE_MEM) == 0)
794 /* In the range of this resource? */
795 if (offset < (rp->start & PAGE_MASK) ||
805 if (found->flags & IORESOURCE_PREFETCH)
806 prot &= ~_PAGE_GUARDED;
810 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
812 return __pgprot(prot);
817 * Perform the actual remap of the pages for a PCI device mapping, as
818 * appropriate for this architecture. The region in the process to map
819 * is described by vm_start and vm_end members of VMA, the base physical
820 * address is found in vm_pgoff.
821 * The pci device structure is provided so that architectures may make mapping
822 * decisions on a per-device or per-bus basis.
824 * Returns a negative error code on failure, zero on success.
826 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
827 enum pci_mmap_state mmap_state, int write_combine)
829 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
833 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
837 vma->vm_pgoff = offset >> PAGE_SHIFT;
838 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
840 mmap_state, write_combine);
842 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
843 vma->vm_end - vma->vm_start, vma->vm_page_prot);
848 static ssize_t pci_show_devspec(struct device *dev,
849 struct device_attribute *attr, char *buf)
851 struct pci_dev *pdev;
852 struct device_node *np;
854 pdev = to_pci_dev (dev);
855 np = pci_device_to_OF_node(pdev);
856 if (np == NULL || np->full_name == NULL)
858 return sprintf(buf, "%s", np->full_name);
860 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
862 void pcibios_add_platform_entries(struct pci_dev *pdev)
864 device_create_file(&pdev->dev, &dev_attr_devspec);
867 #ifdef CONFIG_PPC_MULTIPLATFORM
869 #define ISA_SPACE_MASK 0x1
870 #define ISA_SPACE_IO 0x1
872 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
873 unsigned long phb_io_base_phys,
874 void __iomem * phb_io_base_virt)
876 /* Remove these asap */
890 struct isa_address isa_addr;
891 struct pci_address pci_addr;
895 struct isa_range *range;
896 unsigned long pci_addr;
897 unsigned int isa_addr;
901 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
902 if (range == NULL || (rlen < sizeof(struct isa_range))) {
903 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
905 __ioremap_explicit(phb_io_base_phys,
906 (unsigned long)phb_io_base_virt,
907 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
911 /* From "ISA Binding to 1275"
912 * The ranges property is laid out as an array of elements,
913 * each of which comprises:
914 * cells 0 - 1: an ISA address
915 * cells 2 - 4: a PCI address
916 * (size depending on dev->n_addr_cells)
917 * cell 5: the size of the range
919 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
920 isa_addr = range->isa_addr.a_lo;
921 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
922 range->pci_addr.a_lo;
924 /* Assume these are both zero */
925 if ((pci_addr != 0) || (isa_addr != 0)) {
926 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
931 size = PAGE_ALIGN(range->size);
933 __ioremap_explicit(phb_io_base_phys,
934 (unsigned long) phb_io_base_virt,
935 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
939 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
940 struct device_node *dev, int prim)
942 unsigned int *ranges, pci_space;
946 struct resource *res;
947 int np, na = prom_n_addr_cells(dev);
948 unsigned long pci_addr, cpu_phys_addr;
952 /* From "PCI Binding to 1275"
953 * The ranges property is laid out as an array of elements,
954 * each of which comprises:
955 * cells 0 - 2: a PCI address
956 * cells 3 or 3+4: a CPU physical address
957 * (size depending on dev->n_addr_cells)
958 * cells 4+5 or 5+6: the size of the range
960 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
963 hose->io_base_phys = 0;
964 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
966 pci_space = ranges[0];
967 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
969 cpu_phys_addr = ranges[3];
971 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
973 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
978 /* Now consume following elements while they are contiguous */
979 while (rlen >= np * sizeof(unsigned int)) {
980 unsigned long addr, phys;
982 if (ranges[0] != pci_space)
984 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
987 phys = (phys << 32) | ranges[4];
988 if (addr != pci_addr + size ||
989 phys != cpu_phys_addr + size)
992 size += ((unsigned long)ranges[na+3] << 32)
995 rlen -= np * sizeof(unsigned int);
998 switch ((pci_space >> 24) & 0x3) {
999 case 1: /* I/O space */
1000 hose->io_base_phys = cpu_phys_addr;
1001 hose->pci_io_size = size;
1003 res = &hose->io_resource;
1004 res->flags = IORESOURCE_IO;
1005 res->start = pci_addr;
1006 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
1007 res->start, res->start + size - 1);
1009 case 2: /* memory space */
1011 while (memno < 3 && hose->mem_resources[memno].flags)
1015 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
1017 res = &hose->mem_resources[memno];
1018 res->flags = IORESOURCE_MEM;
1019 res->start = cpu_phys_addr;
1020 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
1021 res->start, res->start + size - 1);
1026 res->name = dev->full_name;
1027 res->end = res->start + size - 1;
1029 res->sibling = NULL;
1035 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
1037 unsigned long size = hose->pci_io_size;
1038 unsigned long io_virt_offset;
1039 struct resource *res;
1040 struct device_node *isa_dn;
1042 hose->io_base_virt = reserve_phb_iospace(size);
1043 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1044 hose->global_number, hose->io_base_phys,
1045 (unsigned long) hose->io_base_virt);
1048 pci_io_base = (unsigned long)hose->io_base_virt;
1049 isa_dn = of_find_node_by_type(NULL, "isa");
1051 isa_io_base = pci_io_base;
1052 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1053 hose->io_base_virt);
1054 of_node_put(isa_dn);
1058 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1059 res = &hose->io_resource;
1060 res->start += io_virt_offset;
1061 res->end += io_virt_offset;
1064 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1067 unsigned long size = hose->pci_io_size;
1068 unsigned long io_virt_offset;
1069 struct resource *res;
1071 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
1072 _PAGE_NO_CACHE | _PAGE_GUARDED);
1073 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1074 hose->global_number, hose->io_base_phys,
1075 (unsigned long) hose->io_base_virt);
1078 pci_io_base = (unsigned long)hose->io_base_virt;
1080 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1081 res = &hose->io_resource;
1082 res->start += io_virt_offset;
1083 res->end += io_virt_offset;
1087 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1088 unsigned long *start_virt, unsigned long *size)
1090 struct pci_controller *hose = pci_bus_to_host(bus);
1091 struct pci_bus_region region;
1092 struct resource *res;
1095 res = bus->resource[0];
1096 pcibios_resource_to_bus(bus->self, ®ion, res);
1097 *start_phys = hose->io_base_phys + region.start;
1098 *start_virt = (unsigned long) hose->io_base_virt +
1100 if (region.end > region.start)
1101 *size = region.end - region.start + 1;
1103 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1104 __FUNCTION__, region.start, region.end);
1110 res = &hose->io_resource;
1111 *start_phys = hose->io_base_phys;
1112 *start_virt = (unsigned long) hose->io_base_virt;
1113 if (res->end > res->start)
1114 *size = res->end - res->start + 1;
1116 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1117 __FUNCTION__, res->start, res->end);
1125 int unmap_bus_range(struct pci_bus *bus)
1127 unsigned long start_phys;
1128 unsigned long start_virt;
1132 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1136 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1138 if (iounmap_explicit((void __iomem *) start_virt, size))
1143 EXPORT_SYMBOL(unmap_bus_range);
1145 int remap_bus_range(struct pci_bus *bus)
1147 unsigned long start_phys;
1148 unsigned long start_virt;
1152 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1157 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1159 if (start_phys == 0)
1161 printk(KERN_DEBUG "mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1162 if (__ioremap_explicit(start_phys, start_virt, size,
1163 _PAGE_NO_CACHE | _PAGE_GUARDED))
1168 EXPORT_SYMBOL(remap_bus_range);
1170 static void phbs_remap_io(void)
1172 struct pci_controller *hose, *tmp;
1174 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1175 remap_bus_range(hose->bus);
1178 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1180 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1181 unsigned long offset;
1183 if (res->flags & IORESOURCE_IO) {
1184 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1186 res->start += offset;
1188 } else if (res->flags & IORESOURCE_MEM) {
1189 res->start += hose->pci_mem_offset;
1190 res->end += hose->pci_mem_offset;
1194 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1195 struct pci_bus *bus)
1197 /* Update device resources. */
1200 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1201 if (dev->resource[i].flags)
1202 fixup_resource(&dev->resource[i], dev);
1204 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1207 static void __devinit do_bus_setup(struct pci_bus *bus)
1209 struct pci_dev *dev;
1211 ppc_md.iommu_bus_setup(bus);
1213 list_for_each_entry(dev, &bus->devices, bus_list)
1214 ppc_md.iommu_dev_setup(dev);
1216 if (ppc_md.irq_bus_setup)
1217 ppc_md.irq_bus_setup(bus);
1220 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1222 struct pci_dev *dev = bus->self;
1224 if (dev && pci_probe_only &&
1225 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1226 /* This is a subordinate bridge */
1228 pci_read_bridge_bases(bus);
1229 pcibios_fixup_device_resources(dev, bus);
1234 if (!pci_probe_only)
1237 list_for_each_entry(dev, &bus->devices, bus_list)
1238 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1239 pcibios_fixup_device_resources(dev, bus);
1241 EXPORT_SYMBOL(pcibios_fixup_bus);
1244 * Reads the interrupt pin to determine if interrupt is use by card.
1245 * If the interrupt is used, then gets the interrupt line from the
1246 * openfirmware and sets it in the pci_dev and pci_config line.
1248 int pci_read_irq_line(struct pci_dev *pci_dev)
1253 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1255 if (of_irq_map_pci(pci_dev, &oirq)) {
1256 DBG(" -> failed !\n");
1260 DBG(" -> got one, spec %d cells (0x%08x...) on %s\n",
1261 oirq.size, oirq.specifier[0], oirq.controller->full_name);
1263 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, oirq.size);
1264 if(virq == NO_IRQ) {
1265 DBG(" -> failed to map !\n");
1268 pci_dev->irq = virq;
1269 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
1273 EXPORT_SYMBOL(pci_read_irq_line);
1275 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1276 const struct resource *rsrc,
1277 u64 *start, u64 *end)
1279 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1280 unsigned long offset = 0;
1285 if (rsrc->flags & IORESOURCE_IO)
1286 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1289 *start = rsrc->start + offset;
1290 *end = rsrc->end + offset;
1293 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
1298 struct pci_controller *hose, *tmp;
1299 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1300 if (hose->arch_data == node)
1302 node = node->parent;
1307 #endif /* CONFIG_PPC_MULTIPLATFORM */
1309 unsigned long pci_address_to_pio(phys_addr_t address)
1311 struct pci_controller *hose, *tmp;
1313 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1314 if (address >= hose->io_base_phys &&
1315 address < (hose->io_base_phys + hose->pci_io_size)) {
1316 unsigned long base =
1317 (unsigned long)hose->io_base_virt - pci_io_base;
1318 return base + (address - hose->io_base_phys);
1321 return (unsigned int)-1;
1323 EXPORT_SYMBOL_GPL(pci_address_to_pio);
1326 #define IOBASE_BRIDGE_NUMBER 0
1327 #define IOBASE_MEMORY 1
1329 #define IOBASE_ISA_IO 3
1330 #define IOBASE_ISA_MEM 4
1332 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1333 unsigned long in_devfn)
1335 struct pci_controller* hose;
1336 struct list_head *ln;
1337 struct pci_bus *bus = NULL;
1338 struct device_node *hose_node;
1340 /* Argh ! Please forgive me for that hack, but that's the
1341 * simplest way to get existing XFree to not lockup on some
1342 * G5 machines... So when something asks for bus 0 io base
1343 * (bus 0 is HT root), we return the AGP one instead.
1345 if (machine_is_compatible("MacRISC4"))
1349 /* That syscall isn't quite compatible with PCI domains, but it's
1350 * used on pre-domains setup. We return the first match
1353 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1354 bus = pci_bus_b(ln);
1355 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1359 if (bus == NULL || bus->sysdata == NULL)
1362 hose_node = (struct device_node *)bus->sysdata;
1363 hose = PCI_DN(hose_node)->phb;
1366 case IOBASE_BRIDGE_NUMBER:
1367 return (long)hose->first_busno;
1369 return (long)hose->pci_mem_offset;
1371 return (long)hose->io_base_phys;
1373 return (long)isa_io_base;
1374 case IOBASE_ISA_MEM:
1382 int pcibus_to_node(struct pci_bus *bus)
1384 struct pci_controller *phb = pci_bus_to_host(bus);
1387 EXPORT_SYMBOL(pcibus_to_node);