2 * P4080DS Device Tree Source
4 * Copyright 2009 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "fsl,P4080DS";
16 compatible = "fsl,P4080DS";
43 cpu0: PowerPC,4080@0 {
46 next-level-cache = <&L2_0>;
50 cpu1: PowerPC,4080@1 {
53 next-level-cache = <&L2_1>;
57 cpu2: PowerPC,4080@2 {
60 next-level-cache = <&L2_2>;
64 cpu3: PowerPC,4080@3 {
67 next-level-cache = <&L2_3>;
71 cpu4: PowerPC,4080@4 {
74 next-level-cache = <&L2_4>;
78 cpu5: PowerPC,4080@5 {
81 next-level-cache = <&L2_5>;
85 cpu6: PowerPC,4080@6 {
88 next-level-cache = <&L2_6>;
92 cpu7: PowerPC,4080@7 {
95 next-level-cache = <&L2_7>;
102 device_type = "memory";
106 #address-cells = <1>;
109 compatible = "simple-bus";
110 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
111 reg = <0xf 0xfe000000 0 0x00001000>;
114 compatible = "fsl,corenet-law";
119 memory-controller@8000 {
120 compatible = "fsl,p4080-memory-controller";
121 reg = <0x8000 0x1000>;
122 interrupt-parent = <&mpic>;
123 interrupts = <0x12 2>;
126 memory-controller@9000 {
127 compatible = "fsl,p4080-memory-controller";
128 reg = <0x9000 0x1000>;
129 interrupt-parent = <&mpic>;
130 interrupts = <0x12 2>;
134 compatible = "fsl,corenet-cf";
135 reg = <0x18000 0x1000>;
136 fsl,ccf-num-csdids = <32>;
137 fsl,ccf-num-snoopids = <32>;
141 compatible = "fsl,p4080-pamu";
142 reg = <0x20000 0x10000>;
144 interrupt-parent = <&mpic>;
148 interrupt-controller;
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 reg = <0x40000 0x40000>;
152 compatible = "chrp,open-pic";
153 device_type = "open-pic";
157 #address-cells = <1>;
159 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
160 reg = <0x100300 0x4>;
161 ranges = <0x0 0x100100 0x200>;
164 compatible = "fsl,p4080-dma-channel",
165 "fsl,eloplus-dma-channel";
168 interrupt-parent = <&mpic>;
172 compatible = "fsl,p4080-dma-channel",
173 "fsl,eloplus-dma-channel";
176 interrupt-parent = <&mpic>;
180 compatible = "fsl,p4080-dma-channel",
181 "fsl,eloplus-dma-channel";
184 interrupt-parent = <&mpic>;
188 compatible = "fsl,p4080-dma-channel",
189 "fsl,eloplus-dma-channel";
192 interrupt-parent = <&mpic>;
198 #address-cells = <1>;
200 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
201 reg = <0x101300 0x4>;
202 ranges = <0x0 0x101100 0x200>;
205 compatible = "fsl,p4080-dma-channel",
206 "fsl,eloplus-dma-channel";
209 interrupt-parent = <&mpic>;
213 compatible = "fsl,p4080-dma-channel",
214 "fsl,eloplus-dma-channel";
217 interrupt-parent = <&mpic>;
221 compatible = "fsl,p4080-dma-channel",
222 "fsl,eloplus-dma-channel";
225 interrupt-parent = <&mpic>;
229 compatible = "fsl,p4080-dma-channel",
230 "fsl,eloplus-dma-channel";
233 interrupt-parent = <&mpic>;
240 #address-cells = <1>;
242 compatible = "fsl,espi";
243 reg = <0x110000 0x1000>;
244 interrupts = <53 0x2>;
245 interrupt-parent = <&mpic>;
246 espi,num-ss-bits = <4>;
250 #address-cells = <1>;
252 compatible = "fsl,espi-flash";
254 linux,modalias = "fsl_m25p80";
255 spi-max-frequency = <40000000>; /* input clock */
258 reg = <0x00000000 0x00100000>;
263 reg = <0x00100000 0x00500000>;
268 reg = <0x00600000 0x00100000>;
272 label = "file system";
273 reg = <0x00700000 0x00900000>;
279 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
280 reg = <0x114000 0x1000>;
282 interrupt-parent = <&mpic>;
286 #address-cells = <1>;
289 compatible = "fsl-i2c";
290 reg = <0x118000 0x100>;
292 interrupt-parent = <&mpic>;
297 #address-cells = <1>;
300 compatible = "fsl-i2c";
301 reg = <0x118100 0x100>;
303 interrupt-parent = <&mpic>;
306 compatible = "at24,24c256";
310 compatible = "at24,24c256";
314 compatible = "dallas,ds3232";
316 interrupts = <0 0x1>;
317 interrupt-parent = <&mpic>;
322 #address-cells = <1>;
325 compatible = "fsl-i2c";
326 reg = <0x119000 0x100>;
328 interrupt-parent = <&mpic>;
333 #address-cells = <1>;
336 compatible = "fsl-i2c";
337 reg = <0x119100 0x100>;
339 interrupt-parent = <&mpic>;
343 serial0: serial@11c500 {
345 device_type = "serial";
346 compatible = "ns16550";
347 reg = <0x11c500 0x100>;
348 clock-frequency = <0>;
350 interrupt-parent = <&mpic>;
353 serial1: serial@11c600 {
355 device_type = "serial";
356 compatible = "ns16550";
357 reg = <0x11c600 0x100>;
358 clock-frequency = <0>;
360 interrupt-parent = <&mpic>;
363 serial2: serial@11d500 {
365 device_type = "serial";
366 compatible = "ns16550";
367 reg = <0x11d500 0x100>;
368 clock-frequency = <0>;
370 interrupt-parent = <&mpic>;
373 serial3: serial@11d600 {
375 device_type = "serial";
376 compatible = "ns16550";
377 reg = <0x11d600 0x100>;
378 clock-frequency = <0>;
380 interrupt-parent = <&mpic>;
384 compatible = "fsl,p4080-gpio";
385 reg = <0x130000 0x1000>;
387 interrupt-parent = <&mpic>;
393 compatible = "fsl,p4080-usb2-mph",
394 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
395 reg = <0x210000 0x1000>;
396 #address-cells = <1>;
398 interrupt-parent = <&mpic>;
399 interrupts = <44 0x2>;
404 compatible = "fsl,p4080-usb2-dr",
405 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
406 reg = <0x211000 0x1000>;
407 #address-cells = <1>;
409 interrupt-parent = <&mpic>;
410 interrupts = <45 0x2>;
416 rapidio0: rapidio@ffe0c0000 {
417 #address-cells = <2>;
419 compatible = "fsl,rapidio-delta";
420 reg = <0xf 0xfe0c0000 0 0x20000>;
421 ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
422 interrupt-parent = <&mpic>;
423 /* err_irq bell_outb_irq bell_inb_irq
424 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
425 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
429 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
430 reg = <0xf 0xfe124000 0 0x1000>;
432 #address-cells = <2>;
435 ranges = <0 0 0xf 0xe8000000 0x08000000>;
438 compatible = "cfi-flash";
439 reg = <0 0 0x08000000>;
445 pci0: pcie@ffe200000 {
446 compatible = "fsl,p4080-pcie";
448 #interrupt-cells = <1>;
450 #address-cells = <3>;
451 reg = <0xf 0xfe200000 0 0x1000>;
452 bus-range = <0x0 0xff>;
453 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
454 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
455 clock-frequency = <0x1fca055>;
456 interrupt-parent = <&mpic>;
459 interrupt-map-mask = <0xf800 0 0 7>;
462 0000 0 0 1 &mpic 40 1
470 #address-cells = <3>;
472 ranges = <0x02000000 0 0xe0000000
473 0x02000000 0 0xe0000000
476 0x01000000 0 0x00000000
477 0x01000000 0 0x00000000
482 pci1: pcie@ffe201000 {
483 compatible = "fsl,p4080-pcie";
485 #interrupt-cells = <1>;
487 #address-cells = <3>;
488 reg = <0xf 0xfe201000 0 0x1000>;
489 bus-range = <0 0xff>;
490 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
491 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
492 clock-frequency = <0x1fca055>;
493 interrupt-parent = <&mpic>;
495 interrupt-map-mask = <0xf800 0 0 7>;
498 0000 0 0 1 &mpic 41 1
506 #address-cells = <3>;
508 ranges = <0x02000000 0 0xe0000000
509 0x02000000 0 0xe0000000
512 0x01000000 0 0x00000000
513 0x01000000 0 0x00000000
518 pci2: pcie@ffe202000 {
519 compatible = "fsl,p4080-pcie";
521 #interrupt-cells = <1>;
523 #address-cells = <3>;
524 reg = <0xf 0xfe202000 0 0x1000>;
525 bus-range = <0x0 0xff>;
526 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
527 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
528 clock-frequency = <0x1fca055>;
529 interrupt-parent = <&mpic>;
531 interrupt-map-mask = <0xf800 0 0 7>;
534 0000 0 0 1 &mpic 42 1
536 0000 0 0 3 &mpic 10 1
537 0000 0 0 4 &mpic 11 1
542 #address-cells = <3>;
544 ranges = <0x02000000 0 0xe0000000
545 0x02000000 0 0xe0000000
548 0x01000000 0 0x00000000
549 0x01000000 0 0x00000000