2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/linkage.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/smp.h>
25 #include <linux/kernel_stat.h>
27 #include <asm/errno.h>
28 #include <asm/signal.h>
29 #include <asm/system.h>
33 #include <asm/sibyte/sb1250_regs.h>
34 #include <asm/sibyte/sb1250_int.h>
35 #include <asm/sibyte/sb1250_uart.h>
36 #include <asm/sibyte/sb1250_scd.h>
37 #include <asm/sibyte/sb1250.h>
40 * These are the routines that handle all the low level interrupt stuff.
41 * Actions handled here are: initialization of the interrupt map, requesting of
42 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
46 #ifdef CONFIG_SIBYTE_HAS_LDT
47 extern unsigned long ldt_eoi_space;
50 /* Store the CPU id (not the logical number) */
51 int sb1250_irq_owner[SB1250_NR_IRQS];
53 static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
55 void sb1250_mask_irq(int cpu, int irq)
60 raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
61 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
62 R_IMR_INTERRUPT_MASK));
63 cur_ints |= (((u64) 1) << irq);
64 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65 R_IMR_INTERRUPT_MASK));
66 raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
69 void sb1250_unmask_irq(int cpu, int irq)
74 raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
75 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
76 R_IMR_INTERRUPT_MASK));
77 cur_ints &= ~(((u64) 1) << irq);
78 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
79 R_IMR_INTERRUPT_MASK));
80 raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
84 static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask,
87 int i = 0, old_cpu, cpu, int_on;
88 unsigned int irq = d->irq;
92 i = cpumask_first(mask);
94 /* Convert logical CPU to physical CPU */
95 cpu = cpu_logical_map(i);
97 /* Protect against other affinity changers and IMR manipulation */
98 raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
100 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
101 old_cpu = sb1250_irq_owner[irq];
102 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
103 R_IMR_INTERRUPT_MASK));
104 int_on = !(cur_ints & (((u64) 1) << irq));
106 /* If it was on, mask it */
107 cur_ints |= (((u64) 1) << irq);
108 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
109 R_IMR_INTERRUPT_MASK));
111 sb1250_irq_owner[irq] = cpu;
113 /* unmask for the new CPU */
114 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
115 R_IMR_INTERRUPT_MASK));
116 cur_ints &= ~(((u64) 1) << irq);
117 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
118 R_IMR_INTERRUPT_MASK));
120 raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
126 static void enable_sb1250_irq(struct irq_data *d)
128 unsigned int irq = d->irq;
130 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
134 static void ack_sb1250_irq(struct irq_data *d)
136 unsigned int irq = d->irq;
137 #ifdef CONFIG_SIBYTE_HAS_LDT
141 * If the interrupt was an HT interrupt, now is the time to
142 * clear it. NOTE: we assume the HT bridge was set up to
143 * deliver the interrupts to all CPUs (which makes affinity
144 * changing easier for us)
146 pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
147 R_IMR_LDT_INTERRUPT)));
148 pending &= ((u64)1 << (irq));
151 for (i=0; i<NR_CPUS; i++) {
154 cpu = cpu_logical_map(i);
159 * Clear for all CPUs so an affinity switch
160 * doesn't find an old status
162 __raw_writeq(pending,
163 IOADDR(A_IMR_REGISTER(cpu,
164 R_IMR_LDT_INTERRUPT_CLR)));
168 * Generate EOI. For Pass 1 parts, EOI is a nop. For
169 * Pass 2, the LDT world may be edge-triggered, but
170 * this EOI shouldn't hurt. If they are
171 * level-sensitive, the EOI is required.
173 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
176 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
179 static struct irq_chip sb1250_irq_type = {
180 .name = "SB1250-IMR",
181 .irq_mask_ack = ack_sb1250_irq,
182 .irq_unmask = enable_sb1250_irq,
184 .irq_set_affinity = sb1250_set_affinity
188 void __init init_sb1250_irqs(void)
192 for (i = 0; i < SB1250_NR_IRQS; i++) {
193 set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
194 sb1250_irq_owner[i] = 0;
200 * arch_init_irq is called early in the boot sequence from init/main.c via
201 * init_IRQ. It is responsible for setting up the interrupt mapper and
202 * installing the handler that will be responsible for dispatching interrupts
203 * to the "right" place.
206 * For now, map all interrupts to IP[2]. We could save
207 * some cycles by parceling out system interrupts to different
208 * IP lines, but keep it simple for bringup. We'll also direct
209 * all interrupts to a single CPU; we should probably route
210 * PCI and LDT to one cpu and everything else to the other
211 * to balance the load a bit.
213 * On the second cpu, everything is set to IP5, which is
214 * ignored, EXCEPT the mailbox interrupt. That one is
215 * set to IP[2] so it is handled. This is needed so we
216 * can do cross-cpu function calls, as required by SMP
219 #define IMR_IP2_VAL K_INT_MAP_I0
220 #define IMR_IP3_VAL K_INT_MAP_I1
221 #define IMR_IP4_VAL K_INT_MAP_I2
222 #define IMR_IP5_VAL K_INT_MAP_I3
223 #define IMR_IP6_VAL K_INT_MAP_I4
225 void __init arch_init_irq(void)
230 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
231 STATUSF_IP1 | STATUSF_IP0;
233 /* Default everything to IP2 */
234 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
235 __raw_writeq(IMR_IP2_VAL,
236 IOADDR(A_IMR_REGISTER(0,
237 R_IMR_INTERRUPT_MAP_BASE) +
239 __raw_writeq(IMR_IP2_VAL,
240 IOADDR(A_IMR_REGISTER(1,
241 R_IMR_INTERRUPT_MAP_BASE) +
248 * Map the high 16 bits of the mailbox registers to IP[3], for
252 __raw_writeq(IMR_IP3_VAL,
253 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
254 (K_INT_MBOX_0 << 3)));
255 __raw_writeq(IMR_IP3_VAL,
256 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
257 (K_INT_MBOX_0 << 3)));
259 /* Clear the mailboxes. The firmware may leave them dirty */
260 __raw_writeq(0xffffffffffffffffULL,
261 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
262 __raw_writeq(0xffffffffffffffffULL,
263 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
265 /* Mask everything except the mailbox registers for both cpus */
266 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
267 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
268 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
271 * Note that the timer interrupts are also mapped, but this is
272 * done in sb1250_time_init(). Also, the profiling driver
273 * does its own management of IP7.
276 /* Enable necessary IPs, disable the rest */
277 change_c0_status(ST0_IM, imask);
280 extern void sb1250_mailbox_interrupt(void);
282 static inline void dispatch_ip2(void)
284 unsigned int cpu = smp_processor_id();
285 unsigned long long mask;
288 * Default...we've hit an IP[2] interrupt, which means we've got to
289 * check the 1250 interrupt registers to figure out what to do. Need
290 * to detect which CPU we're on, now that smp_affinity is supported.
292 mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
293 R_IMR_INTERRUPT_STATUS_BASE)));
295 do_IRQ(fls64(mask) - 1);
298 asmlinkage void plat_irq_dispatch(void)
300 unsigned int cpu = smp_processor_id();
301 unsigned int pending;
304 * What a pain. We have to be really careful saving the upper 32 bits
305 * of any * register across function calls if we don't want them
306 * trashed--since were running in -o32, the calling routing never saves
307 * the full 64 bits of a register across a function call. Being the
308 * interrupt handler, we're guaranteed that interrupts are disabled
309 * during this code so we don't have to worry about random interrupts
310 * blasting the high 32 bits.
313 pending = read_c0_cause() & read_c0_status() & ST0_IM;
315 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
316 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
317 else if (pending & CAUSEF_IP4)
318 do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
321 else if (pending & CAUSEF_IP3)
322 sb1250_mailbox_interrupt();
325 else if (pending & CAUSEF_IP2)
328 spurious_interrupt();