2 * Alchemy PCI host mode support.
4 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
7 * Support for all devices (greater than 16) added by David Gathright.
10 #include <linux/export.h>
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/platform_device.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/vmalloc.h>
18 #include <asm/mach-au1x00/au1000.h>
20 #ifdef CONFIG_DEBUG_PCI
21 #define DBG(x...) printk(KERN_DEBUG x)
23 #define DBG(x...) do {} while (0)
26 #define PCI_ACCESS_READ 0
27 #define PCI_ACCESS_WRITE 1
29 struct alchemy_pci_context {
30 struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
31 void __iomem *regs; /* ctrl base */
32 /* tools for wired entry for config space access */
33 unsigned long last_elo0;
34 unsigned long last_elo1;
36 struct vm_struct *pci_cfg_vm;
40 int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
41 int (*board_pci_idsel)(unsigned int devsel, int assert);
44 /* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
45 * in arch/mips/alchemy/common/setup.c
47 static struct resource alchemy_pci_def_memres = {
48 .start = ALCHEMY_PCI_MEMWIN_START,
49 .end = ALCHEMY_PCI_MEMWIN_END,
50 .name = "PCI memory space",
51 .flags = IORESOURCE_MEM
54 static struct resource alchemy_pci_def_iores = {
55 .start = ALCHEMY_PCI_IOWIN_START,
56 .end = ALCHEMY_PCI_IOWIN_END,
57 .name = "PCI IO space",
58 .flags = IORESOURCE_IO
61 static void mod_wired_entry(int entry, unsigned long entrylo0,
62 unsigned long entrylo1, unsigned long entryhi,
63 unsigned long pagemask)
65 unsigned long old_pagemask;
66 unsigned long old_ctx;
68 /* Save old context and create impossible VPN2 value */
69 old_ctx = read_c0_entryhi() & 0xff;
70 old_pagemask = read_c0_pagemask();
71 write_c0_index(entry);
72 write_c0_pagemask(pagemask);
73 write_c0_entryhi(entryhi);
74 write_c0_entrylo0(entrylo0);
75 write_c0_entrylo1(entrylo1);
77 write_c0_entryhi(old_ctx);
78 write_c0_pagemask(old_pagemask);
81 static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx)
83 ctx->wired_entry = read_c0_wired();
84 add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
85 ctx->last_elo0 = ctx->last_elo1 = ~0;
88 static int config_access(unsigned char access_type, struct pci_bus *bus,
89 unsigned int dev_fn, unsigned char where, u32 *data)
91 struct alchemy_pci_context *ctx = bus->sysdata;
92 unsigned int device = PCI_SLOT(dev_fn);
93 unsigned int function = PCI_FUNC(dev_fn);
94 unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r;
95 int error = PCIBIOS_SUCCESSFUL;
102 /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
103 * on resume, clearing our wired entry. Unfortunately the ->resume()
104 * callback is called way way way too late (and ->suspend() too early)
105 * to have them destroy and recreate it. Instead just test if c0_wired
106 * is now lower than the index we retrieved before suspending and then
107 * recreate the entry if necessary. Of course this is totally bonkers
108 * and breaks as soon as someone else adds another wired entry somewhere
109 * else. Anyone have any ideas how to handle this better?
111 if (unlikely(read_c0_wired() < ctx->wired_entry))
112 alchemy_pci_wired_entry(ctx);
114 local_irq_save(flags);
115 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
116 r |= PCI_STATCMD_STATUS(0x2000);
117 __raw_writel(r, ctx->regs + PCI_REG_STATCMD);
120 /* Allow board vendors to implement their own off-chip IDSEL.
121 * If it doesn't succeed, may as well bail out at this point.
123 if (ctx->board_pci_idsel(device, 1) == 0) {
125 local_irq_restore(flags);
129 /* Setup the config window */
130 if (bus->number == 0)
131 cfg_base = (1 << device) << 11;
133 cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
135 /* Setup the lower bits of the 36-bit address */
136 offset = (function << 8) | (where & ~0x3);
137 /* Pick up any address that falls below the page mask */
138 offset |= cfg_base & ~PAGE_MASK;
141 cfg_base = cfg_base & PAGE_MASK;
143 /* To improve performance, if the current device is the same as
144 * the last device accessed, we don't touch the TLB.
146 entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
147 entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
148 if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) {
149 mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1,
150 (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
151 ctx->last_elo0 = entryLo0;
152 ctx->last_elo1 = entryLo1;
155 if (access_type == PCI_ACCESS_WRITE)
156 __raw_writel(*data, ctx->pci_cfg_vm->addr + offset);
158 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset);
161 DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n",
162 access_type, bus->number, device, where, *data, offset);
164 /* check for errors, master abort */
165 status = __raw_readl(ctx->regs + PCI_REG_STATCMD);
166 if (status & (1 << 29)) {
169 DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d",
170 access_type, bus->number, device);
171 } else if ((status >> 28) & 0xf) {
172 DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
173 device, (status >> 28) & 0xf);
176 __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD);
182 /* Take away the IDSEL. */
183 (void)ctx->board_pci_idsel(device, 0);
185 local_irq_restore(flags);
189 static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
193 int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
203 static int read_config_word(struct pci_bus *bus, unsigned int devfn,
207 int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
211 *val = data & 0xffff;
215 static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
218 return config_access(PCI_ACCESS_READ, bus, devfn, where, val);
221 static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
226 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
229 data = (data & ~(0xff << ((where & 3) << 3))) |
230 (val << ((where & 3) << 3));
232 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
235 return PCIBIOS_SUCCESSFUL;
238 static int write_config_word(struct pci_bus *bus, unsigned int devfn,
243 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
246 data = (data & ~(0xffff << ((where & 3) << 3))) |
247 (val << ((where & 3) << 3));
249 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
252 return PCIBIOS_SUCCESSFUL;
255 static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
258 return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val);
261 static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn,
262 int where, int size, u32 *val)
267 int rc = read_config_byte(bus, devfn, where, &_val);
274 int rc = read_config_word(bus, devfn, where, &_val);
280 return read_config_dword(bus, devfn, where, val);
284 static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn,
285 int where, int size, u32 val)
289 return write_config_byte(bus, devfn, where, (u8) val);
291 return write_config_word(bus, devfn, where, (u16) val);
293 return write_config_dword(bus, devfn, where, val);
297 static struct pci_ops alchemy_pci_ops = {
298 .read = alchemy_pci_read,
299 .write = alchemy_pci_write,
302 static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
304 return 1; /* success */
307 static int __devinit alchemy_pci_probe(struct platform_device *pdev)
309 struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
310 struct alchemy_pci_context *ctx;
311 void __iomem *virt_io;
316 /* need at least PCI IRQ mapping table */
318 dev_err(&pdev->dev, "need platform data for PCI setup\n");
323 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
325 dev_err(&pdev->dev, "no memory for pcictl context\n");
330 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
332 dev_err(&pdev->dev, "no pcictl ctrl regs resource\n");
337 if (!request_mem_region(r->start, resource_size(r), pdev->name)) {
338 dev_err(&pdev->dev, "cannot claim pci regs\n");
343 ctx->regs = ioremap_nocache(r->start, resource_size(r));
345 dev_err(&pdev->dev, "cannot map pci regs\n");
350 /* map parts of the PCI IO area */
351 /* REVISIT: if this changes with a newer variant (doubt it) make this
352 * a platform resource.
354 virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000);
356 dev_err(&pdev->dev, "cannot remap pci io space\n");
360 ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
362 #ifdef CONFIG_DMA_NONCOHERENT
363 /* Au1500 revisions older than AD have borked coherent PCI */
364 if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
365 (read_c0_prid() < 0x01030202)) {
366 val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
367 val |= PCI_CONFIG_NC;
368 __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
370 dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n");
374 if (pd->board_map_irq)
375 ctx->board_map_irq = pd->board_map_irq;
377 if (pd->board_pci_idsel)
378 ctx->board_pci_idsel = pd->board_pci_idsel;
380 ctx->board_pci_idsel = alchemy_pci_def_idsel;
382 /* fill in relevant pci_controller members */
383 ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops;
384 ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres;
385 ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores;
387 /* we can't ioremap the entire pci config space because it's too large,
388 * nor can we dynamically ioremap it because some drivers use the
389 * PCI config routines from within atomic contex and that becomes a
390 * problem in get_vm_area(). Instead we use one wired TLB entry to
391 * handle all config accesses for all busses.
393 ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
394 if (!ctx->pci_cfg_vm) {
395 dev_err(&pdev->dev, "unable to get vm area\n");
399 ctx->wired_entry = 8192; /* impossibly high value */
401 set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
403 /* board may want to modify bits in the config register, do it now */
404 val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
405 val &= ~pd->pci_cfg_clr;
406 val |= pd->pci_cfg_set;
407 val &= ~PCI_CONFIG_PD; /* clear disable bit */
408 __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
411 platform_set_drvdata(pdev, ctx);
412 register_pci_controller(&ctx->alchemy_pci_ctrl);
421 release_mem_region(r->start, resource_size(r));
430 /* save PCI controller register contents. */
431 static int alchemy_pci_suspend(struct device *dev)
433 struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
435 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
436 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
437 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
438 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
439 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
440 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
441 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
442 ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
443 ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
444 ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
445 ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
446 ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
451 static int alchemy_pci_resume(struct device *dev)
453 struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
455 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
456 __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
457 __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
458 __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
459 __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
460 __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
461 __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
462 __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
463 __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
464 __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
465 __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
467 __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
473 static const struct dev_pm_ops alchemy_pci_pmops = {
474 .suspend = alchemy_pci_suspend,
475 .resume = alchemy_pci_resume,
478 #define ALCHEMY_PCICTL_PM (&alchemy_pci_pmops)
481 #define ALCHEMY_PCICTL_PM NULL
484 static struct platform_driver alchemy_pcictl_driver = {
485 .probe = alchemy_pci_probe,
487 .name = "alchemy-pci",
488 .owner = THIS_MODULE,
489 .pm = ALCHEMY_PCICTL_PM,
493 static int __init alchemy_pci_init(void)
495 /* Au1500/Au1550 have PCI */
496 switch (alchemy_get_cputype()) {
497 case ALCHEMY_CPU_AU1500:
498 case ALCHEMY_CPU_AU1550:
499 return platform_driver_register(&alchemy_pcictl_driver);
503 arch_initcall(alchemy_pci_init);
506 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
508 struct alchemy_pci_context *ctx = dev->sysdata;
509 if (ctx && ctx->board_map_irq)
510 return ctx->board_map_irq(dev, slot, pin);
514 int pcibios_plat_dev_init(struct pci_dev *dev)