2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
11 #ifndef _ASM_PROCESSOR_H
12 #define _ASM_PROCESSOR_H
14 #include <linux/cpumask.h>
15 #include <linux/threads.h>
17 #include <asm/cachectl.h>
19 #include <asm/cpu-info.h>
20 #include <asm/mipsregs.h>
21 #include <asm/prefetch.h>
22 #include <asm/system.h>
25 * Return current * instruction pointer ("program counter").
27 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
30 * System setup and hardware flags..
32 extern void (*cpu_wait)(void);
34 extern unsigned int vced_count, vcei_count;
37 * MIPS does have an arch_pick_mmap_layout()
39 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
42 * A special page (the vdso) is mapped into all processes at the very
43 * top of the virtual memory space.
45 #define SPECIAL_PAGES_SIZE PAGE_SIZE
49 * User space process size: 2GB. This is hardcoded into a few places,
50 * so don't change it unless you know what you are doing.
52 #define TASK_SIZE 0x7fff8000UL
53 #define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
56 * This decides where the kernel will search for a free chunk of vm
57 * space during mmap's.
59 #define TASK_UNMAPPED_BASE ((TASK_SIZE / 3) & ~(PAGE_SIZE))
61 #define TASK_IS_32BIT_ADDR 1
67 * User space process size: 1TB. This is hardcoded into a few places,
68 * so don't change it unless you know what you are doing. TASK_SIZE
69 * is limited to 1TB by the R4000 architecture; R10000 and better can
70 * support 16TB; the architectural reserve for future expansion is
73 #define TASK_SIZE32 0x7fff8000UL
74 #define TASK_SIZE 0x10000000000UL
76 (((test_thread_flag(TIF_32BIT_ADDR) ? \
77 TASK_SIZE32 : TASK_SIZE) & PAGE_MASK) - SPECIAL_PAGES_SIZE)
80 * This decides where the kernel will search for a free chunk of vm
81 * space during mmap's.
83 #define TASK_UNMAPPED_BASE \
84 (test_thread_flag(TIF_32BIT_ADDR) ? \
85 PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
86 #define TASK_SIZE_OF(tsk) \
87 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
89 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
94 #define STACK_TOP_MAX TASK_SIZE
97 #define NUM_FPU_REGS 32
99 typedef __u64 fpureg_t;
102 * It would be nice to add some more fields for emulator statistics, but there
103 * are a number of fixed offsets in offset.h and elsewhere that would have to
104 * be recalculated by hand. So the additional information will be private to
105 * the FPU emulator for now. See asm-mips/fpu_emulator.h.
108 struct mips_fpu_struct {
109 fpureg_t fpr[NUM_FPU_REGS];
113 #define NUM_DSP_REGS 6
115 typedef __u32 dspreg_t;
117 struct mips_dsp_state {
118 dspreg_t dspr[NUM_DSP_REGS];
119 unsigned int dspcontrol;
122 #define INIT_CPUMASK { \
126 struct mips3264_watch_reg_state {
127 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
128 64 bit kernel. We use unsigned long as it has the same
130 unsigned long watchlo[NUM_WATCH_REGS];
131 /* Only the mask and IRW bits from watchhi. */
132 u16 watchhi[NUM_WATCH_REGS];
135 union mips_watch_reg_state {
136 struct mips3264_watch_reg_state mips3264;
139 #ifdef CONFIG_CPU_CAVIUM_OCTEON
141 struct octeon_cop2_state {
142 /* DMFC2 rt, 0x0201 */
143 unsigned long cop2_crc_iv;
144 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
145 unsigned long cop2_crc_length;
146 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
147 unsigned long cop2_crc_poly;
148 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
149 unsigned long cop2_llm_dat[2];
150 /* DMFC2 rt, 0x0084 */
151 unsigned long cop2_3des_iv;
152 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
153 unsigned long cop2_3des_key[3];
154 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
155 unsigned long cop2_3des_result;
156 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
157 unsigned long cop2_aes_inp0;
158 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
159 unsigned long cop2_aes_iv[2];
160 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
162 unsigned long cop2_aes_key[4];
163 /* DMFC2 rt, 0x0110 */
164 unsigned long cop2_aes_keylen;
165 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
166 unsigned long cop2_aes_result[2];
167 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
168 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
169 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
170 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
171 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
172 unsigned long cop2_hsh_datw[15];
173 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
174 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
175 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
176 unsigned long cop2_hsh_ivw[8];
177 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
178 unsigned long cop2_gfm_mult[2];
179 /* DMFC2 rt, 0x025E - Pass2 */
180 unsigned long cop2_gfm_poly;
181 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
182 unsigned long cop2_gfm_result[2];
184 #define INIT_OCTEON_COP2 {0,}
186 struct octeon_cvmseg_state {
187 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
188 [cpu_dcache_line_size() / sizeof(unsigned long)];
197 #define ARCH_MIN_TASKALIGN 8
202 * If you change thread_struct remember to change the #defines below too!
204 struct thread_struct {
205 /* Saved main processor registers. */
207 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
208 unsigned long reg29, reg30, reg31;
210 /* Saved cp0 stuff. */
211 unsigned long cp0_status;
213 /* Saved fpu/fpu emulator stuff. */
214 struct mips_fpu_struct fpu;
215 #ifdef CONFIG_MIPS_MT_FPAFF
216 /* Emulated instruction count */
217 unsigned long emulated_fp;
218 /* Saved per-thread scheduler affinity mask */
219 cpumask_t user_cpus_allowed;
220 #endif /* CONFIG_MIPS_MT_FPAFF */
222 /* Saved state of the DSP ASE, if available. */
223 struct mips_dsp_state dsp;
225 /* Saved watch register state, if available. */
226 union mips_watch_reg_state watch;
228 /* Other stuff associated with the thread. */
229 unsigned long cp0_badvaddr; /* Last user fault */
230 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
231 unsigned long error_code;
232 unsigned long trap_no;
233 unsigned long irix_trampoline; /* Wheee... */
234 unsigned long irix_oldctx;
235 #ifdef CONFIG_CPU_CAVIUM_OCTEON
236 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
237 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
239 struct mips_abi *abi;
242 #ifdef CONFIG_MIPS_MT_FPAFF
245 .user_cpus_allowed = INIT_CPUMASK,
248 #endif /* CONFIG_MIPS_MT_FPAFF */
250 #ifdef CONFIG_CPU_CAVIUM_OCTEON
251 #define OCTEON_INIT \
252 .cp2 = INIT_OCTEON_COP2,
255 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
257 #define INIT_THREAD { \
259 * Saved main processor registers \
277 * Saved FPU/FPU emulator stuff \
284 * FPU affinity state (null if not FPAFF) \
295 * saved watch register stuff \
297 .watch = {{{0,},},}, \
299 * Other stuff associated with the process \
305 .irix_trampoline = 0, \
308 * Cavium Octeon specifics (null if not Octeon) \
315 /* Free all resources held by a thread. */
316 #define release_thread(thread) do { } while(0)
318 /* Prepare to copy thread state - unlazy all lazy status */
319 #define prepare_to_copy(tsk) do { } while (0)
321 extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
323 extern unsigned long thread_saved_pc(struct task_struct *tsk);
326 * Do necessary setup to start up a newly executed thread.
328 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
330 unsigned long get_wchan(struct task_struct *p);
332 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
333 THREAD_SIZE - 32 - sizeof(struct pt_regs))
334 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
335 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
336 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
337 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
339 #define cpu_relax() barrier()
342 * Return_address is a replacement for __builtin_return_address(count)
343 * which on certain architectures cannot reasonably be implemented in GCC
344 * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
345 * Note that __builtin_return_address(x>=1) is forbidden because GCC
346 * aborts compilation on some CPUs. It's simply not possible to unwind
347 * some CPU's stackframes.
349 * __builtin_return_address works only for non-leaf functions. We avoid the
350 * overhead of a function call by forcing the compiler to save the return
351 * address register on the stack.
353 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
355 #ifdef CONFIG_CPU_HAS_PREFETCH
357 #define ARCH_HAS_PREFETCH
358 #define prefetch(x) __builtin_prefetch((x), 0, 1)
360 #define ARCH_HAS_PREFETCHW
361 #define prefetchw(x) __builtin_prefetch((x), 1, 1)
365 #endif /* _ASM_PROCESSOR_H */