2 * Switch a MMU context.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
11 #ifndef _ASM_MMU_CONTEXT_H
12 #define _ASM_MMU_CONTEXT_H
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
17 #include <linux/slab.h>
18 #include <asm/cacheflush.h>
19 #include <asm/hazards.h>
20 #include <asm/tlbflush.h>
21 #include <asm-generic/mm_hooks.h>
23 #define htw_set_pwbase(pgd) \
26 write_c0_pwbase(pgd); \
27 back_to_back_c0_hazard(); \
32 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
34 extern void tlbmiss_handler_setup_pgd(unsigned long); \
35 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
36 htw_set_pwbase((unsigned long)pgd); \
39 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
41 #define TLBMISS_HANDLER_RESTORE() \
42 write_c0_xcontext((unsigned long) smp_processor_id() << \
45 #define TLBMISS_HANDLER_SETUP() \
47 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
48 TLBMISS_HANDLER_RESTORE(); \
51 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
54 * For the fast tlb miss handlers, we keep a per cpu array of pointers
55 * to the current pgd for each processor. Also, the proc. id is stuffed
56 * into the context register.
58 extern unsigned long pgd_current[];
60 #define TLBMISS_HANDLER_RESTORE() \
61 write_c0_context((unsigned long) smp_processor_id() << \
64 #define TLBMISS_HANDLER_SETUP() \
65 TLBMISS_HANDLER_RESTORE(); \
66 back_to_back_c0_hazard(); \
67 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
68 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
69 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
72 #define ASID_MASK 0xfc0
74 #elif defined(CONFIG_CPU_R8000)
77 #define ASID_MASK 0xff0
79 #else /* FIXME: not correct for R6000 */
82 #define ASID_MASK 0xff
86 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
87 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
88 #define asid_cache(cpu) (cpu_data[cpu].asid_cache)
90 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
95 * All unused by hardware upper bits will be considered
96 * as a software asid extension.
98 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
99 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
101 /* Normal, classic MIPS get_new_mmu_context */
103 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
105 extern void kvm_local_flush_tlb_all(void);
106 unsigned long asid = asid_cache(cpu);
108 if (! ((asid += ASID_INC) & ASID_MASK) ) {
109 if (cpu_has_vtag_icache)
112 kvm_local_flush_tlb_all(); /* start new asid cycle */
114 local_flush_tlb_all(); /* start new asid cycle */
116 if (!asid) /* fix version if needed */
117 asid = ASID_FIRST_VERSION;
120 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
124 * Initialize the context related info for a new mm_struct
128 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
132 for_each_possible_cpu(i)
133 cpu_context(i, mm) = 0;
138 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
139 struct task_struct *tsk)
141 unsigned int cpu = smp_processor_id();
143 local_irq_save(flags);
145 /* Check if our ASID is of an older version and thus invalid */
146 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
147 get_new_mmu_context(next, cpu);
148 write_c0_entryhi(cpu_asid(cpu, next));
149 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
152 * Mark current->active_mm as not "active" anymore.
153 * We don't want to mislead possible IPI tlb flush routines.
155 cpumask_clear_cpu(cpu, mm_cpumask(prev));
156 cpumask_set_cpu(cpu, mm_cpumask(next));
158 local_irq_restore(flags);
162 * Destroy context related info for an mm_struct that is about
165 static inline void destroy_context(struct mm_struct *mm)
169 #define deactivate_mm(tsk, mm) do { } while (0)
172 * After we have set current->mm to a new value, this activates
173 * the context for the new mm so we see the new mappings.
176 activate_mm(struct mm_struct *prev, struct mm_struct *next)
179 unsigned int cpu = smp_processor_id();
181 local_irq_save(flags);
183 /* Unconditionally get a new ASID. */
184 get_new_mmu_context(next, cpu);
186 write_c0_entryhi(cpu_asid(cpu, next));
187 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
189 /* mark mmu ownership change */
190 cpumask_clear_cpu(cpu, mm_cpumask(prev));
191 cpumask_set_cpu(cpu, mm_cpumask(next));
193 local_irq_restore(flags);
197 * If mm is currently active_mm, we can't really drop it. Instead,
198 * we will get a new one for it.
201 drop_mmu_context(struct mm_struct *mm, unsigned cpu)
205 local_irq_save(flags);
207 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
208 get_new_mmu_context(mm, cpu);
209 write_c0_entryhi(cpu_asid(cpu, mm));
211 /* will get a new context next time */
212 cpu_context(cpu, mm) = 0;
214 local_irq_restore(flags);
217 #endif /* _ASM_MMU_CONTEXT_H */