1 /****************************************************************************/
4 * m523xsim.h -- ColdFire 523x System Integration Module support.
6 * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
9 /****************************************************************************/
12 /****************************************************************************/
14 #define CPU_NAME "COLDFIRE(m523x)"
15 #define CPU_INSTR_PER_JIFFY 3
18 * Define the 523x SIM register set addresses.
20 #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
21 #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
22 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
23 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
24 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
25 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
26 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
27 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
28 #define MCFINTC_IRLR 0x18 /* */
29 #define MCFINTC_IACKL 0x19 /* */
30 #define MCFINTC_ICR0 0x40 /* Base ICR register */
32 #define MCFINT_VECBASE 64 /* Vector base number */
33 #define MCFINT_UART0 13 /* Interrupt number for UART0 */
34 #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
35 #define MCFINT_QSPI 18 /* Interrupt number for QSPI */
38 * SDRAM configuration registers.
40 #define MCFSIM_DCR 0x44 /* SDRAM control */
41 #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
42 #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
43 #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
44 #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
47 * Reset Controll Unit (relative to IPSBAR).
49 #define MCF_RCR 0x110000
50 #define MCF_RSR 0x110001
52 #define MCF_RCR_SWRESET 0x80 /* Software reset bit */
53 #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
58 #define MCFUART_BASE1 0x200 /* Base address of UART1 */
59 #define MCFUART_BASE2 0x240 /* Base address of UART2 */
60 #define MCFUART_BASE3 0x280 /* Base address of UART3 */
62 #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
63 #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
64 #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
65 #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
66 #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
67 #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
68 #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
69 #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
70 #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
71 #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
72 #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
73 #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
74 #define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
76 #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
77 #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
78 #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
79 #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
80 #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
81 #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
82 #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
83 #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
84 #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
85 #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
86 #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
87 #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
88 #define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
90 #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
91 #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
92 #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
93 #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
94 #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
95 #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
96 #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
97 #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
98 #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
99 #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
100 #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
101 #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
102 #define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
104 #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
105 #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
106 #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
107 #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
108 #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
109 #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
110 #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
111 #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
112 #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
113 #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
114 #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
115 #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
116 #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
122 #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
123 #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
124 #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
127 * Generic GPIO support
129 #define MCFGPIO_PODR MCFGPIO_PODR_ADDR
130 #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
131 #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
132 #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
133 #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
135 #define MCFGPIO_PIN_MAX 107
136 #define MCFGPIO_IRQ_MAX 8
137 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
142 #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
143 #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
144 /****************************************************************************/
145 #endif /* m523xsim_h */