1 /****************************************************************************/
4 * m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
6 * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
9 /****************************************************************************/
12 /****************************************************************************/
14 #define CPU_NAME "COLDFIRE(m520x)"
15 #define CPU_INSTR_PER_JIFFY 3
18 * Define the 520x SIM register set addresses.
20 #define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */
21 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
22 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
23 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
24 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
25 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
26 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
27 #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */
28 #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */
29 #define MCFINTC_ICR0 0x40 /* Base ICR register */
32 * The common interrupt controller code just wants to know the absolute
33 * address to the SIMR and CIMR registers (not offsets into IPSBAR).
34 * The 520x family only has a single INTC unit.
36 #define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR)
37 #define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR)
38 #define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0)
39 #define MCFINTC1_SIMR (0)
40 #define MCFINTC1_CIMR (0)
41 #define MCFINTC1_ICR0 (0)
43 #define MCFINT_VECBASE 64
44 #define MCFINT_UART0 26 /* Interrupt number for UART0 */
45 #define MCFINT_UART1 27 /* Interrupt number for UART1 */
46 #define MCFINT_UART2 28 /* Interrupt number for UART2 */
47 #define MCFINT_QSPI 31 /* Interrupt number for QSPI */
48 #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
51 * SDRAM configuration registers.
53 #define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */
54 #define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */
55 #define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */
56 #define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */
57 #define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
58 #define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
60 #define MCFEPORT_EPDDR 0xFC088002
61 #define MCFEPORT_EPDR 0xFC088004
62 #define MCFEPORT_EPPDR 0xFC088005
64 #define MCFGPIO_PODR_BUSCTL 0xFC0A4000
65 #define MCFGPIO_PODR_BE 0xFC0A4001
66 #define MCFGPIO_PODR_CS 0xFC0A4002
67 #define MCFGPIO_PODR_FECI2C 0xFC0A4003
68 #define MCFGPIO_PODR_QSPI 0xFC0A4004
69 #define MCFGPIO_PODR_TIMER 0xFC0A4005
70 #define MCFGPIO_PODR_UART 0xFC0A4006
71 #define MCFGPIO_PODR_FECH 0xFC0A4007
72 #define MCFGPIO_PODR_FECL 0xFC0A4008
74 #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C
75 #define MCFGPIO_PDDR_BE 0xFC0A400D
76 #define MCFGPIO_PDDR_CS 0xFC0A400E
77 #define MCFGPIO_PDDR_FECI2C 0xFC0A400F
78 #define MCFGPIO_PDDR_QSPI 0xFC0A4010
79 #define MCFGPIO_PDDR_TIMER 0xFC0A4011
80 #define MCFGPIO_PDDR_UART 0xFC0A4012
81 #define MCFGPIO_PDDR_FECH 0xFC0A4013
82 #define MCFGPIO_PDDR_FECL 0xFC0A4014
84 #define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A
85 #define MCFGPIO_PPDSDR_BE 0xFC0A401B
86 #define MCFGPIO_PPDSDR_CS 0xFC0A401C
87 #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D
88 #define MCFGPIO_PPDSDR_QSPI 0xFC0A401E
89 #define MCFGPIO_PPDSDR_TIMER 0xFC0A401F
90 #define MCFGPIO_PPDSDR_UART 0xFC0A4021
91 #define MCFGPIO_PPDSDR_FECH 0xFC0A4021
92 #define MCFGPIO_PPDSDR_FECL 0xFC0A4022
94 #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024
95 #define MCFGPIO_PCLRR_BE 0xFC0A4025
96 #define MCFGPIO_PCLRR_CS 0xFC0A4026
97 #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027
98 #define MCFGPIO_PCLRR_QSPI 0xFC0A4028
99 #define MCFGPIO_PCLRR_TIMER 0xFC0A4029
100 #define MCFGPIO_PCLRR_UART 0xFC0A402A
101 #define MCFGPIO_PCLRR_FECH 0xFC0A402B
102 #define MCFGPIO_PCLRR_FECL 0xFC0A402C
104 * Generic GPIO support
106 #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
107 #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
108 #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
109 #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
110 #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
112 #define MCFGPIO_PIN_MAX 80
113 #define MCFGPIO_IRQ_MAX 8
114 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
115 /****************************************************************************/
117 #define MCF_GPIO_PAR_UART (0xA4036)
118 #define MCF_GPIO_PAR_FECI2C (0xA4033)
119 #define MCF_GPIO_PAR_QSPI (0xA4034)
120 #define MCF_GPIO_PAR_FEC (0xA4038)
122 #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
123 #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
125 #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
126 #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
128 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
129 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
132 * Reset Controll Unit.
134 #define MCF_RCR 0xFC0A0000
135 #define MCF_RSR 0xFC0A0001
137 #define MCF_RCR_SWRESET 0x80 /* Software reset bit */
138 #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
140 /****************************************************************************/
141 #endif /* m520xsim_h */