2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/spi/spi.h>
17 #include <asm/arch/at32ap700x.h>
18 #include <asm/arch/board.h>
19 #include <asm/arch/portmux.h>
21 #include <video/atmel_lcdc.h>
32 .end = base + 0x3ff, \
33 .flags = IORESOURCE_MEM, \
39 .flags = IORESOURCE_IRQ, \
41 #define NAMED_IRQ(num, _name) \
46 .flags = IORESOURCE_IRQ, \
49 /* REVISIT these assume *every* device supports DMA, but several
50 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
52 #define DEFINE_DEV(_name, _id) \
53 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
54 static struct platform_device _name##_id##_device = { \
58 .dma_mask = &_name##_id##_dma_mask, \
59 .coherent_dma_mask = DMA_32BIT_MASK, \
61 .resource = _name##_id##_resource, \
62 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
64 #define DEFINE_DEV_DATA(_name, _id) \
65 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
66 static struct platform_device _name##_id##_device = { \
70 .dma_mask = &_name##_id##_dma_mask, \
71 .platform_data = &_name##_id##_data, \
72 .coherent_dma_mask = DMA_32BIT_MASK, \
74 .resource = _name##_id##_resource, \
75 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
78 #define select_peripheral(pin, periph, flags) \
79 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
81 #define DEV_CLK(_name, devname, bus, _index) \
82 static struct clk devname##_##_name = { \
84 .dev = &devname##_device.dev, \
85 .parent = &bus##_clk, \
86 .mode = bus##_clk_mode, \
87 .get_rate = bus##_clk_get_rate, \
91 static DEFINE_SPINLOCK(pm_lock);
93 unsigned long at32ap7000_osc_rates[3] = {
95 /* FIXME: these are ATSTK1002-specific */
100 static unsigned long osc_get_rate(struct clk *clk)
102 return at32ap7000_osc_rates[clk->index];
105 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
107 unsigned long div, mul, rate;
109 if (!(control & PM_BIT(PLLEN)))
112 div = PM_BFEXT(PLLDIV, control) + 1;
113 mul = PM_BFEXT(PLLMUL, control) + 1;
115 rate = clk->parent->get_rate(clk->parent);
116 rate = (rate + div / 2) / div;
122 static unsigned long pll0_get_rate(struct clk *clk)
126 control = pm_readl(PLL0);
128 return pll_get_rate(clk, control);
131 static unsigned long pll1_get_rate(struct clk *clk)
135 control = pm_readl(PLL1);
137 return pll_get_rate(clk, control);
141 * The AT32AP7000 has five primary clock sources: One 32kHz
142 * oscillator, two crystal oscillators and two PLLs.
144 static struct clk osc32k = {
146 .get_rate = osc_get_rate,
150 static struct clk osc0 = {
152 .get_rate = osc_get_rate,
156 static struct clk osc1 = {
158 .get_rate = osc_get_rate,
161 static struct clk pll0 = {
163 .get_rate = pll0_get_rate,
166 static struct clk pll1 = {
168 .get_rate = pll1_get_rate,
173 * The main clock can be either osc0 or pll0. The boot loader may
174 * have chosen one for us, so we don't really know which one until we
175 * have a look at the SM.
177 static struct clk *main_clock;
180 * Synchronous clocks are generated from the main clock. The clocks
181 * must satisfy the constraint
182 * fCPU >= fHSB >= fPB
183 * i.e. each clock must not be faster than its parent.
185 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
187 return main_clock->get_rate(main_clock) >> shift;
190 static void cpu_clk_mode(struct clk *clk, int enabled)
195 spin_lock_irqsave(&pm_lock, flags);
196 mask = pm_readl(CPU_MASK);
198 mask |= 1 << clk->index;
200 mask &= ~(1 << clk->index);
201 pm_writel(CPU_MASK, mask);
202 spin_unlock_irqrestore(&pm_lock, flags);
205 static unsigned long cpu_clk_get_rate(struct clk *clk)
207 unsigned long cksel, shift = 0;
209 cksel = pm_readl(CKSEL);
210 if (cksel & PM_BIT(CPUDIV))
211 shift = PM_BFEXT(CPUSEL, cksel) + 1;
213 return bus_clk_get_rate(clk, shift);
216 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
219 unsigned long parent_rate, child_div, actual_rate, div;
221 parent_rate = clk->parent->get_rate(clk->parent);
222 control = pm_readl(CKSEL);
224 if (control & PM_BIT(HSBDIV))
225 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
229 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
230 actual_rate = parent_rate;
231 control &= ~PM_BIT(CPUDIV);
234 div = (parent_rate + rate / 2) / rate;
237 cpusel = (div > 1) ? (fls(div) - 2) : 0;
238 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
239 actual_rate = parent_rate / (1 << (cpusel + 1));
242 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
243 clk->name, rate, actual_rate);
246 pm_writel(CKSEL, control);
251 static void hsb_clk_mode(struct clk *clk, int enabled)
256 spin_lock_irqsave(&pm_lock, flags);
257 mask = pm_readl(HSB_MASK);
259 mask |= 1 << clk->index;
261 mask &= ~(1 << clk->index);
262 pm_writel(HSB_MASK, mask);
263 spin_unlock_irqrestore(&pm_lock, flags);
266 static unsigned long hsb_clk_get_rate(struct clk *clk)
268 unsigned long cksel, shift = 0;
270 cksel = pm_readl(CKSEL);
271 if (cksel & PM_BIT(HSBDIV))
272 shift = PM_BFEXT(HSBSEL, cksel) + 1;
274 return bus_clk_get_rate(clk, shift);
277 static void pba_clk_mode(struct clk *clk, int enabled)
282 spin_lock_irqsave(&pm_lock, flags);
283 mask = pm_readl(PBA_MASK);
285 mask |= 1 << clk->index;
287 mask &= ~(1 << clk->index);
288 pm_writel(PBA_MASK, mask);
289 spin_unlock_irqrestore(&pm_lock, flags);
292 static unsigned long pba_clk_get_rate(struct clk *clk)
294 unsigned long cksel, shift = 0;
296 cksel = pm_readl(CKSEL);
297 if (cksel & PM_BIT(PBADIV))
298 shift = PM_BFEXT(PBASEL, cksel) + 1;
300 return bus_clk_get_rate(clk, shift);
303 static void pbb_clk_mode(struct clk *clk, int enabled)
308 spin_lock_irqsave(&pm_lock, flags);
309 mask = pm_readl(PBB_MASK);
311 mask |= 1 << clk->index;
313 mask &= ~(1 << clk->index);
314 pm_writel(PBB_MASK, mask);
315 spin_unlock_irqrestore(&pm_lock, flags);
318 static unsigned long pbb_clk_get_rate(struct clk *clk)
320 unsigned long cksel, shift = 0;
322 cksel = pm_readl(CKSEL);
323 if (cksel & PM_BIT(PBBDIV))
324 shift = PM_BFEXT(PBBSEL, cksel) + 1;
326 return bus_clk_get_rate(clk, shift);
329 static struct clk cpu_clk = {
331 .get_rate = cpu_clk_get_rate,
332 .set_rate = cpu_clk_set_rate,
335 static struct clk hsb_clk = {
338 .get_rate = hsb_clk_get_rate,
340 static struct clk pba_clk = {
343 .mode = hsb_clk_mode,
344 .get_rate = pba_clk_get_rate,
347 static struct clk pbb_clk = {
350 .mode = hsb_clk_mode,
351 .get_rate = pbb_clk_get_rate,
356 /* --------------------------------------------------------------------
357 * Generic Clock operations
358 * -------------------------------------------------------------------- */
360 static void genclk_mode(struct clk *clk, int enabled)
364 control = pm_readl(GCCTRL(clk->index));
366 control |= PM_BIT(CEN);
368 control &= ~PM_BIT(CEN);
369 pm_writel(GCCTRL(clk->index), control);
372 static unsigned long genclk_get_rate(struct clk *clk)
375 unsigned long div = 1;
377 control = pm_readl(GCCTRL(clk->index));
378 if (control & PM_BIT(DIVEN))
379 div = 2 * (PM_BFEXT(DIV, control) + 1);
381 return clk->parent->get_rate(clk->parent) / div;
384 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
387 unsigned long parent_rate, actual_rate, div;
389 parent_rate = clk->parent->get_rate(clk->parent);
390 control = pm_readl(GCCTRL(clk->index));
392 if (rate > 3 * parent_rate / 4) {
393 actual_rate = parent_rate;
394 control &= ~PM_BIT(DIVEN);
396 div = (parent_rate + rate) / (2 * rate) - 1;
397 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
398 actual_rate = parent_rate / (2 * (div + 1));
401 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
402 clk->name, rate, actual_rate);
405 pm_writel(GCCTRL(clk->index), control);
410 int genclk_set_parent(struct clk *clk, struct clk *parent)
414 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
415 clk->name, parent->name, clk->parent->name);
417 control = pm_readl(GCCTRL(clk->index));
419 if (parent == &osc1 || parent == &pll1)
420 control |= PM_BIT(OSCSEL);
421 else if (parent == &osc0 || parent == &pll0)
422 control &= ~PM_BIT(OSCSEL);
426 if (parent == &pll0 || parent == &pll1)
427 control |= PM_BIT(PLLSEL);
429 control &= ~PM_BIT(PLLSEL);
431 pm_writel(GCCTRL(clk->index), control);
432 clk->parent = parent;
437 static void __init genclk_init_parent(struct clk *clk)
442 BUG_ON(clk->index > 7);
444 control = pm_readl(GCCTRL(clk->index));
445 if (control & PM_BIT(OSCSEL))
446 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
448 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
450 clk->parent = parent;
453 /* --------------------------------------------------------------------
455 * -------------------------------------------------------------------- */
456 static struct resource at32_pm0_resource[] = {
460 .flags = IORESOURCE_MEM,
465 static struct resource at32ap700x_rtc0_resource[] = {
469 .flags = IORESOURCE_MEM,
474 static struct resource at32_wdt0_resource[] = {
478 .flags = IORESOURCE_MEM,
482 static struct resource at32_eic0_resource[] = {
486 .flags = IORESOURCE_MEM,
491 DEFINE_DEV(at32_pm, 0);
492 DEFINE_DEV(at32ap700x_rtc, 0);
493 DEFINE_DEV(at32_wdt, 0);
494 DEFINE_DEV(at32_eic, 0);
497 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
500 static struct clk at32_pm_pclk = {
502 .dev = &at32_pm0_device.dev,
504 .mode = pbb_clk_mode,
505 .get_rate = pbb_clk_get_rate,
510 static struct resource intc0_resource[] = {
513 struct platform_device at32_intc0_device = {
516 .resource = intc0_resource,
517 .num_resources = ARRAY_SIZE(intc0_resource),
519 DEV_CLK(pclk, at32_intc0, pbb, 1);
521 static struct clk ebi_clk = {
524 .mode = hsb_clk_mode,
525 .get_rate = hsb_clk_get_rate,
528 static struct clk hramc_clk = {
531 .mode = hsb_clk_mode,
532 .get_rate = hsb_clk_get_rate,
537 static struct resource smc0_resource[] = {
541 DEV_CLK(pclk, smc0, pbb, 13);
542 DEV_CLK(mck, smc0, hsb, 0);
544 static struct platform_device pdc_device = {
548 DEV_CLK(hclk, pdc, hsb, 4);
549 DEV_CLK(pclk, pdc, pba, 16);
551 static struct clk pico_clk = {
554 .mode = cpu_clk_mode,
555 .get_rate = cpu_clk_get_rate,
559 static struct resource dmaca0_resource[] = {
563 .flags = IORESOURCE_MEM,
567 DEFINE_DEV(dmaca, 0);
568 DEV_CLK(hclk, dmaca0, hsb, 10);
570 /* --------------------------------------------------------------------
572 * -------------------------------------------------------------------- */
574 static struct clk hmatrix_clk = {
575 .name = "hmatrix_clk",
577 .mode = pbb_clk_mode,
578 .get_rate = pbb_clk_get_rate,
582 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
584 #define hmatrix_readl(reg) \
585 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
586 #define hmatrix_writel(reg,value) \
587 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
590 * Set bits in the HMATRIX Special Function Register (SFR) used by the
591 * External Bus Interface (EBI). This can be used to enable special
592 * features like CompactFlash support, NAND Flash support, etc. on
593 * certain chipselects.
595 static inline void set_ebi_sfr_bits(u32 mask)
599 clk_enable(&hmatrix_clk);
600 sfr = hmatrix_readl(SFR4);
602 hmatrix_writel(SFR4, sfr);
603 clk_disable(&hmatrix_clk);
606 /* --------------------------------------------------------------------
607 * System Timer/Counter (TC)
608 * -------------------------------------------------------------------- */
609 static struct resource at32_systc0_resource[] = {
613 struct platform_device at32_systc0_device = {
616 .resource = at32_systc0_resource,
617 .num_resources = ARRAY_SIZE(at32_systc0_resource),
619 DEV_CLK(pclk, at32_systc0, pbb, 3);
621 /* --------------------------------------------------------------------
623 * -------------------------------------------------------------------- */
625 static struct resource pio0_resource[] = {
630 DEV_CLK(mck, pio0, pba, 10);
632 static struct resource pio1_resource[] = {
637 DEV_CLK(mck, pio1, pba, 11);
639 static struct resource pio2_resource[] = {
644 DEV_CLK(mck, pio2, pba, 12);
646 static struct resource pio3_resource[] = {
651 DEV_CLK(mck, pio3, pba, 13);
653 static struct resource pio4_resource[] = {
658 DEV_CLK(mck, pio4, pba, 14);
660 void __init at32_add_system_devices(void)
662 platform_device_register(&at32_pm0_device);
663 platform_device_register(&at32_intc0_device);
664 platform_device_register(&at32ap700x_rtc0_device);
665 platform_device_register(&at32_wdt0_device);
666 platform_device_register(&at32_eic0_device);
667 platform_device_register(&smc0_device);
668 platform_device_register(&pdc_device);
669 platform_device_register(&dmaca0_device);
671 platform_device_register(&at32_systc0_device);
673 platform_device_register(&pio0_device);
674 platform_device_register(&pio1_device);
675 platform_device_register(&pio2_device);
676 platform_device_register(&pio3_device);
677 platform_device_register(&pio4_device);
680 /* --------------------------------------------------------------------
682 * -------------------------------------------------------------------- */
684 static struct atmel_uart_data atmel_usart0_data = {
688 static struct resource atmel_usart0_resource[] = {
692 DEFINE_DEV_DATA(atmel_usart, 0);
693 DEV_CLK(usart, atmel_usart0, pba, 3);
695 static struct atmel_uart_data atmel_usart1_data = {
699 static struct resource atmel_usart1_resource[] = {
703 DEFINE_DEV_DATA(atmel_usart, 1);
704 DEV_CLK(usart, atmel_usart1, pba, 4);
706 static struct atmel_uart_data atmel_usart2_data = {
710 static struct resource atmel_usart2_resource[] = {
714 DEFINE_DEV_DATA(atmel_usart, 2);
715 DEV_CLK(usart, atmel_usart2, pba, 5);
717 static struct atmel_uart_data atmel_usart3_data = {
721 static struct resource atmel_usart3_resource[] = {
725 DEFINE_DEV_DATA(atmel_usart, 3);
726 DEV_CLK(usart, atmel_usart3, pba, 6);
728 static inline void configure_usart0_pins(void)
730 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
731 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
734 static inline void configure_usart1_pins(void)
736 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
737 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
740 static inline void configure_usart2_pins(void)
742 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
743 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
746 static inline void configure_usart3_pins(void)
748 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
749 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
752 static struct platform_device *__initdata at32_usarts[4];
754 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
756 struct platform_device *pdev;
760 pdev = &atmel_usart0_device;
761 configure_usart0_pins();
764 pdev = &atmel_usart1_device;
765 configure_usart1_pins();
768 pdev = &atmel_usart2_device;
769 configure_usart2_pins();
772 pdev = &atmel_usart3_device;
773 configure_usart3_pins();
779 if (PXSEG(pdev->resource[0].start) == P4SEG) {
780 /* Addresses in the P4 segment are permanently mapped 1:1 */
781 struct atmel_uart_data *data = pdev->dev.platform_data;
782 data->regs = (void __iomem *)pdev->resource[0].start;
786 at32_usarts[line] = pdev;
789 struct platform_device *__init at32_add_device_usart(unsigned int id)
791 platform_device_register(at32_usarts[id]);
792 return at32_usarts[id];
795 struct platform_device *atmel_default_console_device;
797 void __init at32_setup_serial_console(unsigned int usart_id)
799 atmel_default_console_device = at32_usarts[usart_id];
802 /* --------------------------------------------------------------------
804 * -------------------------------------------------------------------- */
806 #ifdef CONFIG_CPU_AT32AP7000
807 static struct eth_platform_data macb0_data;
808 static struct resource macb0_resource[] = {
812 DEFINE_DEV_DATA(macb, 0);
813 DEV_CLK(hclk, macb0, hsb, 8);
814 DEV_CLK(pclk, macb0, pbb, 6);
816 static struct eth_platform_data macb1_data;
817 static struct resource macb1_resource[] = {
821 DEFINE_DEV_DATA(macb, 1);
822 DEV_CLK(hclk, macb1, hsb, 9);
823 DEV_CLK(pclk, macb1, pbb, 7);
825 struct platform_device *__init
826 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
828 struct platform_device *pdev;
832 pdev = &macb0_device;
834 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
835 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
836 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
837 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
838 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
839 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
840 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
841 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
842 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
843 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
845 if (!data->is_rmii) {
846 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
847 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
848 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
849 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
850 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
851 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
852 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
853 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
854 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
859 pdev = &macb1_device;
861 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
862 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
863 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
864 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
865 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
866 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
867 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
868 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
869 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
870 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
872 if (!data->is_rmii) {
873 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
874 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
875 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
876 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
877 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
878 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
879 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
880 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
881 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
889 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
890 platform_device_register(pdev);
896 /* --------------------------------------------------------------------
898 * -------------------------------------------------------------------- */
899 static struct resource atmel_spi0_resource[] = {
903 DEFINE_DEV(atmel_spi, 0);
904 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
906 static struct resource atmel_spi1_resource[] = {
910 DEFINE_DEV(atmel_spi, 1);
911 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
914 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
915 unsigned int n, const u8 *pins)
917 unsigned int pin, mode;
919 for (; n; n--, b++) {
920 b->bus_num = bus_num;
921 if (b->chip_select >= 4)
923 pin = (unsigned)b->controller_data;
925 pin = pins[b->chip_select];
926 b->controller_data = (void *)pin;
928 mode = AT32_GPIOF_OUTPUT;
929 if (!(b->mode & SPI_CS_HIGH))
930 mode |= AT32_GPIOF_HIGH;
931 at32_select_gpio(pin, mode);
935 struct platform_device *__init
936 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
939 * Manage the chipselects as GPIOs, normally using the same pins
940 * the SPI controller expects; but boards can use other pins.
942 static u8 __initdata spi0_pins[] =
943 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
944 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
945 static u8 __initdata spi1_pins[] =
946 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
947 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
948 struct platform_device *pdev;
952 pdev = &atmel_spi0_device;
953 select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
954 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
955 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
956 at32_spi_setup_slaves(0, b, n, spi0_pins);
960 pdev = &atmel_spi1_device;
961 select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
962 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
963 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
964 at32_spi_setup_slaves(1, b, n, spi1_pins);
971 spi_register_board_info(b, n);
972 platform_device_register(pdev);
976 /* --------------------------------------------------------------------
978 * -------------------------------------------------------------------- */
979 static struct resource atmel_twi0_resource[] __initdata = {
983 static struct clk atmel_twi0_pclk = {
986 .mode = pba_clk_mode,
987 .get_rate = pba_clk_get_rate,
991 struct platform_device *__init at32_add_device_twi(unsigned int id)
993 struct platform_device *pdev;
998 pdev = platform_device_alloc("atmel_twi", id);
1002 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1003 ARRAY_SIZE(atmel_twi0_resource)))
1004 goto err_add_resources;
1006 select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
1007 select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
1009 atmel_twi0_pclk.dev = &pdev->dev;
1011 platform_device_add(pdev);
1015 platform_device_put(pdev);
1019 /* --------------------------------------------------------------------
1021 * -------------------------------------------------------------------- */
1022 static struct resource atmel_mci0_resource[] __initdata = {
1026 static struct clk atmel_mci0_pclk = {
1029 .mode = pbb_clk_mode,
1030 .get_rate = pbb_clk_get_rate,
1034 struct platform_device *__init at32_add_device_mci(unsigned int id)
1036 struct platform_device *pdev;
1041 pdev = platform_device_alloc("atmel_mci", id);
1045 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1046 ARRAY_SIZE(atmel_mci0_resource)))
1047 goto err_add_resources;
1049 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
1050 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
1051 select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1052 select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1053 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1054 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1056 atmel_mci0_pclk.dev = &pdev->dev;
1058 platform_device_add(pdev);
1062 platform_device_put(pdev);
1066 /* --------------------------------------------------------------------
1068 * -------------------------------------------------------------------- */
1069 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1070 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1071 static struct resource atmel_lcdfb0_resource[] = {
1073 .start = 0xff000000,
1075 .flags = IORESOURCE_MEM,
1079 /* Placeholder for pre-allocated fb memory */
1080 .start = 0x00000000,
1085 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1086 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1087 static struct clk atmel_lcdfb0_pixclk = {
1089 .dev = &atmel_lcdfb0_device.dev,
1090 .mode = genclk_mode,
1091 .get_rate = genclk_get_rate,
1092 .set_rate = genclk_set_rate,
1093 .set_parent = genclk_set_parent,
1097 struct platform_device *__init
1098 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1099 unsigned long fbmem_start, unsigned long fbmem_len)
1101 struct platform_device *pdev;
1102 struct atmel_lcdfb_info *info;
1103 struct fb_monspecs *monspecs;
1104 struct fb_videomode *modedb;
1105 unsigned int modedb_size;
1108 * Do a deep copy of the fb data, monspecs and modedb. Make
1109 * sure all allocations are done before setting up the
1112 monspecs = kmemdup(data->default_monspecs,
1113 sizeof(struct fb_monspecs), GFP_KERNEL);
1117 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1118 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1120 goto err_dup_modedb;
1121 monspecs->modedb = modedb;
1125 pdev = &atmel_lcdfb0_device;
1126 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
1127 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1128 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1129 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1130 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
1131 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
1132 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1133 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
1134 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
1135 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
1136 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
1137 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
1138 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1139 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1140 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1141 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1142 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1143 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1144 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1145 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1146 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1147 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1148 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1149 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1150 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1151 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1152 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1153 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1154 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1155 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1156 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1158 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1159 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1163 goto err_invalid_id;
1167 pdev->resource[2].start = fbmem_start;
1168 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1169 pdev->resource[2].flags = IORESOURCE_MEM;
1172 info = pdev->dev.platform_data;
1173 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1174 info->default_monspecs = monspecs;
1176 platform_device_register(pdev);
1187 /* --------------------------------------------------------------------
1189 * -------------------------------------------------------------------- */
1190 static struct resource ssc0_resource[] = {
1195 DEV_CLK(pclk, ssc0, pba, 7);
1197 static struct resource ssc1_resource[] = {
1202 DEV_CLK(pclk, ssc1, pba, 8);
1204 static struct resource ssc2_resource[] = {
1209 DEV_CLK(pclk, ssc2, pba, 9);
1211 struct platform_device *__init
1212 at32_add_device_ssc(unsigned int id, unsigned int flags)
1214 struct platform_device *pdev;
1218 pdev = &ssc0_device;
1219 if (flags & ATMEL_SSC_RF)
1220 select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1221 if (flags & ATMEL_SSC_RK)
1222 select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1223 if (flags & ATMEL_SSC_TK)
1224 select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1225 if (flags & ATMEL_SSC_TF)
1226 select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1227 if (flags & ATMEL_SSC_TD)
1228 select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1229 if (flags & ATMEL_SSC_RD)
1230 select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1233 pdev = &ssc1_device;
1234 if (flags & ATMEL_SSC_RF)
1235 select_peripheral(PA(0), PERIPH_B, 0); /* RF */
1236 if (flags & ATMEL_SSC_RK)
1237 select_peripheral(PA(1), PERIPH_B, 0); /* RK */
1238 if (flags & ATMEL_SSC_TK)
1239 select_peripheral(PA(2), PERIPH_B, 0); /* TK */
1240 if (flags & ATMEL_SSC_TF)
1241 select_peripheral(PA(3), PERIPH_B, 0); /* TF */
1242 if (flags & ATMEL_SSC_TD)
1243 select_peripheral(PA(4), PERIPH_B, 0); /* TD */
1244 if (flags & ATMEL_SSC_RD)
1245 select_peripheral(PA(5), PERIPH_B, 0); /* RD */
1248 pdev = &ssc2_device;
1249 if (flags & ATMEL_SSC_TD)
1250 select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1251 if (flags & ATMEL_SSC_RD)
1252 select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1253 if (flags & ATMEL_SSC_TK)
1254 select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1255 if (flags & ATMEL_SSC_TF)
1256 select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1257 if (flags & ATMEL_SSC_RF)
1258 select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1259 if (flags & ATMEL_SSC_RK)
1260 select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1266 platform_device_register(pdev);
1270 /* --------------------------------------------------------------------
1271 * USB Device Controller
1272 * -------------------------------------------------------------------- */
1273 static struct resource usba0_resource[] __initdata = {
1275 .start = 0xff300000,
1277 .flags = IORESOURCE_MEM,
1279 .start = 0xfff03000,
1281 .flags = IORESOURCE_MEM,
1285 static struct clk usba0_pclk = {
1288 .mode = pbb_clk_mode,
1289 .get_rate = pbb_clk_get_rate,
1292 static struct clk usba0_hclk = {
1295 .mode = hsb_clk_mode,
1296 .get_rate = hsb_clk_get_rate,
1300 struct platform_device *__init
1301 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1303 struct platform_device *pdev;
1308 pdev = platform_device_alloc("atmel_usba_udc", 0);
1312 if (platform_device_add_resources(pdev, usba0_resource,
1313 ARRAY_SIZE(usba0_resource)))
1317 if (platform_device_add_data(pdev, data, sizeof(*data)))
1320 if (data->vbus_pin != GPIO_PIN_NONE)
1321 at32_select_gpio(data->vbus_pin, 0);
1324 usba0_pclk.dev = &pdev->dev;
1325 usba0_hclk.dev = &pdev->dev;
1327 platform_device_add(pdev);
1332 platform_device_put(pdev);
1336 /* --------------------------------------------------------------------
1337 * IDE / CompactFlash
1338 * -------------------------------------------------------------------- */
1339 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1340 static struct resource at32_smc_cs4_resource[] __initdata = {
1342 .start = 0x04000000,
1344 .flags = IORESOURCE_MEM,
1346 IRQ(~0UL), /* Magic IRQ will be overridden */
1348 static struct resource at32_smc_cs5_resource[] __initdata = {
1350 .start = 0x20000000,
1352 .flags = IORESOURCE_MEM,
1354 IRQ(~0UL), /* Magic IRQ will be overridden */
1357 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1358 unsigned int cs, unsigned int extint)
1360 static unsigned int extint_pin_map[4] __initdata = {
1366 static bool common_pins_initialized __initdata = false;
1367 unsigned int extint_pin;
1370 if (extint >= ARRAY_SIZE(extint_pin_map))
1372 extint_pin = extint_pin_map[extint];
1376 ret = platform_device_add_resources(pdev,
1377 at32_smc_cs4_resource,
1378 ARRAY_SIZE(at32_smc_cs4_resource));
1382 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
1383 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1386 ret = platform_device_add_resources(pdev,
1387 at32_smc_cs5_resource,
1388 ARRAY_SIZE(at32_smc_cs5_resource));
1392 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
1393 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1399 if (!common_pins_initialized) {
1400 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
1401 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
1402 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
1403 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
1404 common_pins_initialized = true;
1407 at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1409 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1410 pdev->resource[1].end = pdev->resource[1].start;
1415 struct platform_device *__init
1416 at32_add_device_ide(unsigned int id, unsigned int extint,
1417 struct ide_platform_data *data)
1419 struct platform_device *pdev;
1421 pdev = platform_device_alloc("at32_ide", id);
1425 if (platform_device_add_data(pdev, data,
1426 sizeof(struct ide_platform_data)))
1429 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1432 platform_device_add(pdev);
1436 platform_device_put(pdev);
1440 struct platform_device *__init
1441 at32_add_device_cf(unsigned int id, unsigned int extint,
1442 struct cf_platform_data *data)
1444 struct platform_device *pdev;
1446 pdev = platform_device_alloc("at32_cf", id);
1450 if (platform_device_add_data(pdev, data,
1451 sizeof(struct cf_platform_data)))
1454 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1457 if (data->detect_pin != GPIO_PIN_NONE)
1458 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1459 if (data->reset_pin != GPIO_PIN_NONE)
1460 at32_select_gpio(data->reset_pin, 0);
1461 if (data->vcc_pin != GPIO_PIN_NONE)
1462 at32_select_gpio(data->vcc_pin, 0);
1463 /* READY is used as extint, so we can't select it as gpio */
1465 platform_device_add(pdev);
1469 platform_device_put(pdev);
1474 /* --------------------------------------------------------------------
1476 * -------------------------------------------------------------------- */
1477 static struct resource atmel_ac97c0_resource[] __initdata = {
1481 static struct clk atmel_ac97c0_pclk = {
1484 .mode = pbb_clk_mode,
1485 .get_rate = pbb_clk_get_rate,
1489 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1491 struct platform_device *pdev;
1496 pdev = platform_device_alloc("atmel_ac97c", id);
1500 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1501 ARRAY_SIZE(atmel_ac97c0_resource)))
1502 goto err_add_resources;
1504 select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1505 select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
1506 select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
1507 select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1509 atmel_ac97c0_pclk.dev = &pdev->dev;
1511 platform_device_add(pdev);
1515 platform_device_put(pdev);
1519 /* --------------------------------------------------------------------
1521 * -------------------------------------------------------------------- */
1522 static struct resource abdac0_resource[] __initdata = {
1526 static struct clk abdac0_pclk = {
1529 .mode = pbb_clk_mode,
1530 .get_rate = pbb_clk_get_rate,
1533 static struct clk abdac0_sample_clk = {
1534 .name = "sample_clk",
1535 .mode = genclk_mode,
1536 .get_rate = genclk_get_rate,
1537 .set_rate = genclk_set_rate,
1538 .set_parent = genclk_set_parent,
1542 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1544 struct platform_device *pdev;
1549 pdev = platform_device_alloc("abdac", id);
1553 if (platform_device_add_resources(pdev, abdac0_resource,
1554 ARRAY_SIZE(abdac0_resource)))
1555 goto err_add_resources;
1557 select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
1558 select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
1559 select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
1560 select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
1562 abdac0_pclk.dev = &pdev->dev;
1563 abdac0_sample_clk.dev = &pdev->dev;
1565 platform_device_add(pdev);
1569 platform_device_put(pdev);
1573 /* --------------------------------------------------------------------
1575 * -------------------------------------------------------------------- */
1576 static struct clk gclk0 = {
1578 .mode = genclk_mode,
1579 .get_rate = genclk_get_rate,
1580 .set_rate = genclk_set_rate,
1581 .set_parent = genclk_set_parent,
1584 static struct clk gclk1 = {
1586 .mode = genclk_mode,
1587 .get_rate = genclk_get_rate,
1588 .set_rate = genclk_set_rate,
1589 .set_parent = genclk_set_parent,
1592 static struct clk gclk2 = {
1594 .mode = genclk_mode,
1595 .get_rate = genclk_get_rate,
1596 .set_rate = genclk_set_rate,
1597 .set_parent = genclk_set_parent,
1600 static struct clk gclk3 = {
1602 .mode = genclk_mode,
1603 .get_rate = genclk_get_rate,
1604 .set_rate = genclk_set_rate,
1605 .set_parent = genclk_set_parent,
1608 static struct clk gclk4 = {
1610 .mode = genclk_mode,
1611 .get_rate = genclk_get_rate,
1612 .set_rate = genclk_set_rate,
1613 .set_parent = genclk_set_parent,
1617 struct clk *at32_clock_list[] = {
1644 &atmel_usart0_usart,
1645 &atmel_usart1_usart,
1646 &atmel_usart2_usart,
1647 &atmel_usart3_usart,
1648 #if defined(CONFIG_CPU_AT32AP7000)
1654 &atmel_spi0_spi_clk,
1655 &atmel_spi1_spi_clk,
1658 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1660 &atmel_lcdfb0_pixclk,
1676 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1678 void __init at32_portmux_init(void)
1680 at32_init_pio(&pio0_device);
1681 at32_init_pio(&pio1_device);
1682 at32_init_pio(&pio2_device);
1683 at32_init_pio(&pio3_device);
1684 at32_init_pio(&pio4_device);
1687 void __init at32_clock_init(void)
1689 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1692 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
1694 cpu_clk.parent = &pll0;
1697 cpu_clk.parent = &osc0;
1700 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1701 pll0.parent = &osc1;
1702 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1703 pll1.parent = &osc1;
1705 genclk_init_parent(&gclk0);
1706 genclk_init_parent(&gclk1);
1707 genclk_init_parent(&gclk2);
1708 genclk_init_parent(&gclk3);
1709 genclk_init_parent(&gclk4);
1710 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1711 genclk_init_parent(&atmel_lcdfb0_pixclk);
1713 genclk_init_parent(&abdac0_sample_clk);
1716 * Turn on all clocks that have at least one user already, and
1717 * turn off everything else. We only do this for module
1718 * clocks, and even though it isn't particularly pretty to
1719 * check the address of the mode function, it should do the
1722 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1723 struct clk *clk = at32_clock_list[i];
1725 if (clk->users == 0)
1728 if (clk->mode == &cpu_clk_mode)
1729 cpu_mask |= 1 << clk->index;
1730 else if (clk->mode == &hsb_clk_mode)
1731 hsb_mask |= 1 << clk->index;
1732 else if (clk->mode == &pba_clk_mode)
1733 pba_mask |= 1 << clk->index;
1734 else if (clk->mode == &pbb_clk_mode)
1735 pbb_mask |= 1 << clk->index;
1738 pm_writel(CPU_MASK, cpu_mask);
1739 pm_writel(HSB_MASK, hsb_mask);
1740 pm_writel(PBA_MASK, pba_mask);
1741 pm_writel(PBB_MASK, pbb_mask);