2 * arch/arm/plat-orion/gpio.c
4 * Marvell Orion SoC GPIO handling.
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
18 #include <linux/gpio.h>
21 * GPIO unit register offsets.
23 #define GPIO_OUT_OFF 0x0000
24 #define GPIO_IO_CONF_OFF 0x0004
25 #define GPIO_BLINK_EN_OFF 0x0008
26 #define GPIO_IN_POL_OFF 0x000c
27 #define GPIO_DATA_IN_OFF 0x0010
28 #define GPIO_EDGE_CAUSE_OFF 0x0014
29 #define GPIO_EDGE_MASK_OFF 0x0018
30 #define GPIO_LEVEL_MASK_OFF 0x001c
32 struct orion_gpio_chip {
33 struct gpio_chip chip;
36 unsigned long valid_input;
37 unsigned long valid_output;
39 int secondary_irq_base;
42 static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
44 return ochip->base + GPIO_OUT_OFF;
47 static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
49 return ochip->base + GPIO_IO_CONF_OFF;
52 static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
54 return ochip->base + GPIO_BLINK_EN_OFF;
57 static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
59 return ochip->base + GPIO_IN_POL_OFF;
62 static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
64 return ochip->base + GPIO_DATA_IN_OFF;
67 static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
69 return ochip->base + GPIO_EDGE_CAUSE_OFF;
72 static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
74 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
77 static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
79 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
83 static struct orion_gpio_chip orion_gpio_chips[2];
84 static int orion_gpio_chip_count;
87 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
91 u = readl(GPIO_IO_CONF(ochip));
96 writel(u, GPIO_IO_CONF(ochip));
99 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
103 u = readl(GPIO_OUT(ochip));
108 writel(u, GPIO_OUT(ochip));
112 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
116 u = readl(GPIO_BLINK_EN(ochip));
121 writel(u, GPIO_BLINK_EN(ochip));
125 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
127 if (pin >= ochip->chip.ngpio)
130 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
133 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
139 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
144 * GENERIC_GPIO primitives.
146 static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
148 struct orion_gpio_chip *ochip =
149 container_of(chip, struct orion_gpio_chip, chip);
151 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
152 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
158 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
160 struct orion_gpio_chip *ochip =
161 container_of(chip, struct orion_gpio_chip, chip);
164 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
167 spin_lock_irqsave(&ochip->lock, flags);
168 __set_direction(ochip, pin, 1);
169 spin_unlock_irqrestore(&ochip->lock, flags);
174 static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
176 struct orion_gpio_chip *ochip =
177 container_of(chip, struct orion_gpio_chip, chip);
180 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
181 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
183 val = readl(GPIO_OUT(ochip));
186 return (val >> pin) & 1;
190 orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
192 struct orion_gpio_chip *ochip =
193 container_of(chip, struct orion_gpio_chip, chip);
196 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
199 spin_lock_irqsave(&ochip->lock, flags);
200 __set_blinking(ochip, pin, 0);
201 __set_level(ochip, pin, value);
202 __set_direction(ochip, pin, 0);
203 spin_unlock_irqrestore(&ochip->lock, flags);
208 static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
210 struct orion_gpio_chip *ochip =
211 container_of(chip, struct orion_gpio_chip, chip);
214 spin_lock_irqsave(&ochip->lock, flags);
215 __set_level(ochip, pin, value);
216 spin_unlock_irqrestore(&ochip->lock, flags);
219 static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
221 struct orion_gpio_chip *ochip =
222 container_of(chip, struct orion_gpio_chip, chip);
224 return ochip->secondary_irq_base + pin;
229 * Orion-specific GPIO API extensions.
231 static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
235 for (i = 0; i < orion_gpio_chip_count; i++) {
236 struct orion_gpio_chip *ochip = orion_gpio_chips + i;
237 struct gpio_chip *chip = &ochip->chip;
239 if (pin >= chip->base && pin < chip->base + chip->ngpio)
246 void __init orion_gpio_set_unused(unsigned pin)
248 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
253 pin -= ochip->chip.base;
255 /* Configure as output, drive low. */
256 __set_level(ochip, pin, 0);
257 __set_direction(ochip, pin, 0);
260 void __init orion_gpio_set_valid(unsigned pin, int mode)
262 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
267 pin -= ochip->chip.base;
270 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
272 if (mode & GPIO_INPUT_OK)
273 __set_bit(pin, &ochip->valid_input);
275 __clear_bit(pin, &ochip->valid_input);
277 if (mode & GPIO_OUTPUT_OK)
278 __set_bit(pin, &ochip->valid_output);
280 __clear_bit(pin, &ochip->valid_output);
283 void orion_gpio_set_blink(unsigned pin, int blink)
285 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
291 spin_lock_irqsave(&ochip->lock, flags);
292 __set_level(ochip, pin, 0);
293 __set_blinking(ochip, pin, blink);
294 spin_unlock_irqrestore(&ochip->lock, flags);
296 EXPORT_SYMBOL(orion_gpio_set_blink);
299 /*****************************************************************************
302 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
303 * value of the line or the opposite value.
305 * Level IRQ handlers: DATA_IN is used directly as cause register.
306 * Interrupt are masked by LEVEL_MASK registers.
307 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
308 * Interrupt are masked by EDGE_MASK registers.
309 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
310 * the polarity to catch the next line transaction.
311 * This is a race condition that might not perfectly
312 * work on some use cases.
314 * Every eight GPIO lines are grouped (OR'ed) before going up to main
318 * data-in /--------| |-----| |----\
319 * -----| |----- ---- to main cause reg
320 * X \----------------| |----/
321 * polarity LEVEL mask
323 ****************************************************************************/
324 static void gpio_irq_ack(struct irq_data *d)
326 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
329 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
330 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
331 int pin = d->irq - ochip->secondary_irq_base;
333 writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
337 static void gpio_irq_mask(struct irq_data *d)
339 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
344 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
345 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
346 reg = GPIO_EDGE_MASK(ochip);
348 reg = GPIO_LEVEL_MASK(ochip);
350 pin = d->irq - ochip->secondary_irq_base;
352 writel(readl(reg) & ~(1 << pin), reg);
355 static void gpio_irq_unmask(struct irq_data *d)
357 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
362 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
363 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
364 reg = GPIO_EDGE_MASK(ochip);
366 reg = GPIO_LEVEL_MASK(ochip);
368 pin = d->irq - ochip->secondary_irq_base;
370 writel(readl(reg) | (1 << pin), reg);
373 static int gpio_irq_set_type(struct irq_data *d, u32 type)
375 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
379 pin = d->irq - ochip->secondary_irq_base;
381 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
383 printk(KERN_ERR "orion gpio_irq_set_type failed "
384 "(irq %d, pin %d).\n", d->irq, pin);
389 * Set edge/level type.
391 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
392 set_irq_handler(d->irq, handle_edge_irq);
393 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
394 set_irq_handler(d->irq, handle_level_irq);
396 printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
402 * Configure interrupt polarity.
404 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
405 u = readl(GPIO_IN_POL(ochip));
407 writel(u, GPIO_IN_POL(ochip));
408 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
409 u = readl(GPIO_IN_POL(ochip));
411 writel(u, GPIO_IN_POL(ochip));
412 } else if (type == IRQ_TYPE_EDGE_BOTH) {
415 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
418 * set initial polarity based on current input level
420 u = readl(GPIO_IN_POL(ochip));
422 u |= 1 << pin; /* falling */
424 u &= ~(1 << pin); /* rising */
425 writel(u, GPIO_IN_POL(ochip));
431 struct irq_chip orion_gpio_irq_chip = {
432 .name = "orion_gpio_irq",
433 .irq_ack = gpio_irq_ack,
434 .irq_mask = gpio_irq_mask,
435 .irq_unmask = gpio_irq_unmask,
436 .irq_set_type = gpio_irq_set_type,
439 void __init orion_gpio_init(int gpio_base, int ngpio,
440 u32 base, int mask_offset, int secondary_irq_base)
442 struct orion_gpio_chip *ochip;
445 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
448 ochip = orion_gpio_chips + orion_gpio_chip_count;
449 ochip->chip.label = "orion_gpio";
450 ochip->chip.request = orion_gpio_request;
451 ochip->chip.direction_input = orion_gpio_direction_input;
452 ochip->chip.get = orion_gpio_get;
453 ochip->chip.direction_output = orion_gpio_direction_output;
454 ochip->chip.set = orion_gpio_set;
455 ochip->chip.to_irq = orion_gpio_to_irq;
456 ochip->chip.base = gpio_base;
457 ochip->chip.ngpio = ngpio;
458 ochip->chip.can_sleep = 0;
459 spin_lock_init(&ochip->lock);
460 ochip->base = (void __iomem *)base;
461 ochip->valid_input = 0;
462 ochip->valid_output = 0;
463 ochip->mask_offset = mask_offset;
464 ochip->secondary_irq_base = secondary_irq_base;
466 gpiochip_add(&ochip->chip);
468 orion_gpio_chip_count++;
471 * Mask and clear GPIO interrupts.
473 writel(0, GPIO_EDGE_CAUSE(ochip));
474 writel(0, GPIO_EDGE_MASK(ochip));
475 writel(0, GPIO_LEVEL_MASK(ochip));
477 for (i = 0; i < ngpio; i++) {
478 unsigned int irq = secondary_irq_base + i;
480 set_irq_chip(irq, &orion_gpio_irq_chip);
481 set_irq_handler(irq, handle_level_irq);
482 set_irq_chip_data(irq, ochip);
483 irq_desc[irq].status |= IRQ_LEVEL;
484 set_irq_flags(irq, IRQF_VALID);
488 void orion_gpio_irq_handler(int pinoff)
490 struct orion_gpio_chip *ochip;
494 ochip = orion_gpio_chip_find(pinoff);
498 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
499 cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
501 for (i = 0; i < ochip->chip.ngpio; i++) {
503 struct irq_desc *desc;
505 irq = ochip->secondary_irq_base + i;
507 if (!(cause & (1 << i)))
510 desc = irq_desc + irq;
511 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
512 /* Swap polarity (race with GPIO line) */
515 polarity = readl(GPIO_IN_POL(ochip));
517 writel(polarity, GPIO_IN_POL(ochip));
520 desc_handle_irq(irq, desc);