2 * OMAP clock: data structure definitions, function prototypes, shared macros
4 * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ARCH_ARM_OMAP_CLOCK_H
14 #define __ARCH_ARM_OMAP_CLOCK_H
16 #include <linux/list.h>
23 int (*enable)(struct clk *);
24 void (*disable)(struct clk *);
25 void (*find_idlest)(struct clk *, void __iomem **,
27 void (*find_companion)(struct clk *, void __iomem **,
31 #ifdef CONFIG_ARCH_OMAP2PLUS
41 const struct clksel_rate *rates;
45 * struct dpll_data - DPLL registers and integration data
46 * @mult_div1_reg: register containing the DPLL M and N bitfields
47 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
48 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
49 * @clk_bypass: struct clk pointer to the clock's bypass clock input
50 * @clk_ref: struct clk pointer to the clock's reference clock input
51 * @control_reg: register containing the DPLL mode bitfield
52 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
53 * @rate_tolerance: maximum variance allowed from target rate (in Hz)
54 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
55 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
56 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
57 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
58 * @min_divider: minimum valid non-bypass divider value (actual)
59 * @max_divider: maximum valid non-bypass divider value (actual)
60 * @modes: possible values of @enable_mask
61 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
62 * @idlest_reg: register containing the DPLL idle status bitfield
63 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
64 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
65 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
66 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
67 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
68 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
69 * @flags: DPLL type/features (see below)
71 * Possible values for @flags:
72 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
73 * NO_DCO_SEL: don't program DCO (only for some J-type DPLLs)
75 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
77 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
78 * correct to only have one @clk_bypass pointer.
80 * XXX @rate_tolerance should probably be deprecated - currently there
81 * don't seem to be any usecases for DPLL rounding that is not exact.
83 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
84 * @last_rounded_n) should be separated from the runtime-fixed fields
85 * and placed into a differenct structure, so that the runtime-fixed data
86 * can be placed into read-only space.
89 void __iomem *mult_div1_reg;
92 struct clk *clk_bypass;
94 void __iomem *control_reg;
96 unsigned int rate_tolerance;
97 unsigned long last_rounded_rate;
104 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
105 void __iomem *autoidle_reg;
106 void __iomem *idlest_reg;
120 struct list_head node;
121 const struct clkops *ops;
124 struct list_head children;
125 struct list_head sibling; /* node for children */
127 void __iomem *enable_reg;
128 unsigned long (*recalc)(struct clk *);
129 int (*set_rate)(struct clk *, unsigned long);
130 long (*round_rate)(struct clk *, unsigned long);
131 void (*init)(struct clk *);
136 #ifdef CONFIG_ARCH_OMAP2PLUS
137 void __iomem *clksel_reg;
139 const struct clksel *clksel;
140 struct dpll_data *dpll_data;
141 const char *clkdm_name;
142 struct clockdomain *clkdm;
147 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
148 struct dentry *dent; /* For visible tree hierarchy */
152 struct cpufreq_frequency_table;
154 struct clk_functions {
155 int (*clk_enable)(struct clk *clk);
156 void (*clk_disable)(struct clk *clk);
157 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
158 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
159 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
160 void (*clk_allow_idle)(struct clk *clk);
161 void (*clk_deny_idle)(struct clk *clk);
162 void (*clk_disable_unused)(struct clk *clk);
163 #ifdef CONFIG_CPU_FREQ
164 void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
165 void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
171 extern int clk_init(struct clk_functions *custom_clocks);
172 extern void clk_preinit(struct clk *clk);
173 extern int clk_register(struct clk *clk);
174 extern void clk_reparent(struct clk *child, struct clk *parent);
175 extern void clk_unregister(struct clk *clk);
176 extern void propagate_rate(struct clk *clk);
177 extern void recalculate_root_clocks(void);
178 extern unsigned long followparent_recalc(struct clk *clk);
179 extern void clk_enable_init_clocks(void);
180 unsigned long omap_fixed_divisor_recalc(struct clk *clk);
181 #ifdef CONFIG_CPU_FREQ
182 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
183 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
185 extern struct clk *omap_clk_get_by_name(const char *name);
187 extern const struct clkops clkops_null;
189 extern struct clk dummy_ck;
192 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
193 #define CLOCK_IDLE_CONTROL (1 << 1)
194 #define CLOCK_NO_IDLE_PARENT (1 << 2)
195 #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
196 #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
198 /* Clksel_rate flags */
199 #define RATE_IN_242X (1 << 0)
200 #define RATE_IN_243X (1 << 1)
201 #define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */
202 #define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */
203 #define RATE_IN_36XX (1 << 4)
204 #define RATE_IN_4430 (1 << 5)
206 #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
208 #define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX)