2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30 #include <plat/powerdomain.h>
33 * OMAP1510 GPIO registers
35 #define OMAP1510_GPIO_BASE 0xfffce000
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
44 #define OMAP1510_IH_GPIO_BASE 64
47 * OMAP1610 specific GPIO registers
49 #define OMAP1610_GPIO1_BASE 0xfffbe400
50 #define OMAP1610_GPIO2_BASE 0xfffbec00
51 #define OMAP1610_GPIO3_BASE 0xfffbb400
52 #define OMAP1610_GPIO4_BASE 0xfffbbc00
53 #define OMAP1610_GPIO_REVISION 0x0000
54 #define OMAP1610_GPIO_SYSCONFIG 0x0010
55 #define OMAP1610_GPIO_SYSSTATUS 0x0014
56 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
57 #define OMAP1610_GPIO_IRQENABLE1 0x001c
58 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
59 #define OMAP1610_GPIO_DATAIN 0x002c
60 #define OMAP1610_GPIO_DATAOUT 0x0030
61 #define OMAP1610_GPIO_DIRECTION 0x0034
62 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
63 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
64 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
65 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
66 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
67 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
68 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
69 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
72 * OMAP7XX specific GPIO registers
74 #define OMAP7XX_GPIO1_BASE 0xfffbc000
75 #define OMAP7XX_GPIO2_BASE 0xfffbc800
76 #define OMAP7XX_GPIO3_BASE 0xfffbd000
77 #define OMAP7XX_GPIO4_BASE 0xfffbd800
78 #define OMAP7XX_GPIO5_BASE 0xfffbe000
79 #define OMAP7XX_GPIO6_BASE 0xfffbe800
80 #define OMAP7XX_GPIO_DATA_INPUT 0x00
81 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
82 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
83 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
84 #define OMAP7XX_GPIO_INT_MASK 0x10
85 #define OMAP7XX_GPIO_INT_STATUS 0x14
87 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
90 * omap24xx specific GPIO registers
92 #define OMAP242X_GPIO1_BASE 0x48018000
93 #define OMAP242X_GPIO2_BASE 0x4801a000
94 #define OMAP242X_GPIO3_BASE 0x4801c000
95 #define OMAP242X_GPIO4_BASE 0x4801e000
97 #define OMAP243X_GPIO1_BASE 0x4900C000
98 #define OMAP243X_GPIO2_BASE 0x4900E000
99 #define OMAP243X_GPIO3_BASE 0x49010000
100 #define OMAP243X_GPIO4_BASE 0x49012000
101 #define OMAP243X_GPIO5_BASE 0x480B6000
103 #define OMAP24XX_GPIO_REVISION 0x0000
104 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
105 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
106 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
107 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
108 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
109 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
110 #define OMAP24XX_GPIO_WAKE_EN 0x0020
111 #define OMAP24XX_GPIO_CTRL 0x0030
112 #define OMAP24XX_GPIO_OE 0x0034
113 #define OMAP24XX_GPIO_DATAIN 0x0038
114 #define OMAP24XX_GPIO_DATAOUT 0x003c
115 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
116 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
117 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
118 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
119 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
120 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
121 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
122 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
123 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
124 #define OMAP24XX_GPIO_SETWKUENA 0x0084
125 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
126 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
128 #define OMAP4_GPIO_REVISION 0x0000
129 #define OMAP4_GPIO_SYSCONFIG 0x0010
130 #define OMAP4_GPIO_EOI 0x0020
131 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
132 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
133 #define OMAP4_GPIO_IRQSTATUS0 0x002c
134 #define OMAP4_GPIO_IRQSTATUS1 0x0030
135 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
136 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
137 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
138 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
139 #define OMAP4_GPIO_IRQWAKEN0 0x0044
140 #define OMAP4_GPIO_IRQWAKEN1 0x0048
141 #define OMAP4_GPIO_SYSSTATUS 0x0114
142 #define OMAP4_GPIO_IRQENABLE1 0x011c
143 #define OMAP4_GPIO_WAKE_EN 0x0120
144 #define OMAP4_GPIO_IRQSTATUS2 0x0128
145 #define OMAP4_GPIO_IRQENABLE2 0x012c
146 #define OMAP4_GPIO_CTRL 0x0130
147 #define OMAP4_GPIO_OE 0x0134
148 #define OMAP4_GPIO_DATAIN 0x0138
149 #define OMAP4_GPIO_DATAOUT 0x013c
150 #define OMAP4_GPIO_LEVELDETECT0 0x0140
151 #define OMAP4_GPIO_LEVELDETECT1 0x0144
152 #define OMAP4_GPIO_RISINGDETECT 0x0148
153 #define OMAP4_GPIO_FALLINGDETECT 0x014c
154 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
155 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
156 #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
157 #define OMAP4_GPIO_SETIRQENABLE1 0x0164
158 #define OMAP4_GPIO_CLEARWKUENA 0x0180
159 #define OMAP4_GPIO_SETWKUENA 0x0184
160 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
161 #define OMAP4_GPIO_SETDATAOUT 0x0194
163 * omap34xx specific GPIO registers
166 #define OMAP34XX_GPIO1_BASE 0x48310000
167 #define OMAP34XX_GPIO2_BASE 0x49050000
168 #define OMAP34XX_GPIO3_BASE 0x49052000
169 #define OMAP34XX_GPIO4_BASE 0x49054000
170 #define OMAP34XX_GPIO5_BASE 0x49056000
171 #define OMAP34XX_GPIO6_BASE 0x49058000
174 * OMAP44XX specific GPIO registers
176 #define OMAP44XX_GPIO1_BASE 0x4a310000
177 #define OMAP44XX_GPIO2_BASE 0x48055000
178 #define OMAP44XX_GPIO3_BASE 0x48057000
179 #define OMAP44XX_GPIO4_BASE 0x48059000
180 #define OMAP44XX_GPIO5_BASE 0x4805B000
181 #define OMAP44XX_GPIO6_BASE 0x4805D000
187 u16 virtual_irq_start;
189 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
193 #ifdef CONFIG_ARCH_OMAP2PLUS
194 u32 non_wakeup_gpios;
195 u32 enabled_non_wakeup_gpios;
198 u32 saved_fallingdetect;
199 u32 saved_risingdetect;
204 struct gpio_chip chip;
207 u32 dbck_enable_mask;
210 #define METHOD_MPUIO 0
211 #define METHOD_GPIO_1510 1
212 #define METHOD_GPIO_1610 2
213 #define METHOD_GPIO_7XX 3
214 #define METHOD_GPIO_24XX 5
215 #define METHOD_GPIO_44XX 6
217 #ifdef CONFIG_ARCH_OMAP16XX
218 static struct gpio_bank gpio_bank_1610[5] = {
219 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
221 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
223 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
225 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
227 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
232 #ifdef CONFIG_ARCH_OMAP15XX
233 static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
236 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
241 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
242 static struct gpio_bank gpio_bank_7xx[7] = {
243 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
245 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
247 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
249 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
251 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
253 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
255 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
260 #ifdef CONFIG_ARCH_OMAP2
262 static struct gpio_bank gpio_bank_242x[4] = {
263 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
265 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
267 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
269 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
273 static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
276 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
278 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
280 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
282 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
288 #ifdef CONFIG_ARCH_OMAP3
289 static struct gpio_bank gpio_bank_34xx[6] = {
290 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
292 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
294 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
296 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
298 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
300 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
304 struct omap3_gpio_regs {
318 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
321 #ifdef CONFIG_ARCH_OMAP4
322 static struct gpio_bank gpio_bank_44xx[6] = {
323 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
325 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
327 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
329 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
331 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
333 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
339 static struct gpio_bank *gpio_bank;
340 static int gpio_bank_count;
342 static inline struct gpio_bank *get_gpio_bank(int gpio)
344 if (cpu_is_omap15xx()) {
345 if (OMAP_GPIO_IS_MPUIO(gpio))
346 return &gpio_bank[0];
347 return &gpio_bank[1];
349 if (cpu_is_omap16xx()) {
350 if (OMAP_GPIO_IS_MPUIO(gpio))
351 return &gpio_bank[0];
352 return &gpio_bank[1 + (gpio >> 4)];
354 if (cpu_is_omap7xx()) {
355 if (OMAP_GPIO_IS_MPUIO(gpio))
356 return &gpio_bank[0];
357 return &gpio_bank[1 + (gpio >> 5)];
359 if (cpu_is_omap24xx())
360 return &gpio_bank[gpio >> 5];
361 if (cpu_is_omap34xx() || cpu_is_omap44xx())
362 return &gpio_bank[gpio >> 5];
367 static inline int get_gpio_index(int gpio)
369 if (cpu_is_omap7xx())
371 if (cpu_is_omap24xx())
373 if (cpu_is_omap34xx() || cpu_is_omap44xx())
378 static inline int gpio_valid(int gpio)
382 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
383 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
387 if (cpu_is_omap15xx() && gpio < 16)
389 if ((cpu_is_omap16xx()) && gpio < 64)
391 if (cpu_is_omap7xx() && gpio < 192)
393 if (cpu_is_omap24xx() && gpio < 128)
395 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
400 static int check_gpio(int gpio)
402 if (unlikely(gpio_valid(gpio) < 0)) {
403 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
410 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
412 void __iomem *reg = bank->base;
415 switch (bank->method) {
416 #ifdef CONFIG_ARCH_OMAP1
418 reg += OMAP_MPUIO_IO_CNTL;
421 #ifdef CONFIG_ARCH_OMAP15XX
422 case METHOD_GPIO_1510:
423 reg += OMAP1510_GPIO_DIR_CONTROL;
426 #ifdef CONFIG_ARCH_OMAP16XX
427 case METHOD_GPIO_1610:
428 reg += OMAP1610_GPIO_DIRECTION;
431 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
432 case METHOD_GPIO_7XX:
433 reg += OMAP7XX_GPIO_DIR_CONTROL;
436 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
437 case METHOD_GPIO_24XX:
438 reg += OMAP24XX_GPIO_OE;
441 #if defined(CONFIG_ARCH_OMAP4)
442 case METHOD_GPIO_44XX:
443 reg += OMAP4_GPIO_OE;
450 l = __raw_readl(reg);
455 __raw_writel(l, reg);
458 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
460 void __iomem *reg = bank->base;
463 switch (bank->method) {
464 #ifdef CONFIG_ARCH_OMAP1
466 reg += OMAP_MPUIO_OUTPUT;
467 l = __raw_readl(reg);
474 #ifdef CONFIG_ARCH_OMAP15XX
475 case METHOD_GPIO_1510:
476 reg += OMAP1510_GPIO_DATA_OUTPUT;
477 l = __raw_readl(reg);
484 #ifdef CONFIG_ARCH_OMAP16XX
485 case METHOD_GPIO_1610:
487 reg += OMAP1610_GPIO_SET_DATAOUT;
489 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
493 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
494 case METHOD_GPIO_7XX:
495 reg += OMAP7XX_GPIO_DATA_OUTPUT;
496 l = __raw_readl(reg);
503 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
504 case METHOD_GPIO_24XX:
506 reg += OMAP24XX_GPIO_SETDATAOUT;
508 reg += OMAP24XX_GPIO_CLEARDATAOUT;
512 #ifdef CONFIG_ARCH_OMAP4
513 case METHOD_GPIO_44XX:
515 reg += OMAP4_GPIO_SETDATAOUT;
517 reg += OMAP4_GPIO_CLEARDATAOUT;
525 __raw_writel(l, reg);
528 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
532 if (check_gpio(gpio) < 0)
535 switch (bank->method) {
536 #ifdef CONFIG_ARCH_OMAP1
538 reg += OMAP_MPUIO_INPUT_LATCH;
541 #ifdef CONFIG_ARCH_OMAP15XX
542 case METHOD_GPIO_1510:
543 reg += OMAP1510_GPIO_DATA_INPUT;
546 #ifdef CONFIG_ARCH_OMAP16XX
547 case METHOD_GPIO_1610:
548 reg += OMAP1610_GPIO_DATAIN;
551 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
552 case METHOD_GPIO_7XX:
553 reg += OMAP7XX_GPIO_DATA_INPUT;
556 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
557 case METHOD_GPIO_24XX:
558 reg += OMAP24XX_GPIO_DATAIN;
561 #ifdef CONFIG_ARCH_OMAP4
562 case METHOD_GPIO_44XX:
563 reg += OMAP4_GPIO_DATAIN;
569 return (__raw_readl(reg)
570 & (1 << get_gpio_index(gpio))) != 0;
573 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
577 if (check_gpio(gpio) < 0)
581 switch (bank->method) {
582 #ifdef CONFIG_ARCH_OMAP1
584 reg += OMAP_MPUIO_OUTPUT;
587 #ifdef CONFIG_ARCH_OMAP15XX
588 case METHOD_GPIO_1510:
589 reg += OMAP1510_GPIO_DATA_OUTPUT;
592 #ifdef CONFIG_ARCH_OMAP16XX
593 case METHOD_GPIO_1610:
594 reg += OMAP1610_GPIO_DATAOUT;
597 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
598 case METHOD_GPIO_7XX:
599 reg += OMAP7XX_GPIO_DATA_OUTPUT;
602 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
603 case METHOD_GPIO_24XX:
604 reg += OMAP24XX_GPIO_DATAOUT;
607 #ifdef CONFIG_ARCH_OMAP4
608 case METHOD_GPIO_44XX:
609 reg += OMAP4_GPIO_DATAOUT;
616 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
619 #define MOD_REG_BIT(reg, bit_mask, set) \
621 int l = __raw_readl(base + reg); \
622 if (set) l |= bit_mask; \
623 else l &= ~bit_mask; \
624 __raw_writel(l, base + reg); \
628 * _set_gpio_debounce - low level gpio debounce time
629 * @bank: the gpio bank we're acting upon
630 * @gpio: the gpio number on this @gpio
631 * @debounce: debounce time to use
633 * OMAP's debounce time is in 31us steps so we need
634 * to convert and round up to the closest unit.
636 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
639 void __iomem *reg = bank->base;
645 else if (debounce > 7936)
648 debounce = (debounce / 0x1f) - 1;
650 l = 1 << get_gpio_index(gpio);
652 if (cpu_is_omap44xx())
653 reg += OMAP4_GPIO_DEBOUNCINGTIME;
655 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
657 __raw_writel(debounce, reg);
660 if (cpu_is_omap44xx())
661 reg += OMAP4_GPIO_DEBOUNCENABLE;
663 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
665 val = __raw_readl(reg);
669 if (cpu_is_omap34xx() || cpu_is_omap44xx())
670 clk_enable(bank->dbck);
673 if (cpu_is_omap34xx() || cpu_is_omap44xx())
674 clk_disable(bank->dbck);
677 __raw_writel(val, reg);
680 #ifdef CONFIG_ARCH_OMAP2PLUS
681 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
684 void __iomem *base = bank->base;
685 u32 gpio_bit = 1 << gpio;
688 if (cpu_is_omap44xx()) {
689 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
690 trigger & IRQ_TYPE_LEVEL_LOW);
691 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
692 trigger & IRQ_TYPE_LEVEL_HIGH);
693 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
694 trigger & IRQ_TYPE_EDGE_RISING);
695 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
696 trigger & IRQ_TYPE_EDGE_FALLING);
698 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
699 trigger & IRQ_TYPE_LEVEL_LOW);
700 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
701 trigger & IRQ_TYPE_LEVEL_HIGH);
702 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
703 trigger & IRQ_TYPE_EDGE_RISING);
704 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
705 trigger & IRQ_TYPE_EDGE_FALLING);
707 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
708 if (cpu_is_omap44xx()) {
710 __raw_writel(1 << gpio, bank->base+
711 OMAP4_GPIO_IRQWAKEN0);
713 val = __raw_readl(bank->base +
714 OMAP4_GPIO_IRQWAKEN0);
715 __raw_writel(val & (~(1 << gpio)), bank->base +
716 OMAP4_GPIO_IRQWAKEN0);
720 * GPIO wakeup request can only be generated on edge
723 if (trigger & IRQ_TYPE_EDGE_BOTH)
724 __raw_writel(1 << gpio, bank->base
725 + OMAP24XX_GPIO_SETWKUENA);
727 __raw_writel(1 << gpio, bank->base
728 + OMAP24XX_GPIO_CLEARWKUENA);
731 /* This part needs to be executed always for OMAP34xx */
732 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
734 * Log the edge gpio and manually trigger the IRQ
735 * after resume if the input level changes
736 * to avoid irq lost during PER RET/OFF mode
737 * Applies for omap2 non-wakeup gpio and all omap3 gpios
739 if (trigger & IRQ_TYPE_EDGE_BOTH)
740 bank->enabled_non_wakeup_gpios |= gpio_bit;
742 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
745 if (cpu_is_omap44xx()) {
747 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
748 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
751 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
752 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
757 #ifdef CONFIG_ARCH_OMAP1
759 * This only applies to chips that can't do both rising and falling edge
760 * detection at once. For all other chips, this function is a noop.
762 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
764 void __iomem *reg = bank->base;
767 switch (bank->method) {
769 reg += OMAP_MPUIO_GPIO_INT_EDGE;
771 #ifdef CONFIG_ARCH_OMAP15XX
772 case METHOD_GPIO_1510:
773 reg += OMAP1510_GPIO_INT_CONTROL;
776 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
777 case METHOD_GPIO_7XX:
778 reg += OMAP7XX_GPIO_INT_CONTROL;
785 l = __raw_readl(reg);
791 __raw_writel(l, reg);
795 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
797 void __iomem *reg = bank->base;
800 switch (bank->method) {
801 #ifdef CONFIG_ARCH_OMAP1
803 reg += OMAP_MPUIO_GPIO_INT_EDGE;
804 l = __raw_readl(reg);
805 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
806 bank->toggle_mask |= 1 << gpio;
807 if (trigger & IRQ_TYPE_EDGE_RISING)
809 else if (trigger & IRQ_TYPE_EDGE_FALLING)
815 #ifdef CONFIG_ARCH_OMAP15XX
816 case METHOD_GPIO_1510:
817 reg += OMAP1510_GPIO_INT_CONTROL;
818 l = __raw_readl(reg);
819 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
820 bank->toggle_mask |= 1 << gpio;
821 if (trigger & IRQ_TYPE_EDGE_RISING)
823 else if (trigger & IRQ_TYPE_EDGE_FALLING)
829 #ifdef CONFIG_ARCH_OMAP16XX
830 case METHOD_GPIO_1610:
832 reg += OMAP1610_GPIO_EDGE_CTRL2;
834 reg += OMAP1610_GPIO_EDGE_CTRL1;
836 l = __raw_readl(reg);
837 l &= ~(3 << (gpio << 1));
838 if (trigger & IRQ_TYPE_EDGE_RISING)
839 l |= 2 << (gpio << 1);
840 if (trigger & IRQ_TYPE_EDGE_FALLING)
841 l |= 1 << (gpio << 1);
843 /* Enable wake-up during idle for dynamic tick */
844 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
846 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
849 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
850 case METHOD_GPIO_7XX:
851 reg += OMAP7XX_GPIO_INT_CONTROL;
852 l = __raw_readl(reg);
853 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
854 bank->toggle_mask |= 1 << gpio;
855 if (trigger & IRQ_TYPE_EDGE_RISING)
857 else if (trigger & IRQ_TYPE_EDGE_FALLING)
863 #ifdef CONFIG_ARCH_OMAP2PLUS
864 case METHOD_GPIO_24XX:
865 case METHOD_GPIO_44XX:
866 set_24xx_gpio_triggering(bank, gpio, trigger);
872 __raw_writel(l, reg);
878 static int gpio_irq_type(unsigned irq, unsigned type)
880 struct gpio_bank *bank;
885 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
886 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
888 gpio = irq - IH_GPIO_BASE;
890 if (check_gpio(gpio) < 0)
893 if (type & ~IRQ_TYPE_SENSE_MASK)
896 /* OMAP1 allows only only edge triggering */
897 if (!cpu_class_is_omap2()
898 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
901 bank = get_irq_chip_data(irq);
902 spin_lock_irqsave(&bank->lock, flags);
903 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
905 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
906 irq_desc[irq].status |= type;
908 spin_unlock_irqrestore(&bank->lock, flags);
910 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
911 __set_irq_handler_unlocked(irq, handle_level_irq);
912 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
913 __set_irq_handler_unlocked(irq, handle_edge_irq);
918 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
920 void __iomem *reg = bank->base;
922 switch (bank->method) {
923 #ifdef CONFIG_ARCH_OMAP1
925 /* MPUIO irqstatus is reset by reading the status register,
926 * so do nothing here */
929 #ifdef CONFIG_ARCH_OMAP15XX
930 case METHOD_GPIO_1510:
931 reg += OMAP1510_GPIO_INT_STATUS;
934 #ifdef CONFIG_ARCH_OMAP16XX
935 case METHOD_GPIO_1610:
936 reg += OMAP1610_GPIO_IRQSTATUS1;
939 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
940 case METHOD_GPIO_7XX:
941 reg += OMAP7XX_GPIO_INT_STATUS;
944 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
945 case METHOD_GPIO_24XX:
946 reg += OMAP24XX_GPIO_IRQSTATUS1;
949 #if defined(CONFIG_ARCH_OMAP4)
950 case METHOD_GPIO_44XX:
951 reg += OMAP4_GPIO_IRQSTATUS0;
958 __raw_writel(gpio_mask, reg);
960 /* Workaround for clearing DSP GPIO interrupts to allow retention */
961 if (cpu_is_omap24xx() || cpu_is_omap34xx())
962 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
963 else if (cpu_is_omap44xx())
964 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
966 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
967 __raw_writel(gpio_mask, reg);
969 /* Flush posted write for the irq status to avoid spurious interrupts */
974 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
976 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
979 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
981 void __iomem *reg = bank->base;
986 switch (bank->method) {
987 #ifdef CONFIG_ARCH_OMAP1
989 reg += OMAP_MPUIO_GPIO_MASKIT;
994 #ifdef CONFIG_ARCH_OMAP15XX
995 case METHOD_GPIO_1510:
996 reg += OMAP1510_GPIO_INT_MASK;
1001 #ifdef CONFIG_ARCH_OMAP16XX
1002 case METHOD_GPIO_1610:
1003 reg += OMAP1610_GPIO_IRQENABLE1;
1007 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1008 case METHOD_GPIO_7XX:
1009 reg += OMAP7XX_GPIO_INT_MASK;
1014 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1015 case METHOD_GPIO_24XX:
1016 reg += OMAP24XX_GPIO_IRQENABLE1;
1020 #if defined(CONFIG_ARCH_OMAP4)
1021 case METHOD_GPIO_44XX:
1022 reg += OMAP4_GPIO_IRQSTATUSSET0;
1031 l = __raw_readl(reg);
1038 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1040 void __iomem *reg = bank->base;
1043 switch (bank->method) {
1044 #ifdef CONFIG_ARCH_OMAP1
1046 reg += OMAP_MPUIO_GPIO_MASKIT;
1047 l = __raw_readl(reg);
1054 #ifdef CONFIG_ARCH_OMAP15XX
1055 case METHOD_GPIO_1510:
1056 reg += OMAP1510_GPIO_INT_MASK;
1057 l = __raw_readl(reg);
1064 #ifdef CONFIG_ARCH_OMAP16XX
1065 case METHOD_GPIO_1610:
1067 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1069 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1073 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1074 case METHOD_GPIO_7XX:
1075 reg += OMAP7XX_GPIO_INT_MASK;
1076 l = __raw_readl(reg);
1083 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1084 case METHOD_GPIO_24XX:
1086 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1088 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1092 #ifdef CONFIG_ARCH_OMAP4
1093 case METHOD_GPIO_44XX:
1095 reg += OMAP4_GPIO_IRQSTATUSSET0;
1097 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1105 __raw_writel(l, reg);
1108 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1110 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1114 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1115 * 1510 does not seem to have a wake-up register. If JTAG is connected
1116 * to the target, system will wake up always on GPIO events. While
1117 * system is running all registered GPIO interrupts need to have wake-up
1118 * enabled. When system is suspended, only selected GPIO interrupts need
1119 * to have wake-up enabled.
1121 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1123 unsigned long uninitialized_var(flags);
1125 switch (bank->method) {
1126 #ifdef CONFIG_ARCH_OMAP16XX
1128 case METHOD_GPIO_1610:
1129 spin_lock_irqsave(&bank->lock, flags);
1131 bank->suspend_wakeup |= (1 << gpio);
1133 bank->suspend_wakeup &= ~(1 << gpio);
1134 spin_unlock_irqrestore(&bank->lock, flags);
1137 #ifdef CONFIG_ARCH_OMAP2PLUS
1138 case METHOD_GPIO_24XX:
1139 case METHOD_GPIO_44XX:
1140 if (bank->non_wakeup_gpios & (1 << gpio)) {
1141 printk(KERN_ERR "Unable to modify wakeup on "
1142 "non-wakeup GPIO%d\n",
1143 (bank - gpio_bank) * 32 + gpio);
1146 spin_lock_irqsave(&bank->lock, flags);
1148 bank->suspend_wakeup |= (1 << gpio);
1150 bank->suspend_wakeup &= ~(1 << gpio);
1151 spin_unlock_irqrestore(&bank->lock, flags);
1155 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1161 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1163 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1164 _set_gpio_irqenable(bank, gpio, 0);
1165 _clear_gpio_irqstatus(bank, gpio);
1166 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1169 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1170 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1172 unsigned int gpio = irq - IH_GPIO_BASE;
1173 struct gpio_bank *bank;
1176 if (check_gpio(gpio) < 0)
1178 bank = get_irq_chip_data(irq);
1179 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1184 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1186 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1187 unsigned long flags;
1189 spin_lock_irqsave(&bank->lock, flags);
1191 /* Set trigger to none. You need to enable the desired trigger with
1192 * request_irq() or set_irq_type().
1194 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1196 #ifdef CONFIG_ARCH_OMAP15XX
1197 if (bank->method == METHOD_GPIO_1510) {
1200 /* Claim the pin for MPU */
1201 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1202 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1205 if (!cpu_class_is_omap1()) {
1206 if (!bank->mod_usage) {
1207 void __iomem *reg = bank->base;
1210 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1211 reg += OMAP24XX_GPIO_CTRL;
1212 else if (cpu_is_omap44xx())
1213 reg += OMAP4_GPIO_CTRL;
1214 ctrl = __raw_readl(reg);
1215 /* Module is enabled, clocks are not gated */
1217 __raw_writel(ctrl, reg);
1219 bank->mod_usage |= 1 << offset;
1221 spin_unlock_irqrestore(&bank->lock, flags);
1226 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1228 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1229 unsigned long flags;
1231 spin_lock_irqsave(&bank->lock, flags);
1232 #ifdef CONFIG_ARCH_OMAP16XX
1233 if (bank->method == METHOD_GPIO_1610) {
1234 /* Disable wake-up during idle for dynamic tick */
1235 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1236 __raw_writel(1 << offset, reg);
1239 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1240 if (bank->method == METHOD_GPIO_24XX) {
1241 /* Disable wake-up during idle for dynamic tick */
1242 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1243 __raw_writel(1 << offset, reg);
1246 #ifdef CONFIG_ARCH_OMAP4
1247 if (bank->method == METHOD_GPIO_44XX) {
1248 /* Disable wake-up during idle for dynamic tick */
1249 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1250 __raw_writel(1 << offset, reg);
1253 if (!cpu_class_is_omap1()) {
1254 bank->mod_usage &= ~(1 << offset);
1255 if (!bank->mod_usage) {
1256 void __iomem *reg = bank->base;
1259 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1260 reg += OMAP24XX_GPIO_CTRL;
1261 else if (cpu_is_omap44xx())
1262 reg += OMAP4_GPIO_CTRL;
1263 ctrl = __raw_readl(reg);
1264 /* Module is disabled, clocks are gated */
1266 __raw_writel(ctrl, reg);
1269 _reset_gpio(bank, bank->chip.base + offset);
1270 spin_unlock_irqrestore(&bank->lock, flags);
1274 * We need to unmask the GPIO bank interrupt as soon as possible to
1275 * avoid missing GPIO interrupts for other lines in the bank.
1276 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1277 * in the bank to avoid missing nested interrupts for a GPIO line.
1278 * If we wait to unmask individual GPIO lines in the bank after the
1279 * line's interrupt handler has been run, we may miss some nested
1282 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1284 void __iomem *isr_reg = NULL;
1286 unsigned int gpio_irq, gpio_index;
1287 struct gpio_bank *bank;
1291 desc->chip->ack(irq);
1293 bank = get_irq_data(irq);
1294 #ifdef CONFIG_ARCH_OMAP1
1295 if (bank->method == METHOD_MPUIO)
1296 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1298 #ifdef CONFIG_ARCH_OMAP15XX
1299 if (bank->method == METHOD_GPIO_1510)
1300 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1302 #if defined(CONFIG_ARCH_OMAP16XX)
1303 if (bank->method == METHOD_GPIO_1610)
1304 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1306 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1307 if (bank->method == METHOD_GPIO_7XX)
1308 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1310 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1311 if (bank->method == METHOD_GPIO_24XX)
1312 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1314 #if defined(CONFIG_ARCH_OMAP4)
1315 if (bank->method == METHOD_GPIO_44XX)
1316 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1319 u32 isr_saved, level_mask = 0;
1322 enabled = _get_gpio_irqbank_mask(bank);
1323 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1325 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1328 if (cpu_class_is_omap2()) {
1329 level_mask = bank->level_mask & enabled;
1332 /* clear edge sensitive interrupts before handler(s) are
1333 called so that we don't miss any interrupt occurred while
1335 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1336 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1337 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1339 /* if there is only edge sensitive GPIO pin interrupts
1340 configured, we could unmask GPIO bank interrupt immediately */
1341 if (!level_mask && !unmasked) {
1343 desc->chip->unmask(irq);
1351 gpio_irq = bank->virtual_irq_start;
1352 for (; isr != 0; isr >>= 1, gpio_irq++) {
1353 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1358 #ifdef CONFIG_ARCH_OMAP1
1360 * Some chips can't respond to both rising and falling
1361 * at the same time. If this irq was requested with
1362 * both flags, we need to flip the ICR data for the IRQ
1363 * to respond to the IRQ for the opposite direction.
1364 * This will be indicated in the bank toggle_mask.
1366 if (bank->toggle_mask & (1 << gpio_index))
1367 _toggle_gpio_edge_triggering(bank, gpio_index);
1370 generic_handle_irq(gpio_irq);
1373 /* if bank has any level sensitive GPIO pin interrupt
1374 configured, we must unmask the bank interrupt only after
1375 handler(s) are executed in order to avoid spurious bank
1378 desc->chip->unmask(irq);
1382 static void gpio_irq_shutdown(unsigned int irq)
1384 unsigned int gpio = irq - IH_GPIO_BASE;
1385 struct gpio_bank *bank = get_irq_chip_data(irq);
1387 _reset_gpio(bank, gpio);
1390 static void gpio_ack_irq(unsigned int irq)
1392 unsigned int gpio = irq - IH_GPIO_BASE;
1393 struct gpio_bank *bank = get_irq_chip_data(irq);
1395 _clear_gpio_irqstatus(bank, gpio);
1398 static void gpio_mask_irq(unsigned int irq)
1400 unsigned int gpio = irq - IH_GPIO_BASE;
1401 struct gpio_bank *bank = get_irq_chip_data(irq);
1403 _set_gpio_irqenable(bank, gpio, 0);
1404 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1407 static void gpio_unmask_irq(unsigned int irq)
1409 unsigned int gpio = irq - IH_GPIO_BASE;
1410 struct gpio_bank *bank = get_irq_chip_data(irq);
1411 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1412 struct irq_desc *desc = irq_to_desc(irq);
1413 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1416 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1418 /* For level-triggered GPIOs, the clearing must be done after
1419 * the HW source is cleared, thus after the handler has run */
1420 if (bank->level_mask & irq_mask) {
1421 _set_gpio_irqenable(bank, gpio, 0);
1422 _clear_gpio_irqstatus(bank, gpio);
1425 _set_gpio_irqenable(bank, gpio, 1);
1428 static struct irq_chip gpio_irq_chip = {
1430 .shutdown = gpio_irq_shutdown,
1431 .ack = gpio_ack_irq,
1432 .mask = gpio_mask_irq,
1433 .unmask = gpio_unmask_irq,
1434 .set_type = gpio_irq_type,
1435 .set_wake = gpio_wake_enable,
1438 /*---------------------------------------------------------------------*/
1440 #ifdef CONFIG_ARCH_OMAP1
1442 /* MPUIO uses the always-on 32k clock */
1444 static void mpuio_ack_irq(unsigned int irq)
1446 /* The ISR is reset automatically, so do nothing here. */
1449 static void mpuio_mask_irq(unsigned int irq)
1451 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1452 struct gpio_bank *bank = get_irq_chip_data(irq);
1454 _set_gpio_irqenable(bank, gpio, 0);
1457 static void mpuio_unmask_irq(unsigned int irq)
1459 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1460 struct gpio_bank *bank = get_irq_chip_data(irq);
1462 _set_gpio_irqenable(bank, gpio, 1);
1465 static struct irq_chip mpuio_irq_chip = {
1467 .ack = mpuio_ack_irq,
1468 .mask = mpuio_mask_irq,
1469 .unmask = mpuio_unmask_irq,
1470 .set_type = gpio_irq_type,
1471 #ifdef CONFIG_ARCH_OMAP16XX
1472 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1473 .set_wake = gpio_wake_enable,
1478 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1481 #ifdef CONFIG_ARCH_OMAP16XX
1483 #include <linux/platform_device.h>
1485 static int omap_mpuio_suspend_noirq(struct device *dev)
1487 struct platform_device *pdev = to_platform_device(dev);
1488 struct gpio_bank *bank = platform_get_drvdata(pdev);
1489 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1490 unsigned long flags;
1492 spin_lock_irqsave(&bank->lock, flags);
1493 bank->saved_wakeup = __raw_readl(mask_reg);
1494 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1495 spin_unlock_irqrestore(&bank->lock, flags);
1500 static int omap_mpuio_resume_noirq(struct device *dev)
1502 struct platform_device *pdev = to_platform_device(dev);
1503 struct gpio_bank *bank = platform_get_drvdata(pdev);
1504 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1505 unsigned long flags;
1507 spin_lock_irqsave(&bank->lock, flags);
1508 __raw_writel(bank->saved_wakeup, mask_reg);
1509 spin_unlock_irqrestore(&bank->lock, flags);
1514 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1515 .suspend_noirq = omap_mpuio_suspend_noirq,
1516 .resume_noirq = omap_mpuio_resume_noirq,
1519 /* use platform_driver for this, now that there's no longer any
1520 * point to sys_device (other than not disturbing old code).
1522 static struct platform_driver omap_mpuio_driver = {
1525 .pm = &omap_mpuio_dev_pm_ops,
1529 static struct platform_device omap_mpuio_device = {
1533 .driver = &omap_mpuio_driver.driver,
1535 /* could list the /proc/iomem resources */
1538 static inline void mpuio_init(void)
1540 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1542 if (platform_driver_register(&omap_mpuio_driver) == 0)
1543 (void) platform_device_register(&omap_mpuio_device);
1547 static inline void mpuio_init(void) {}
1552 extern struct irq_chip mpuio_irq_chip;
1554 #define bank_is_mpuio(bank) 0
1555 static inline void mpuio_init(void) {}
1559 /*---------------------------------------------------------------------*/
1561 /* REVISIT these are stupid implementations! replace by ones that
1562 * don't switch on METHOD_* and which mostly avoid spinlocks
1565 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1567 struct gpio_bank *bank;
1568 unsigned long flags;
1570 bank = container_of(chip, struct gpio_bank, chip);
1571 spin_lock_irqsave(&bank->lock, flags);
1572 _set_gpio_direction(bank, offset, 1);
1573 spin_unlock_irqrestore(&bank->lock, flags);
1577 static int gpio_is_input(struct gpio_bank *bank, int mask)
1579 void __iomem *reg = bank->base;
1581 switch (bank->method) {
1583 reg += OMAP_MPUIO_IO_CNTL;
1585 case METHOD_GPIO_1510:
1586 reg += OMAP1510_GPIO_DIR_CONTROL;
1588 case METHOD_GPIO_1610:
1589 reg += OMAP1610_GPIO_DIRECTION;
1591 case METHOD_GPIO_7XX:
1592 reg += OMAP7XX_GPIO_DIR_CONTROL;
1594 case METHOD_GPIO_24XX:
1595 reg += OMAP24XX_GPIO_OE;
1597 case METHOD_GPIO_44XX:
1598 reg += OMAP4_GPIO_OE;
1601 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1604 return __raw_readl(reg) & mask;
1607 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1609 struct gpio_bank *bank;
1614 gpio = chip->base + offset;
1615 bank = get_gpio_bank(gpio);
1617 mask = 1 << get_gpio_index(gpio);
1619 if (gpio_is_input(bank, mask))
1620 return _get_gpio_datain(bank, gpio);
1622 return _get_gpio_dataout(bank, gpio);
1625 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1627 struct gpio_bank *bank;
1628 unsigned long flags;
1630 bank = container_of(chip, struct gpio_bank, chip);
1631 spin_lock_irqsave(&bank->lock, flags);
1632 _set_gpio_dataout(bank, offset, value);
1633 _set_gpio_direction(bank, offset, 0);
1634 spin_unlock_irqrestore(&bank->lock, flags);
1638 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1641 struct gpio_bank *bank;
1642 unsigned long flags;
1644 bank = container_of(chip, struct gpio_bank, chip);
1645 spin_lock_irqsave(&bank->lock, flags);
1646 _set_gpio_debounce(bank, offset, debounce);
1647 spin_unlock_irqrestore(&bank->lock, flags);
1652 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1654 struct gpio_bank *bank;
1655 unsigned long flags;
1657 bank = container_of(chip, struct gpio_bank, chip);
1658 spin_lock_irqsave(&bank->lock, flags);
1659 _set_gpio_dataout(bank, offset, value);
1660 spin_unlock_irqrestore(&bank->lock, flags);
1663 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1665 struct gpio_bank *bank;
1667 bank = container_of(chip, struct gpio_bank, chip);
1668 return bank->virtual_irq_start + offset;
1671 /*---------------------------------------------------------------------*/
1673 static int initialized;
1674 #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1675 static struct clk * gpio_ick;
1678 #if defined(CONFIG_ARCH_OMAP2)
1679 static struct clk * gpio_fck;
1682 #if defined(CONFIG_ARCH_OMAP2430)
1683 static struct clk * gpio5_ick;
1684 static struct clk * gpio5_fck;
1687 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1688 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1691 static void __init omap_gpio_show_rev(void)
1695 if (cpu_is_omap16xx())
1696 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1697 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1698 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1699 else if (cpu_is_omap44xx())
1700 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1704 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1705 (rev >> 4) & 0x0f, rev & 0x0f);
1708 /* This lock class tells lockdep that GPIO irqs are in a different
1709 * category than their parents, so it won't report false recursion.
1711 static struct lock_class_key gpio_lock_class;
1713 static int __init _omap_gpio_init(void)
1717 struct gpio_bank *bank;
1718 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1723 #if defined(CONFIG_ARCH_OMAP1)
1724 if (cpu_is_omap15xx()) {
1725 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1726 if (IS_ERR(gpio_ick))
1727 printk("Could not get arm_gpio_ck\n");
1729 clk_enable(gpio_ick);
1732 #if defined(CONFIG_ARCH_OMAP2)
1733 if (cpu_class_is_omap2()) {
1734 gpio_ick = clk_get(NULL, "gpios_ick");
1735 if (IS_ERR(gpio_ick))
1736 printk("Could not get gpios_ick\n");
1738 clk_enable(gpio_ick);
1739 gpio_fck = clk_get(NULL, "gpios_fck");
1740 if (IS_ERR(gpio_fck))
1741 printk("Could not get gpios_fck\n");
1743 clk_enable(gpio_fck);
1746 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1748 #if defined(CONFIG_ARCH_OMAP2430)
1749 if (cpu_is_omap2430()) {
1750 gpio5_ick = clk_get(NULL, "gpio5_ick");
1751 if (IS_ERR(gpio5_ick))
1752 printk("Could not get gpio5_ick\n");
1754 clk_enable(gpio5_ick);
1755 gpio5_fck = clk_get(NULL, "gpio5_fck");
1756 if (IS_ERR(gpio5_fck))
1757 printk("Could not get gpio5_fck\n");
1759 clk_enable(gpio5_fck);
1765 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1766 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1767 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1768 sprintf(clk_name, "gpio%d_ick", i + 1);
1769 gpio_iclks[i] = clk_get(NULL, clk_name);
1770 if (IS_ERR(gpio_iclks[i]))
1771 printk(KERN_ERR "Could not get %s\n", clk_name);
1773 clk_enable(gpio_iclks[i]);
1779 #ifdef CONFIG_ARCH_OMAP15XX
1780 if (cpu_is_omap15xx()) {
1781 gpio_bank_count = 2;
1782 gpio_bank = gpio_bank_1510;
1786 #if defined(CONFIG_ARCH_OMAP16XX)
1787 if (cpu_is_omap16xx()) {
1788 gpio_bank_count = 5;
1789 gpio_bank = gpio_bank_1610;
1793 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1794 if (cpu_is_omap7xx()) {
1795 gpio_bank_count = 7;
1796 gpio_bank = gpio_bank_7xx;
1800 #ifdef CONFIG_ARCH_OMAP2
1801 if (cpu_is_omap242x()) {
1802 gpio_bank_count = 4;
1803 gpio_bank = gpio_bank_242x;
1805 if (cpu_is_omap243x()) {
1806 gpio_bank_count = 5;
1807 gpio_bank = gpio_bank_243x;
1810 #ifdef CONFIG_ARCH_OMAP3
1811 if (cpu_is_omap34xx()) {
1812 gpio_bank_count = OMAP34XX_NR_GPIOS;
1813 gpio_bank = gpio_bank_34xx;
1816 #ifdef CONFIG_ARCH_OMAP4
1817 if (cpu_is_omap44xx()) {
1818 gpio_bank_count = OMAP34XX_NR_GPIOS;
1819 gpio_bank = gpio_bank_44xx;
1822 for (i = 0; i < gpio_bank_count; i++) {
1823 int j, gpio_count = 16;
1825 bank = &gpio_bank[i];
1826 spin_lock_init(&bank->lock);
1828 /* Static mapping, never released */
1829 bank->base = ioremap(bank->pbase, bank_size);
1831 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1835 if (bank_is_mpuio(bank))
1836 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1837 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1838 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1839 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1841 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1842 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1843 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1844 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1846 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1847 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1848 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1850 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1853 #ifdef CONFIG_ARCH_OMAP2PLUS
1854 if ((bank->method == METHOD_GPIO_24XX) ||
1855 (bank->method == METHOD_GPIO_44XX)) {
1856 static const u32 non_wakeup_gpios[] = {
1857 0xe203ffc0, 0x08700040
1860 if (cpu_is_omap44xx()) {
1861 __raw_writel(0xffffffff, bank->base +
1862 OMAP4_GPIO_IRQSTATUSCLR0);
1863 __raw_writew(0x0015, bank->base +
1864 OMAP4_GPIO_SYSCONFIG);
1865 __raw_writel(0x00000000, bank->base +
1866 OMAP4_GPIO_DEBOUNCENABLE);
1868 * Initialize interface clock ungated,
1871 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1873 __raw_writel(0x00000000, bank->base +
1874 OMAP24XX_GPIO_IRQENABLE1);
1875 __raw_writel(0xffffffff, bank->base +
1876 OMAP24XX_GPIO_IRQSTATUS1);
1877 __raw_writew(0x0015, bank->base +
1878 OMAP24XX_GPIO_SYSCONFIG);
1879 __raw_writel(0x00000000, bank->base +
1880 OMAP24XX_GPIO_DEBOUNCE_EN);
1883 * Initialize interface clock ungated,
1886 __raw_writel(0, bank->base +
1887 OMAP24XX_GPIO_CTRL);
1889 if (cpu_is_omap24xx() &&
1890 i < ARRAY_SIZE(non_wakeup_gpios))
1891 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1896 bank->mod_usage = 0;
1897 /* REVISIT eventually switch from OMAP-specific gpio structs
1898 * over to the generic ones
1900 bank->chip.request = omap_gpio_request;
1901 bank->chip.free = omap_gpio_free;
1902 bank->chip.direction_input = gpio_input;
1903 bank->chip.get = gpio_get;
1904 bank->chip.direction_output = gpio_output;
1905 bank->chip.set_debounce = gpio_debounce;
1906 bank->chip.set = gpio_set;
1907 bank->chip.to_irq = gpio_2irq;
1908 if (bank_is_mpuio(bank)) {
1909 bank->chip.label = "mpuio";
1910 #ifdef CONFIG_ARCH_OMAP16XX
1911 bank->chip.dev = &omap_mpuio_device.dev;
1913 bank->chip.base = OMAP_MPUIO(0);
1915 bank->chip.label = "gpio";
1916 bank->chip.base = gpio;
1919 bank->chip.ngpio = gpio_count;
1921 gpiochip_add(&bank->chip);
1923 for (j = bank->virtual_irq_start;
1924 j < bank->virtual_irq_start + gpio_count; j++) {
1925 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1926 set_irq_chip_data(j, bank);
1927 if (bank_is_mpuio(bank))
1928 set_irq_chip(j, &mpuio_irq_chip);
1930 set_irq_chip(j, &gpio_irq_chip);
1931 set_irq_handler(j, handle_simple_irq);
1932 set_irq_flags(j, IRQF_VALID);
1934 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1935 set_irq_data(bank->irq, bank);
1937 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1938 sprintf(clk_name, "gpio%d_dbck", i + 1);
1939 bank->dbck = clk_get(NULL, clk_name);
1940 if (IS_ERR(bank->dbck))
1941 printk(KERN_ERR "Could not get %s\n", clk_name);
1945 /* Enable system clock for GPIO module.
1946 * The CAM_CLK_CTRL *is* really the right place. */
1947 if (cpu_is_omap16xx())
1948 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1950 /* Enable autoidle for the OCP interface */
1951 if (cpu_is_omap24xx())
1952 omap_writel(1 << 0, 0x48019010);
1953 if (cpu_is_omap34xx())
1954 omap_writel(1 << 0, 0x48306814);
1956 omap_gpio_show_rev();
1961 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1962 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1966 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1969 for (i = 0; i < gpio_bank_count; i++) {
1970 struct gpio_bank *bank = &gpio_bank[i];
1971 void __iomem *wake_status;
1972 void __iomem *wake_clear;
1973 void __iomem *wake_set;
1974 unsigned long flags;
1976 switch (bank->method) {
1977 #ifdef CONFIG_ARCH_OMAP16XX
1978 case METHOD_GPIO_1610:
1979 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1980 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1981 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1984 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1985 case METHOD_GPIO_24XX:
1986 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1987 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1988 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1991 #ifdef CONFIG_ARCH_OMAP4
1992 case METHOD_GPIO_44XX:
1993 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1994 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1995 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2002 spin_lock_irqsave(&bank->lock, flags);
2003 bank->saved_wakeup = __raw_readl(wake_status);
2004 __raw_writel(0xffffffff, wake_clear);
2005 __raw_writel(bank->suspend_wakeup, wake_set);
2006 spin_unlock_irqrestore(&bank->lock, flags);
2012 static int omap_gpio_resume(struct sys_device *dev)
2016 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
2019 for (i = 0; i < gpio_bank_count; i++) {
2020 struct gpio_bank *bank = &gpio_bank[i];
2021 void __iomem *wake_clear;
2022 void __iomem *wake_set;
2023 unsigned long flags;
2025 switch (bank->method) {
2026 #ifdef CONFIG_ARCH_OMAP16XX
2027 case METHOD_GPIO_1610:
2028 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
2029 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
2032 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
2033 case METHOD_GPIO_24XX:
2034 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
2035 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
2038 #ifdef CONFIG_ARCH_OMAP4
2039 case METHOD_GPIO_44XX:
2040 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2041 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2048 spin_lock_irqsave(&bank->lock, flags);
2049 __raw_writel(0xffffffff, wake_clear);
2050 __raw_writel(bank->saved_wakeup, wake_set);
2051 spin_unlock_irqrestore(&bank->lock, flags);
2057 static struct sysdev_class omap_gpio_sysclass = {
2059 .suspend = omap_gpio_suspend,
2060 .resume = omap_gpio_resume,
2063 static struct sys_device omap_gpio_device = {
2065 .cls = &omap_gpio_sysclass,
2070 #ifdef CONFIG_ARCH_OMAP2PLUS
2072 static int workaround_enabled;
2074 void omap2_gpio_prepare_for_idle(int power_state)
2079 if (cpu_is_omap34xx())
2082 for (i = min; i < gpio_bank_count; i++) {
2083 struct gpio_bank *bank = &gpio_bank[i];
2086 if (bank->dbck_enable_mask)
2087 clk_disable(bank->dbck);
2089 if (power_state > PWRDM_POWER_OFF)
2092 /* If going to OFF, remove triggering for all
2093 * non-wakeup GPIOs. Otherwise spurious IRQs will be
2094 * generated. See OMAP2420 Errata item 1.101. */
2095 if (!(bank->enabled_non_wakeup_gpios))
2098 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2099 bank->saved_datain = __raw_readl(bank->base +
2100 OMAP24XX_GPIO_DATAIN);
2101 l1 = __raw_readl(bank->base +
2102 OMAP24XX_GPIO_FALLINGDETECT);
2103 l2 = __raw_readl(bank->base +
2104 OMAP24XX_GPIO_RISINGDETECT);
2107 if (cpu_is_omap44xx()) {
2108 bank->saved_datain = __raw_readl(bank->base +
2110 l1 = __raw_readl(bank->base +
2111 OMAP4_GPIO_FALLINGDETECT);
2112 l2 = __raw_readl(bank->base +
2113 OMAP4_GPIO_RISINGDETECT);
2116 bank->saved_fallingdetect = l1;
2117 bank->saved_risingdetect = l2;
2118 l1 &= ~bank->enabled_non_wakeup_gpios;
2119 l2 &= ~bank->enabled_non_wakeup_gpios;
2121 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2122 __raw_writel(l1, bank->base +
2123 OMAP24XX_GPIO_FALLINGDETECT);
2124 __raw_writel(l2, bank->base +
2125 OMAP24XX_GPIO_RISINGDETECT);
2128 if (cpu_is_omap44xx()) {
2129 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2130 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2136 workaround_enabled = 0;
2139 workaround_enabled = 1;
2142 void omap2_gpio_resume_after_idle(void)
2147 if (cpu_is_omap34xx())
2149 for (i = min; i < gpio_bank_count; i++) {
2150 struct gpio_bank *bank = &gpio_bank[i];
2151 u32 l, gen, gen0, gen1;
2153 if (bank->dbck_enable_mask)
2154 clk_enable(bank->dbck);
2156 if (!workaround_enabled)
2159 if (!(bank->enabled_non_wakeup_gpios))
2162 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2163 __raw_writel(bank->saved_fallingdetect,
2164 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2165 __raw_writel(bank->saved_risingdetect,
2166 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2167 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2170 if (cpu_is_omap44xx()) {
2171 __raw_writel(bank->saved_fallingdetect,
2172 bank->base + OMAP4_GPIO_FALLINGDETECT);
2173 __raw_writel(bank->saved_risingdetect,
2174 bank->base + OMAP4_GPIO_RISINGDETECT);
2175 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2178 /* Check if any of the non-wakeup interrupt GPIOs have changed
2179 * state. If so, generate an IRQ by software. This is
2180 * horribly racy, but it's the best we can do to work around
2181 * this silicon bug. */
2182 l ^= bank->saved_datain;
2183 l &= bank->enabled_non_wakeup_gpios;
2186 * No need to generate IRQs for the rising edge for gpio IRQs
2187 * configured with falling edge only; and vice versa.
2189 gen0 = l & bank->saved_fallingdetect;
2190 gen0 &= bank->saved_datain;
2192 gen1 = l & bank->saved_risingdetect;
2193 gen1 &= ~(bank->saved_datain);
2195 /* FIXME: Consider GPIO IRQs with level detections properly! */
2196 gen = l & (~(bank->saved_fallingdetect) &
2197 ~(bank->saved_risingdetect));
2198 /* Consider all GPIO IRQs needed to be updated */
2204 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2205 old0 = __raw_readl(bank->base +
2206 OMAP24XX_GPIO_LEVELDETECT0);
2207 old1 = __raw_readl(bank->base +
2208 OMAP24XX_GPIO_LEVELDETECT1);
2209 __raw_writel(old0 | gen, bank->base +
2210 OMAP24XX_GPIO_LEVELDETECT0);
2211 __raw_writel(old1 | gen, bank->base +
2212 OMAP24XX_GPIO_LEVELDETECT1);
2213 __raw_writel(old0, bank->base +
2214 OMAP24XX_GPIO_LEVELDETECT0);
2215 __raw_writel(old1, bank->base +
2216 OMAP24XX_GPIO_LEVELDETECT1);
2219 if (cpu_is_omap44xx()) {
2220 old0 = __raw_readl(bank->base +
2221 OMAP4_GPIO_LEVELDETECT0);
2222 old1 = __raw_readl(bank->base +
2223 OMAP4_GPIO_LEVELDETECT1);
2224 __raw_writel(old0 | l, bank->base +
2225 OMAP4_GPIO_LEVELDETECT0);
2226 __raw_writel(old1 | l, bank->base +
2227 OMAP4_GPIO_LEVELDETECT1);
2228 __raw_writel(old0, bank->base +
2229 OMAP4_GPIO_LEVELDETECT0);
2230 __raw_writel(old1, bank->base +
2231 OMAP4_GPIO_LEVELDETECT1);
2240 #ifdef CONFIG_ARCH_OMAP3
2241 /* save the registers of bank 2-6 */
2242 void omap_gpio_save_context(void)
2246 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2247 for (i = 1; i < gpio_bank_count; i++) {
2248 struct gpio_bank *bank = &gpio_bank[i];
2249 gpio_context[i].sysconfig =
2250 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2251 gpio_context[i].irqenable1 =
2252 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2253 gpio_context[i].irqenable2 =
2254 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2255 gpio_context[i].wake_en =
2256 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2257 gpio_context[i].ctrl =
2258 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2259 gpio_context[i].oe =
2260 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2261 gpio_context[i].leveldetect0 =
2262 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2263 gpio_context[i].leveldetect1 =
2264 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2265 gpio_context[i].risingdetect =
2266 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2267 gpio_context[i].fallingdetect =
2268 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2269 gpio_context[i].dataout =
2270 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2274 /* restore the required registers of bank 2-6 */
2275 void omap_gpio_restore_context(void)
2279 for (i = 1; i < gpio_bank_count; i++) {
2280 struct gpio_bank *bank = &gpio_bank[i];
2281 __raw_writel(gpio_context[i].sysconfig,
2282 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2283 __raw_writel(gpio_context[i].irqenable1,
2284 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2285 __raw_writel(gpio_context[i].irqenable2,
2286 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2287 __raw_writel(gpio_context[i].wake_en,
2288 bank->base + OMAP24XX_GPIO_WAKE_EN);
2289 __raw_writel(gpio_context[i].ctrl,
2290 bank->base + OMAP24XX_GPIO_CTRL);
2291 __raw_writel(gpio_context[i].oe,
2292 bank->base + OMAP24XX_GPIO_OE);
2293 __raw_writel(gpio_context[i].leveldetect0,
2294 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2295 __raw_writel(gpio_context[i].leveldetect1,
2296 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2297 __raw_writel(gpio_context[i].risingdetect,
2298 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2299 __raw_writel(gpio_context[i].fallingdetect,
2300 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2301 __raw_writel(gpio_context[i].dataout,
2302 bank->base + OMAP24XX_GPIO_DATAOUT);
2308 * This may get called early from board specific init
2309 * for boards that have interrupts routed via FPGA.
2311 int __init omap_gpio_init(void)
2314 return _omap_gpio_init();
2319 static int __init omap_gpio_sysinit(void)
2324 ret = _omap_gpio_init();
2328 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2329 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2331 ret = sysdev_class_register(&omap_gpio_sysclass);
2333 ret = sysdev_register(&omap_gpio_device);
2341 arch_initcall(omap_gpio_sysinit);