2 * sh7377 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/uio_driver.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_intc.h>
31 #include <linux/sh_timer.h>
32 #include <mach/hardware.h>
33 #include <asm/mach-types.h>
34 #include <asm/mach/arch.h>
37 static struct plat_sci_port scif0_platform_data = {
38 .mapbase = 0xe6c40000,
39 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE,
41 .scbrr_algo_id = SCBRR_ALGO_4,
43 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
44 evt2irq(0xc00), evt2irq(0xc00) },
47 static struct platform_device scif0_device = {
51 .platform_data = &scif0_platform_data,
56 static struct plat_sci_port scif1_platform_data = {
57 .mapbase = 0xe6c50000,
58 .flags = UPF_BOOT_AUTOCONF,
59 .scscr = SCSCR_RE | SCSCR_TE,
60 .scbrr_algo_id = SCBRR_ALGO_4,
62 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
63 evt2irq(0xc20), evt2irq(0xc20) },
66 static struct platform_device scif1_device = {
70 .platform_data = &scif1_platform_data,
75 static struct plat_sci_port scif2_platform_data = {
76 .mapbase = 0xe6c60000,
77 .flags = UPF_BOOT_AUTOCONF,
78 .scscr = SCSCR_RE | SCSCR_TE,
79 .scbrr_algo_id = SCBRR_ALGO_4,
81 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
82 evt2irq(0xc40), evt2irq(0xc40) },
85 static struct platform_device scif2_device = {
89 .platform_data = &scif2_platform_data,
94 static struct plat_sci_port scif3_platform_data = {
95 .mapbase = 0xe6c70000,
96 .flags = UPF_BOOT_AUTOCONF,
97 .scscr = SCSCR_RE | SCSCR_TE,
98 .scbrr_algo_id = SCBRR_ALGO_4,
100 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
101 evt2irq(0xc60), evt2irq(0xc60) },
104 static struct platform_device scif3_device = {
108 .platform_data = &scif3_platform_data,
113 static struct plat_sci_port scif4_platform_data = {
114 .mapbase = 0xe6c80000,
115 .flags = UPF_BOOT_AUTOCONF,
116 .scscr = SCSCR_RE | SCSCR_TE,
117 .scbrr_algo_id = SCBRR_ALGO_4,
119 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
120 evt2irq(0xd20), evt2irq(0xd20) },
123 static struct platform_device scif4_device = {
127 .platform_data = &scif4_platform_data,
132 static struct plat_sci_port scif5_platform_data = {
133 .mapbase = 0xe6cb0000,
134 .flags = UPF_BOOT_AUTOCONF,
135 .scscr = SCSCR_RE | SCSCR_TE,
136 .scbrr_algo_id = SCBRR_ALGO_4,
138 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
139 evt2irq(0xd40), evt2irq(0xd40) },
142 static struct platform_device scif5_device = {
146 .platform_data = &scif5_platform_data,
151 static struct plat_sci_port scif6_platform_data = {
152 .mapbase = 0xe6cc0000,
153 .flags = UPF_BOOT_AUTOCONF,
154 .scscr = SCSCR_RE | SCSCR_TE,
155 .scbrr_algo_id = SCBRR_ALGO_4,
157 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
158 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
161 static struct platform_device scif6_device = {
165 .platform_data = &scif6_platform_data,
170 static struct plat_sci_port scif7_platform_data = {
171 .mapbase = 0xe6c30000,
172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE,
174 .scbrr_algo_id = SCBRR_ALGO_4,
176 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
177 evt2irq(0xd60), evt2irq(0xd60) },
180 static struct platform_device scif7_device = {
184 .platform_data = &scif7_platform_data,
188 static struct sh_timer_config cmt10_platform_data = {
190 .channel_offset = 0x10,
192 .clockevent_rating = 125,
193 .clocksource_rating = 125,
196 static struct resource cmt10_resources[] = {
201 .flags = IORESOURCE_MEM,
204 .start = evt2irq(0xb00), /* CMT1_CMT10 */
205 .flags = IORESOURCE_IRQ,
209 static struct platform_device cmt10_device = {
213 .platform_data = &cmt10_platform_data,
215 .resource = cmt10_resources,
216 .num_resources = ARRAY_SIZE(cmt10_resources),
220 static struct uio_info vpu_platform_data = {
223 .irq = intcs_evt2irq(0x980),
226 static struct resource vpu_resources[] = {
231 .flags = IORESOURCE_MEM,
235 static struct platform_device vpu_device = {
236 .name = "uio_pdrv_genirq",
239 .platform_data = &vpu_platform_data,
241 .resource = vpu_resources,
242 .num_resources = ARRAY_SIZE(vpu_resources),
246 static struct uio_info veu0_platform_data = {
249 .irq = intcs_evt2irq(0x700),
252 static struct resource veu0_resources[] = {
257 .flags = IORESOURCE_MEM,
261 static struct platform_device veu0_device = {
262 .name = "uio_pdrv_genirq",
265 .platform_data = &veu0_platform_data,
267 .resource = veu0_resources,
268 .num_resources = ARRAY_SIZE(veu0_resources),
272 static struct uio_info veu1_platform_data = {
275 .irq = intcs_evt2irq(0x720),
278 static struct resource veu1_resources[] = {
283 .flags = IORESOURCE_MEM,
287 static struct platform_device veu1_device = {
288 .name = "uio_pdrv_genirq",
291 .platform_data = &veu1_platform_data,
293 .resource = veu1_resources,
294 .num_resources = ARRAY_SIZE(veu1_resources),
298 static struct uio_info veu2_platform_data = {
301 .irq = intcs_evt2irq(0x740),
304 static struct resource veu2_resources[] = {
309 .flags = IORESOURCE_MEM,
313 static struct platform_device veu2_device = {
314 .name = "uio_pdrv_genirq",
317 .platform_data = &veu2_platform_data,
319 .resource = veu2_resources,
320 .num_resources = ARRAY_SIZE(veu2_resources),
324 static struct uio_info veu3_platform_data = {
327 .irq = intcs_evt2irq(0x760),
330 static struct resource veu3_resources[] = {
335 .flags = IORESOURCE_MEM,
339 static struct platform_device veu3_device = {
340 .name = "uio_pdrv_genirq",
343 .platform_data = &veu3_platform_data,
345 .resource = veu3_resources,
346 .num_resources = ARRAY_SIZE(veu3_resources),
350 static struct uio_info jpu_platform_data = {
353 .irq = intcs_evt2irq(0x560),
356 static struct resource jpu_resources[] = {
361 .flags = IORESOURCE_MEM,
365 static struct platform_device jpu_device = {
366 .name = "uio_pdrv_genirq",
369 .platform_data = &jpu_platform_data,
371 .resource = jpu_resources,
372 .num_resources = ARRAY_SIZE(jpu_resources),
376 static struct uio_info spu0_platform_data = {
379 .irq = evt2irq(0x1800),
382 static struct resource spu0_resources[] = {
387 .flags = IORESOURCE_MEM,
391 static struct platform_device spu0_device = {
392 .name = "uio_pdrv_genirq",
395 .platform_data = &spu0_platform_data,
397 .resource = spu0_resources,
398 .num_resources = ARRAY_SIZE(spu0_resources),
402 static struct uio_info spu1_platform_data = {
405 .irq = evt2irq(0x1820),
408 static struct resource spu1_resources[] = {
413 .flags = IORESOURCE_MEM,
417 static struct platform_device spu1_device = {
418 .name = "uio_pdrv_genirq",
421 .platform_data = &spu1_platform_data,
423 .resource = spu1_resources,
424 .num_resources = ARRAY_SIZE(spu1_resources),
427 static struct platform_device *sh7377_early_devices[] __initdata = {
439 static struct platform_device *sh7377_devices[] __initdata = {
450 void __init sh7377_add_standard_devices(void)
452 platform_add_devices(sh7377_early_devices,
453 ARRAY_SIZE(sh7377_early_devices));
455 platform_add_devices(sh7377_devices,
456 ARRAY_SIZE(sh7377_devices));
459 #define SMSTPCR3 0xe615013c
460 #define SMSTPCR3_CMT1 (1 << 29)
462 void __init sh7377_add_early_devices(void)
464 /* enable clock to CMT1 */
465 __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
467 early_platform_add_devices(sh7377_early_devices,
468 ARRAY_SIZE(sh7377_early_devices));