1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
3 * Copyright (c) 2005-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <linux/gpio.h>
19 #include <linux/device.h>
20 #include <linux/sysdev.h>
21 #include <linux/serial_core.h>
22 #include <linux/clk.h>
23 #include <linux/i2c.h>
26 #include <linux/i2c/tps65010.h>
28 #include <asm/mach/arch.h>
29 #include <asm/mach/map.h>
30 #include <asm/mach/irq.h>
32 #include <mach/osiris-map.h>
33 #include <mach/osiris-cpld.h>
35 #include <mach/hardware.h>
37 #include <asm/mach-types.h>
39 #include <plat/cpu-freq.h>
40 #include <plat/regs-serial.h>
41 #include <mach/regs-gpio.h>
42 #include <mach/regs-mem.h>
43 #include <mach/regs-lcd.h>
44 #include <plat/nand.h>
47 #include <linux/mtd/mtd.h>
48 #include <linux/mtd/nand.h>
49 #include <linux/mtd/nand_ecc.h>
50 #include <linux/mtd/partitions.h>
52 #include <plat/clock.h>
53 #include <plat/devs.h>
56 /* onboard perihperal map */
58 static struct map_desc osiris_iodesc[] __initdata = {
59 /* ISA IO areas (may be over-written later) */
62 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
63 .pfn = __phys_to_pfn(S3C2410_CS5),
67 .virtual = (u32)S3C24XX_VA_ISA_WORD,
68 .pfn = __phys_to_pfn(S3C2410_CS5),
73 /* CPLD control registers */
76 .virtual = (u32)OSIRIS_VA_CTRL0,
77 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
81 .virtual = (u32)OSIRIS_VA_CTRL1,
82 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
86 .virtual = (u32)OSIRIS_VA_CTRL2,
87 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
91 .virtual = (u32)OSIRIS_VA_IDREG,
92 .pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
98 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
99 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
100 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
102 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
117 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
124 .clocks = osiris_serial_clocks,
125 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
133 .clocks = osiris_serial_clocks,
134 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
142 .clocks = osiris_serial_clocks,
143 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
147 /* NAND Flash on Osiris board */
149 static int external_map[] = { 2 };
150 static int chip0_map[] = { 0 };
151 static int chip1_map[] = { 1 };
153 static struct mtd_partition __initdata osiris_default_nand_part[] = {
155 .name = "Boot Agent",
161 .size = SZ_4M - SZ_16K,
167 .size = SZ_32M - SZ_4M,
172 .size = MTDPART_SIZ_FULL,
176 static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
178 .name = "Boot Agent",
184 .size = SZ_4M - SZ_128K,
190 .size = SZ_32M - SZ_4M,
195 .size = MTDPART_SIZ_FULL,
199 /* the Osiris has 3 selectable slots for nand-flash, the two
200 * on-board chip areas, as well as the external slot.
202 * Note, there is no current hot-plug support for the External
206 static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
210 .nr_map = external_map,
211 .options = NAND_SCAN_SILENT_NODEV,
212 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
213 .partitions = osiris_default_nand_part,
219 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
220 .partitions = osiris_default_nand_part,
226 .options = NAND_SCAN_SILENT_NODEV,
227 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
228 .partitions = osiris_default_nand_part,
232 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
236 slot = set->nr_map[slot] & 3;
238 pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
239 slot, set, set->nr_map);
241 tmp = __raw_readb(OSIRIS_VA_CTRL0);
242 tmp &= ~OSIRIS_CTRL0_NANDSEL;
245 pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
247 __raw_writeb(tmp, OSIRIS_VA_CTRL0);
250 static struct s3c2410_platform_nand __initdata osiris_nand_info = {
254 .nr_sets = ARRAY_SIZE(osiris_nand_sets),
255 .sets = osiris_nand_sets,
256 .select_chip = osiris_nand_select,
259 /* PCMCIA control and configuration */
261 static struct resource osiris_pcmcia_resource[] = {
265 .flags = IORESOURCE_MEM,
270 .flags = IORESOURCE_MEM,
274 static struct platform_device osiris_pcmcia = {
275 .name = "osiris-pcmcia",
277 .num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
278 .resource = osiris_pcmcia_resource,
281 /* Osiris power management device */
284 static unsigned char pm_osiris_ctrl0;
286 static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
290 pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
291 tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
293 /* ensure correct NAND slot is selected on resume */
294 if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
297 __raw_writeb(tmp, OSIRIS_VA_CTRL0);
299 /* ensure that an nRESET is not generated on resume. */
300 s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
301 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
306 static int osiris_pm_resume(struct sys_device *sd)
308 if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
309 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
311 __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
313 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
319 #define osiris_pm_suspend NULL
320 #define osiris_pm_resume NULL
323 static struct sysdev_class osiris_pm_sysclass = {
324 .name = "mach-osiris",
325 .suspend = osiris_pm_suspend,
326 .resume = osiris_pm_resume,
329 static struct sys_device osiris_pm_sysdev = {
330 .cls = &osiris_pm_sysclass,
333 /* Link for DVS driver to TPS65011 */
335 static void osiris_tps_release(struct device *dev)
337 /* static device, do not need to release anything */
340 static struct platform_device osiris_tps_device = {
341 .name = "osiris-dvs",
343 .dev.release = osiris_tps_release,
346 static int osiris_tps_setup(struct i2c_client *client, void *context)
348 osiris_tps_device.dev.parent = &client->dev;
349 return platform_device_register(&osiris_tps_device);
352 static int osiris_tps_remove(struct i2c_client *client, void *context)
354 platform_device_unregister(&osiris_tps_device);
358 static struct tps65010_board osiris_tps_board = {
359 .base = -1, /* GPIO can go anywhere at the moment */
360 .setup = osiris_tps_setup,
361 .teardown = osiris_tps_remove,
364 /* I2C devices fitted. */
366 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
368 I2C_BOARD_INFO("tps65011", 0x48),
370 .platform_data = &osiris_tps_board,
374 /* Standard Osiris devices */
376 static struct platform_device *osiris_devices[] __initdata = {
383 static struct clk *osiris_clocks[] __initdata = {
391 static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
392 .refresh = 7800, /* refresh period is 7.8usec */
397 static void __init osiris_map_io(void)
401 /* initialise the clocks */
403 s3c24xx_dclk0.parent = &clk_upll;
404 s3c24xx_dclk0.rate = 12*1000*1000;
406 s3c24xx_dclk1.parent = &clk_upll;
407 s3c24xx_dclk1.rate = 24*1000*1000;
409 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
410 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
412 s3c24xx_uclk.parent = &s3c24xx_clkout1;
414 s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
416 s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
417 s3c24xx_init_clocks(0);
418 s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
420 /* check for the newer revision boards with large page nand */
422 if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
423 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
424 __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
425 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
426 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
428 /* write-protect line to the NAND */
429 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
432 /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
434 local_irq_save(flags);
435 __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
436 local_irq_restore(flags);
439 static void __init osiris_init(void)
441 sysdev_class_register(&osiris_pm_sysclass);
442 sysdev_register(&osiris_pm_sysdev);
444 s3c_i2c0_set_platdata(NULL);
445 s3c_nand_set_platdata(&osiris_nand_info);
447 s3c_cpufreq_setboard(&osiris_cpufreq);
449 i2c_register_board_info(0, osiris_i2c_devs,
450 ARRAY_SIZE(osiris_i2c_devs));
452 platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
455 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
456 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
457 .phys_io = S3C2410_PA_UART,
458 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
459 .boot_params = S3C2410_SDRAM_PA + 0x100,
460 .map_io = osiris_map_io,
461 .init_irq = s3c24xx_init_irq,
462 .init_machine = osiris_init,
463 .timer = &s3c24xx_timer,