2 * OMAP2 Power Management Routines
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk.h>
30 #include <linux/irq.h>
31 #include <linux/time.h>
32 #include <linux/gpio.h>
33 #include <linux/console.h>
35 #include <asm/mach/time.h>
36 #include <asm/mach/irq.h>
37 #include <asm/mach-types.h>
39 #include <mach/irqs.h>
40 #include <plat/clock.h>
41 #include <plat/sram.h>
43 #include <plat/board.h>
45 #include "prm2xxx_3xxx.h"
46 #include "prm-regbits-24xx.h"
47 #include "cm2xxx_3xxx.h"
48 #include "cm-regbits-24xx.h"
53 #include "powerdomain.h"
54 #include "clockdomain.h"
56 static int omap2_pm_debug;
59 static suspend_state_t suspend_state = PM_SUSPEND_ON;
60 static inline bool is_suspending(void)
62 return (suspend_state != PM_SUSPEND_ON);
65 static inline bool is_suspending(void)
71 static void (*omap2_sram_idle)(void);
72 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
73 void __iomem *sdrc_power);
75 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
76 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
78 static struct clk *osc_ck, *emul_ck;
80 static int omap2_fclks_active(void)
84 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
85 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
87 /* Ignore UART clocks. These are handled by UART core (serial.c) */
88 f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
89 f2 &= ~OMAP24XX_EN_UART3_MASK;
96 static void omap2_enter_full_retention(void)
99 struct timespec ts_preidle, ts_postidle, ts_idle;
101 /* There is 1 reference hold for all children of the oscillator
102 * clock, the following will remove it. If no one else uses the
103 * oscillator itself it will be disabled if/when we enter retention
108 /* Clear old wake-up events */
109 /* REVISIT: These write to reserved bits? */
110 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
111 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
112 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
115 * Set MPU powerdomain's next power state to RETENTION;
116 * preserve logic state during retention
118 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
119 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
121 /* Workaround to kill USB */
122 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
123 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
125 omap2_gpio_prepare_for_idle(0);
127 if (omap2_pm_debug) {
128 getnstimeofday(&ts_preidle);
131 /* One last check for pending IRQs to avoid extra latency due
132 * to sleeping unnecessarily. */
133 if (omap_irq_pending())
136 /* Block console output in case it is on one of the OMAP UARTs */
137 if (!is_suspending())
138 if (!console_trylock())
141 omap_uart_prepare_idle(0);
142 omap_uart_prepare_idle(1);
143 omap_uart_prepare_idle(2);
145 /* Jump to SRAM suspend code */
146 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
147 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
148 OMAP_SDRC_REGADDR(SDRC_POWER));
150 omap_uart_resume_idle(2);
151 omap_uart_resume_idle(1);
152 omap_uart_resume_idle(0);
154 if (!is_suspending())
158 if (omap2_pm_debug) {
159 unsigned long long tmp;
161 getnstimeofday(&ts_postidle);
162 ts_idle = timespec_sub(ts_postidle, ts_preidle);
163 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
165 omap2_gpio_resume_after_idle();
169 /* clear CORE wake-up events */
170 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
171 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
173 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
174 omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
176 /* MPU domain wake events */
177 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
179 omap2_prm_write_mod_reg(0x01, OCP_MOD,
180 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
182 omap2_prm_write_mod_reg(0x20, OCP_MOD,
183 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
185 /* Mask future PRCM-to-MPU interrupts */
186 omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
189 static int omap2_i2c_active(void)
193 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
194 return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
197 static int sti_console_enabled;
199 static int omap2_allow_mpu_retention(void)
203 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
204 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
205 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
206 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
207 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
209 /* Check for UART3. */
210 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
211 if (l & OMAP24XX_EN_UART3_MASK)
213 if (sti_console_enabled)
219 static void omap2_enter_mpu_retention(void)
222 struct timespec ts_preidle, ts_postidle, ts_idle;
224 /* Putting MPU into the WFI state while a transfer is active
225 * seems to cause the I2C block to timeout. Why? Good question. */
226 if (omap2_i2c_active())
229 /* The peripherals seem not to be able to wake up the MPU when
230 * it is in retention mode. */
231 if (omap2_allow_mpu_retention()) {
232 /* REVISIT: These write to reserved bits? */
233 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
234 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
235 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
237 /* Try to enter MPU retention */
238 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
239 OMAP_LOGICRETSTATE_MASK,
240 MPU_MOD, OMAP2_PM_PWSTCTRL);
242 /* Block MPU retention */
244 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
249 if (omap2_pm_debug) {
250 getnstimeofday(&ts_preidle);
255 if (omap2_pm_debug) {
256 unsigned long long tmp;
258 getnstimeofday(&ts_postidle);
259 ts_idle = timespec_sub(ts_postidle, ts_preidle);
260 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
264 static int omap2_can_sleep(void)
266 if (omap2_fclks_active())
268 if (!omap_uart_can_sleep())
270 if (osc_ck->usecount > 1)
272 if (omap_dma_running())
278 static void omap2_pm_idle(void)
283 if (!omap2_can_sleep()) {
284 if (omap_irq_pending())
286 omap2_enter_mpu_retention();
290 if (omap_irq_pending())
293 omap2_enter_full_retention();
300 #ifdef CONFIG_SUSPEND
301 static int omap2_pm_begin(suspend_state_t state)
304 suspend_state = state;
308 static int omap2_pm_suspend(void)
312 wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
313 wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
314 omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
317 mir1 = omap_readl(0x480fe0a4);
318 omap_writel(1 << 5, 0x480fe0ac);
320 omap_uart_prepare_suspend();
321 omap2_enter_full_retention();
323 omap_writel(mir1, 0x480fe0a4);
324 omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
329 static int omap2_pm_enter(suspend_state_t state)
334 case PM_SUSPEND_STANDBY:
336 ret = omap2_pm_suspend();
345 static void omap2_pm_end(void)
347 suspend_state = PM_SUSPEND_ON;
351 static const struct platform_suspend_ops omap_pm_ops = {
352 .begin = omap2_pm_begin,
353 .enter = omap2_pm_enter,
355 .valid = suspend_valid_only_mem,
358 static const struct platform_suspend_ops __initdata omap_pm_ops;
359 #endif /* CONFIG_SUSPEND */
361 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
362 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
364 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
365 clkdm_allow_idle(clkdm);
366 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
367 atomic_read(&clkdm->usecount) == 0)
372 static void __init prcm_setup_regs(void)
374 int i, num_mem_banks;
375 struct powerdomain *pwrdm;
379 * XXX This should be handled by hwmod code or PRCM init code
381 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
382 OMAP2_PRCM_SYSCONFIG_OFFSET);
385 * Set CORE powerdomain memory banks to retain their contents
388 num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
389 for (i = 0; i < num_mem_banks; i++)
390 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
392 /* Set CORE powerdomain's next power state to RETENTION */
393 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
396 * Set MPU powerdomain's next power state to RETENTION;
397 * preserve logic state during retention
399 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
400 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
402 /* Force-power down DSP, GFX powerdomains */
404 pwrdm = clkdm_get_pwrdm(dsp_clkdm);
405 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
406 clkdm_sleep(dsp_clkdm);
408 pwrdm = clkdm_get_pwrdm(gfx_clkdm);
409 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
410 clkdm_sleep(gfx_clkdm);
412 /* Enable hardware-supervised idle for all clkdms */
413 clkdm_for_each(clkdms_setup, NULL);
414 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
416 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
418 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
419 OMAP2_PRCM_CLKSSETUP_OFFSET);
421 /* Configure automatic voltage transition */
422 omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
423 OMAP2_PRCM_VOLTSETUP_OFFSET);
424 omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
425 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
426 OMAP24XX_MEMRETCTRL_MASK |
427 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
428 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
429 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
431 /* Enable wake-up events */
432 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
436 static int __init omap2_pm_init(void)
440 if (!cpu_is_omap24xx())
443 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
444 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
445 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
447 /* Look up important powerdomains */
449 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
451 pr_err("PM: mpu_pwrdm not found\n");
453 core_pwrdm = pwrdm_lookup("core_pwrdm");
455 pr_err("PM: core_pwrdm not found\n");
457 /* Look up important clockdomains */
459 mpu_clkdm = clkdm_lookup("mpu_clkdm");
461 pr_err("PM: mpu_clkdm not found\n");
463 wkup_clkdm = clkdm_lookup("wkup_clkdm");
465 pr_err("PM: wkup_clkdm not found\n");
467 dsp_clkdm = clkdm_lookup("dsp_clkdm");
469 pr_err("PM: dsp_clkdm not found\n");
471 gfx_clkdm = clkdm_lookup("gfx_clkdm");
473 pr_err("PM: gfx_clkdm not found\n");
476 osc_ck = clk_get(NULL, "osc_ck");
477 if (IS_ERR(osc_ck)) {
478 printk(KERN_ERR "could not get osc_ck\n");
482 if (cpu_is_omap242x()) {
483 emul_ck = clk_get(NULL, "emul_ck");
484 if (IS_ERR(emul_ck)) {
485 printk(KERN_ERR "could not get emul_ck\n");
493 /* Hack to prevent MPU retention when STI console is enabled. */
495 const struct omap_sti_console_config *sti;
497 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
498 struct omap_sti_console_config);
499 if (sti != NULL && sti->enable)
500 sti_console_enabled = 1;
504 * We copy the assembler sleep/wakeup routines to SRAM.
505 * These routines need to be in SRAM as that's the only
506 * memory the MPU can see when it wakes up.
508 if (cpu_is_omap24xx()) {
509 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
510 omap24xx_idle_loop_suspend_sz);
512 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
513 omap24xx_cpu_suspend_sz);
516 suspend_set_ops(&omap_pm_ops);
517 pm_idle = omap2_pm_idle;
522 late_initcall(omap2_pm_init);