2 * This file configures the internal USB PHY in OMAP4430. Used
3 * with TWL6030 transceiver and MUSB on OMAP4430.
5 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * Author: Hema HK <hemahk@ti.com>
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/types.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
28 #include <linux/err.h>
29 #include <linux/usb.h>
34 /* OMAP control module register for UTMI PHY */
35 #define CONTROL_DEV_CONF 0x300
38 #define USBOTGHS_CONTROL 0x33c
41 #define VBUSVALID BIT(2)
42 #define SESSEND BIT(3)
45 static struct clk *phyclk, *clk48m, *clk32k;
46 static void __iomem *ctrl_base;
47 static int usbotghs_control;
49 int omap4430_phy_init(struct device *dev)
51 ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
53 dev_err(dev, "control module ioremap failed\n");
56 /* Power down the phy */
57 __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
58 phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
61 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
63 return PTR_ERR(phyclk);
66 clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
68 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
71 return PTR_ERR(clk48m);
74 clk32k = clk_get(dev, "usb_phy_cm_clk32k");
76 dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
80 return PTR_ERR(clk32k);
85 int omap4430_phy_set_clk(struct device *dev, int on)
90 /* Enable the phy clocks */
96 /* Disable the phy clocks */
105 int omap4430_phy_power(struct device *dev, int ID, int on)
109 /* enable VBUS valid, IDDIG groung */
110 __raw_writel(AVALID | VBUSVALID, ctrl_base +
114 * Enable VBUS Valid, AValid and IDDIG
117 __raw_writel(IDDIG | AVALID | VBUSVALID,
118 ctrl_base + USBOTGHS_CONTROL);
120 /* Enable session END and IDIG to high impedance. */
121 __raw_writel(SESSEND | IDDIG, ctrl_base +
127 int omap4430_phy_suspend(struct device *dev, int suspend)
130 /* Disable the clocks */
131 omap4430_phy_set_clk(dev, 0);
132 /* Power down the phy */
133 __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
135 /* save the context */
136 usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
138 /* Enable the internel phy clcoks */
139 omap4430_phy_set_clk(dev, 1);
140 /* power on the phy */
141 if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
142 __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
146 /* restore the context */
147 __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
153 int omap4430_phy_exit(struct device *dev)
167 void am35x_musb_reset(void)
171 /* Reset the musb interface */
172 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
174 regval |= AM35XX_USBOTGSS_SW_RST;
175 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
177 regval &= ~AM35XX_USBOTGSS_SW_RST;
178 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
180 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
183 void am35x_musb_phy_power(u8 on)
185 unsigned long timeout = jiffies + msecs_to_jiffies(100);
190 * Start the on-chip PHY and its PLL.
192 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
194 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
195 devconf2 |= CONF2_PHY_PLLON;
197 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
199 pr_info(KERN_INFO "Waiting for PHY clock good...\n");
200 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
204 if (time_after(jiffies, timeout)) {
205 pr_err(KERN_ERR "musb PHY clock good timed out\n");
211 * Power down the on-chip PHY.
213 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
215 devconf2 &= ~CONF2_PHY_PLLON;
216 devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
217 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
221 void am35x_musb_clear_irq(void)
225 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
226 regval |= AM35XX_USBOTGSS_INT_CLR;
227 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
228 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
231 void am35x_musb_set_mode(u8 musb_mode)
233 u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
235 devconf2 &= ~CONF2_OTGMODE;
237 #ifdef CONFIG_USB_MUSB_HDRC_HCD
238 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
239 devconf2 |= CONF2_FORCE_HOST;
242 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
243 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
244 devconf2 |= CONF2_FORCE_DEVICE;
247 #ifdef CONFIG_USB_MUSB_OTG
248 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
249 devconf2 |= CONF2_NO_OVERRIDE;
253 pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
256 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);