2 * linux/arch/arm/mach-omap2/irq.c
4 * Interrupt handler for OMAP2 boards.
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
17 #include <mach/hardware.h>
18 #include <asm/mach/irq.h>
21 /* selected INTC register offsets */
23 #define INTC_REVISION 0x0000
24 #define INTC_SYSCONFIG 0x0010
25 #define INTC_SYSSTATUS 0x0014
26 #define INTC_SIR 0x0040
27 #define INTC_CONTROL 0x0048
28 #define INTC_PROTECTION 0x004C
29 #define INTC_IDLE 0x0050
30 #define INTC_THRESHOLD 0x0068
31 #define INTC_MIR0 0x0084
32 #define INTC_MIR_CLEAR0 0x0088
33 #define INTC_MIR_SET0 0x008c
34 #define INTC_PENDING_IRQ0 0x0098
35 /* Number of IRQ state bits in each MIR register */
36 #define IRQ_BITS_PER_REG 32
39 * OMAP2 has a number of different interrupt controllers, each interrupt
40 * controller is identified as its own "bank". Register definitions are
41 * fairly consistent for each bank, but not all registers are implemented
42 * for each bank.. when in doubt, consult the TRM.
44 static struct omap_irq_bank {
45 void __iomem *base_reg;
47 } __attribute__ ((aligned(4))) irq_banks[] = {
54 /* Structure to save interrupt controller context */
55 struct omap3_intc_regs {
60 u32 ilr[INTCPS_NR_IRQS];
61 u32 mir[INTCPS_NR_MIR_REGS];
64 /* INTC bank register get/set */
66 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
68 __raw_writel(val, bank->base_reg + reg);
71 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
73 return __raw_readl(bank->base_reg + reg);
76 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
77 static void omap_ack_irq(struct irq_data *d)
79 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
82 static void omap_mask_ack_irq(struct irq_data *d)
84 irq_gc_mask_disable_reg(d);
88 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
92 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
93 printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
94 "(revision %ld.%ld) with %d interrupts\n",
95 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
97 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
98 tmp |= 1 << 1; /* soft reset */
99 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
101 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
102 /* Wait for reset to complete */;
104 /* Enable autoidle */
105 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
108 int omap_irq_pending(void)
112 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
113 struct omap_irq_bank *bank = irq_banks + i;
116 for (irq = 0; irq < bank->nr_irqs; irq += 32)
117 if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
125 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
127 struct irq_chip_generic *gc;
128 struct irq_chip_type *ct;
130 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
133 ct->chip.irq_ack = omap_mask_ack_irq;
134 ct->chip.irq_mask = irq_gc_mask_disable_reg;
135 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
136 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
138 ct->regs.ack = INTC_CONTROL;
139 ct->regs.enable = INTC_MIR_CLEAR0;
140 ct->regs.disable = INTC_MIR_SET0;
141 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
142 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
145 static void __init omap_init_irq(u32 base, int nr_irqs)
147 unsigned long nr_of_irqs = 0;
148 unsigned int nr_banks = 0;
151 omap_irq_base = ioremap(base, SZ_4K);
152 if (WARN_ON(!omap_irq_base))
155 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
156 struct omap_irq_bank *bank = irq_banks + i;
158 bank->nr_irqs = nr_irqs;
160 /* Static mapping, never released */
161 bank->base_reg = ioremap(base, SZ_4K);
162 if (!bank->base_reg) {
163 printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
167 omap_irq_bank_init_one(bank);
169 for (j = 0; j < bank->nr_irqs; j += 32)
170 omap_alloc_gc(bank->base_reg + j, j, 32);
172 nr_of_irqs += bank->nr_irqs;
176 printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
177 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
180 void __init omap2_init_irq(void)
182 omap_init_irq(OMAP24XX_IC_BASE, 96);
185 void __init omap3_init_irq(void)
187 omap_init_irq(OMAP34XX_IC_BASE, 96);
190 void __init ti816x_init_irq(void)
192 omap_init_irq(OMAP34XX_IC_BASE, 128);
195 #ifdef CONFIG_ARCH_OMAP3
196 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
198 void omap_intc_save_context(void)
201 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
202 struct omap_irq_bank *bank = irq_banks + ind;
203 intc_context[ind].sysconfig =
204 intc_bank_read_reg(bank, INTC_SYSCONFIG);
205 intc_context[ind].protection =
206 intc_bank_read_reg(bank, INTC_PROTECTION);
207 intc_context[ind].idle =
208 intc_bank_read_reg(bank, INTC_IDLE);
209 intc_context[ind].threshold =
210 intc_bank_read_reg(bank, INTC_THRESHOLD);
211 for (i = 0; i < INTCPS_NR_IRQS; i++)
212 intc_context[ind].ilr[i] =
213 intc_bank_read_reg(bank, (0x100 + 0x4*i));
214 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
215 intc_context[ind].mir[i] =
216 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
221 void omap_intc_restore_context(void)
225 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
226 struct omap_irq_bank *bank = irq_banks + ind;
227 intc_bank_write_reg(intc_context[ind].sysconfig,
228 bank, INTC_SYSCONFIG);
229 intc_bank_write_reg(intc_context[ind].sysconfig,
230 bank, INTC_SYSCONFIG);
231 intc_bank_write_reg(intc_context[ind].protection,
232 bank, INTC_PROTECTION);
233 intc_bank_write_reg(intc_context[ind].idle,
235 intc_bank_write_reg(intc_context[ind].threshold,
236 bank, INTC_THRESHOLD);
237 for (i = 0; i < INTCPS_NR_IRQS; i++)
238 intc_bank_write_reg(intc_context[ind].ilr[i],
239 bank, (0x100 + 0x4*i));
240 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
241 intc_bank_write_reg(intc_context[ind].mir[i],
242 &irq_banks[0], INTC_MIR0 + (0x20 * i));
244 /* MIRs are saved and restore with other PRCM registers */
247 void omap3_intc_suspend(void)
249 /* A pending interrupt would prevent OMAP from entering suspend */
253 void omap3_intc_prepare_idle(void)
256 * Disable autoidle as it can stall interrupt controller,
257 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
259 intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
262 void omap3_intc_resume_idle(void)
264 /* Re-enable autoidle */
265 intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
267 #endif /* CONFIG_ARCH_OMAP3 */