2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
31 #include <plat/clock.h>
32 #include <plat/sram.h>
33 #include <plat/sdrc.h>
34 #include <asm/div64.h>
35 #include <asm/clkdev.h>
37 #include <plat/sdrc.h>
39 #include "clock34xx.h"
42 #include "prm-regbits-34xx.h"
44 #include "cm-regbits-34xx.h"
46 #define CYCLES_PER_MHZ 1000000
49 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
50 * that are sourced by DPLL5, and both of these require this clock
51 * to be at 120 MHz for proper operation.
53 #define DPLL5_FREQ_FOR_USBHOST 120000000
55 /* needed by omap3_core_dpll_m2_set_rate() */
56 struct clk *sdrc_ick_p, *arm_fck_p;
59 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
60 * @clk: struct clk * being enabled
61 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
62 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
64 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
65 * from the CM_{I,F}CLKEN bit. Pass back the correct info via
66 * @idlest_reg and @idlest_bit. No return value.
68 static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
69 void __iomem **idlest_reg,
74 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
75 *idlest_reg = (__force void __iomem *)r;
76 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
79 const struct clkops clkops_omap3430es2_ssi_wait = {
80 .enable = omap2_dflt_clk_enable,
81 .disable = omap2_dflt_clk_disable,
82 .find_idlest = omap3430es2_clk_ssi_find_idlest,
83 .find_companion = omap2_clk_dflt_find_companion,
87 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
88 * @clk: struct clk * being enabled
89 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
90 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
92 * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
93 * target IDLEST bits. For our purposes, we are concerned with the
94 * target IDLEST bits, which exist at a different bit position than
95 * the *CLKEN bit position for these modules (DSS and USBHOST) (The
96 * default find_idlest code assumes that they are at the same
97 * position.) No return value.
99 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
100 void __iomem **idlest_reg,
105 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
106 *idlest_reg = (__force void __iomem *)r;
107 /* USBHOST_IDLE has same shift */
108 *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
111 const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
112 .enable = omap2_dflt_clk_enable,
113 .disable = omap2_dflt_clk_disable,
114 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
115 .find_companion = omap2_clk_dflt_find_companion,
119 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
120 * @clk: struct clk * being enabled
121 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
122 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
124 * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
125 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
126 * @idlest_reg and @idlest_bit. No return value.
128 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
129 void __iomem **idlest_reg,
134 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
135 *idlest_reg = (__force void __iomem *)r;
136 *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
139 const struct clkops clkops_omap3430es2_hsotgusb_wait = {
140 .enable = omap2_dflt_clk_enable,
141 .disable = omap2_dflt_clk_disable,
142 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
143 .find_companion = omap2_clk_dflt_find_companion,
146 const struct clkops clkops_noncore_dpll_ops = {
147 .enable = omap3_noncore_dpll_enable,
148 .disable = omap3_noncore_dpll_disable,
151 int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
154 * According to the 12-5 CDP code from TI, "Limitation 2.5"
155 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
158 if (omap_rev() == OMAP3430_REV_ES1_0) {
159 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
160 "silicon 'Limitation 2.5' on 3430ES1.\n");
163 return omap3_noncore_dpll_set_rate(clk, rate);
168 * CORE DPLL (DPLL3) rate programming functions
170 * These call into SRAM code to do the actual CM writes, since the SDRAM
171 * is clocked from DPLL3.
175 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
176 * @clk: struct clk * of DPLL to set
177 * @rate: rounded target rate
179 * Program the DPLL M2 divider with the rounded target rate. Returns
180 * -EINVAL upon error, or 0 upon success.
182 int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
187 unsigned long validrate, sdrcrate, _mpurate;
188 struct omap_sdrc_params *sdrc_cs0;
189 struct omap_sdrc_params *sdrc_cs1;
195 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
196 if (validrate != rate)
199 sdrcrate = sdrc_ick_p->rate;
200 if (rate > clk->rate)
201 sdrcrate <<= ((rate / clk->rate) >> 1);
203 sdrcrate >>= ((clk->rate / rate) >> 1);
205 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
209 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
210 pr_debug("clock: will unlock SDRC DLL\n");
215 * XXX This only needs to be done when the CPU frequency changes
217 _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
218 c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
219 c += 1; /* for safety */
220 c *= SDRC_MPURATE_LOOPS;
221 c >>= SDRC_MPURATE_SCALE;
225 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
227 pr_debug("clock: SDRC CS0 timing params used:"
228 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
229 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
230 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
232 pr_debug("clock: SDRC CS1 timing params used: "
233 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
234 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
235 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
238 omap3_configure_core_dpll(
239 new_div, unlock_dll, c, rate > clk->rate,
240 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
241 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
242 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
243 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
245 omap3_configure_core_dpll(
246 new_div, unlock_dll, c, rate > clk->rate,
247 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
248 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
254 /* Common clock code */
257 * As it is structured now, this will prevent an OMAP2/3 multiboot
258 * kernel from compiling. This will need further attention.
260 #if defined(CONFIG_ARCH_OMAP3)
262 struct clk_functions omap2_clk_functions = {
263 .clk_enable = omap2_clk_enable,
264 .clk_disable = omap2_clk_disable,
265 .clk_round_rate = omap2_clk_round_rate,
266 .clk_set_rate = omap2_clk_set_rate,
267 .clk_set_parent = omap2_clk_set_parent,
268 .clk_disable_unused = omap2_clk_disable_unused,
272 * Set clocks for bypass mode for reboot to work.
274 void omap2_clk_prepare_for_reboot(void)
276 /* REVISIT: Not ready for 343x */
280 if (vclk == NULL || sclk == NULL)
283 rate = clk_get_rate(sclk);
284 clk_set_rate(vclk, rate);
288 void omap3_clk_lock_dpll5(void)
290 struct clk *dpll5_clk;
291 struct clk *dpll5_m2_clk;
293 dpll5_clk = clk_get(NULL, "dpll5_ck");
294 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
295 clk_enable(dpll5_clk);
297 /* Enable autoidle to allow it to enter low power bypass */
298 omap3_dpll_allow_idle(dpll5_clk);
300 /* Program dpll5_m2_clk divider for no division */
301 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
302 clk_enable(dpll5_m2_clk);
303 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
305 clk_disable(dpll5_m2_clk);
306 clk_disable(dpll5_clk);
310 /* REVISIT: Move this init stuff out into clock.c */
313 * Switch the MPU rate if specified on cmdline.
314 * We cannot do this early until cmdline is parsed.
316 static int __init omap2_clk_arch_init(void)
318 struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
319 unsigned long osc_sys_rate;
324 /* XXX test these for success */
325 dpll1_ck = clk_get(NULL, "dpll1_ck");
326 arm_fck = clk_get(NULL, "arm_fck");
327 core_ck = clk_get(NULL, "core_ck");
328 osc_sys_ck = clk_get(NULL, "osc_sys_ck");
330 /* REVISIT: not yet ready for 343x */
331 if (clk_set_rate(dpll1_ck, mpurate))
332 printk(KERN_ERR "*** Unable to set MPU rate\n");
334 recalculate_root_clocks();
336 osc_sys_rate = clk_get_rate(osc_sys_ck);
338 pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
339 "%ld.%01ld/%ld/%ld MHz\n",
340 (osc_sys_rate / 1000000),
341 ((osc_sys_rate / 100000) % 10),
342 (clk_get_rate(core_ck) / 1000000),
343 (clk_get_rate(arm_fck) / 1000000));
349 arch_initcall(omap2_clk_arch_init);