2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/platform_device.h>
15 #include <mach/hardware.h>
18 /* set cpu low power mode before WFI instruction. This function is called
19 * mx5 because it can be used for mx50, mx51, and mx53.*/
20 void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
22 u32 plat_lpc, arm_srpgcr, ccm_clpcr;
26 /* always allow platform to issue a deep sleep mode request */
27 plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
28 ~(MXC_CORTEXA8_PLAT_LPC_DSM);
29 ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
30 arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
31 empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
32 empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
38 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
40 case WAIT_UNCLOCKED_POWER_OFF:
42 plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
43 | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
44 if (mode == WAIT_UNCLOCKED_POWER_OFF) {
45 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
46 ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
47 ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
50 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
51 ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
52 ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
53 ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
56 arm_srpgcr |= MXC_SRPGCR_PCR;
58 if (tzic_enable_wake(1) != 0)
62 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
65 printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
69 __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
70 __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
71 __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
73 /* Enable NEON SRPG for all but MX50TO1.0. */
74 if (mx50_revision() != IMX_CHIP_REVISION_1_0)
75 __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
78 empgc0 |= MXC_SRPGCR_PCR;
79 empgc1 |= MXC_SRPGCR_PCR;
81 __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
82 __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);