2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c.h>
18 #include <linux/gpio.h>
19 #include <linux/leds.h>
20 #include <linux/input.h>
21 #include <linux/delay.h>
23 #include <linux/spi/flash.h>
24 #include <linux/spi/spi.h>
25 #include <linux/mfd/mc13892.h>
26 #include <linux/regulator/machine.h>
27 #include <linux/regulator/consumer.h>
29 #include <mach/common.h>
30 #include <mach/hardware.h>
31 #include <mach/iomux-mx51.h>
33 #include <linux/usb/otg.h>
34 #include <linux/usb/ulpi.h>
35 #include <mach/ulpi.h>
38 #include <asm/setup.h>
39 #include <asm/mach-types.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/time.h>
43 #include "devices-imx51.h"
46 #include "cpu_op-mx51.h"
48 #define MX51_USB_CTRL_1_OFFSET 0x10
49 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
50 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
52 #define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
53 #define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
55 #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
56 #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
58 #define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
60 static iomux_v3_cfg_t mx51efika_pads[] = {
62 MX51_PAD_UART1_RXD__UART1_RXD,
63 MX51_PAD_UART1_TXD__UART1_TXD,
64 MX51_PAD_UART1_RTS__UART1_RTS,
65 MX51_PAD_UART1_CTS__UART1_CTS,
68 MX51_PAD_SD1_CMD__SD1_CMD,
69 MX51_PAD_SD1_CLK__SD1_CLK,
70 MX51_PAD_SD1_DATA0__SD1_DATA0,
71 MX51_PAD_SD1_DATA1__SD1_DATA1,
72 MX51_PAD_SD1_DATA2__SD1_DATA2,
73 MX51_PAD_SD1_DATA3__SD1_DATA3,
76 MX51_PAD_SD2_CMD__SD2_CMD,
77 MX51_PAD_SD2_CLK__SD2_CLK,
78 MX51_PAD_SD2_DATA0__SD2_DATA0,
79 MX51_PAD_SD2_DATA1__SD2_DATA1,
80 MX51_PAD_SD2_DATA2__SD2_DATA2,
81 MX51_PAD_SD2_DATA3__SD2_DATA3,
84 MX51_PAD_GPIO1_0__SD1_CD,
85 MX51_PAD_GPIO1_1__SD1_WP,
86 MX51_PAD_GPIO1_7__SD2_WP,
87 MX51_PAD_GPIO1_8__SD2_CD,
90 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
91 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
92 MX51_PAD_CSPI1_SS0__GPIO4_24,
93 MX51_PAD_CSPI1_SS1__GPIO4_25,
94 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
95 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
96 MX51_PAD_GPIO1_6__GPIO1_6,
99 MX51_PAD_USBH1_CLK__USBH1_CLK,
100 MX51_PAD_USBH1_DIR__USBH1_DIR,
101 MX51_PAD_USBH1_NXT__USBH1_NXT,
102 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
103 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
104 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
105 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
106 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
107 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
108 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
109 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
112 MX51_PAD_GPIO1_5__GPIO1_5,
115 MX51_PAD_EIM_A22__GPIO2_16,
116 MX51_PAD_EIM_A16__GPIO2_10,
119 MX51_PAD_EIM_D27__GPIO2_9,
123 static const struct imxuart_platform_data uart_pdata = {
124 .flags = IMXUART_HAVE_RTSCTS,
127 /* This function is board specific as the bit mask for the plldiv will also
128 * be different for other Freescale SoCs, thus a common bitmask is not
129 * possible and cannot get place in /plat-mxc/ehci.c.
131 static int initialize_otg_port(struct platform_device *pdev)
134 void __iomem *usb_base;
135 void __iomem *usbother_base;
136 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
139 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
141 /* Set the PHY clock to 19.2MHz */
142 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
143 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
144 v |= MX51_USB_PLL_DIV_19_2_MHZ;
145 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
150 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
153 static struct mxc_usbh_platform_data dr_utmi_config = {
154 .init = initialize_otg_port,
155 .portsc = MXC_EHCI_UTMI_16BIT,
158 static int initialize_usbh1_port(struct platform_device *pdev)
160 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
161 iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
163 void __iomem *usb_base;
164 void __iomem *socregs_base;
166 mxc_iomux_v3_setup_pad(usbh1gpio);
167 gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
168 gpio_direction_output(EFIKAMX_USBH1_STP, 0);
170 gpio_set_value(EFIKAMX_USBH1_STP, 1);
173 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
174 socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
176 /* The clock for the USBH1 ULPI port will come externally */
178 v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
179 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
180 socregs_base + MX51_USB_CTRL_1_OFFSET);
184 gpio_free(EFIKAMX_USBH1_STP);
185 mxc_iomux_v3_setup_pad(usbh1stp);
189 return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD);
192 static struct mxc_usbh_platform_data usbh1_config = {
193 .init = initialize_usbh1_port,
194 .portsc = MXC_EHCI_MODE_ULPI,
197 static void mx51_efika_hubreset(void)
199 gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
200 gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
202 gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
204 gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
207 static void __init mx51_efika_usb(void)
209 mx51_efika_hubreset();
211 /* pulling it low, means no USB at all... */
212 gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
213 gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
215 gpio_set_value(EFIKA_USB_PHY_RESET, 1);
217 usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
218 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
220 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
221 if (usbh1_config.otg)
222 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
225 static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
233 .offset = MTDPART_OFS_APPEND,
238 static struct flash_platform_data mx51_efika_spi_flash_data = {
240 .parts = mx51_efika_spi_nor_partitions,
241 .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
242 .type = "sst25vf032b",
245 static struct regulator_consumer_supply sw1_consumers[] = {
251 static struct regulator_consumer_supply vdig_consumers[] = {
253 REGULATOR_SUPPLY("VDDA", "1-000a"),
254 REGULATOR_SUPPLY("VDDD", "1-000a"),
257 static struct regulator_consumer_supply vvideo_consumers[] = {
259 REGULATOR_SUPPLY("VDDIO", "1-000a"),
262 static struct regulator_consumer_supply vsd_consumers[] = {
263 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
264 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
267 static struct regulator_consumer_supply pwgt1_consumer[] = {
273 static struct regulator_consumer_supply pwgt2_consumer[] = {
279 static struct regulator_consumer_supply coincell_consumer[] = {
281 .supply = "coincell",
285 static struct regulator_init_data sw1_init = {
290 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
291 .valid_modes_mask = 0,
296 .mode = REGULATOR_MODE_NORMAL,
300 .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
301 .consumer_supplies = sw1_consumers,
304 static struct regulator_init_data sw2_init = {
309 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
314 .mode = REGULATOR_MODE_NORMAL,
320 static struct regulator_init_data sw3_init = {
325 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
331 static struct regulator_init_data sw4_init = {
336 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
342 static struct regulator_init_data viohi_init = {
350 static struct regulator_init_data vusb_init = {
358 static struct regulator_init_data swbst_init = {
364 static struct regulator_init_data vdig_init = {
370 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
374 .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
375 .consumer_supplies = vdig_consumers,
378 static struct regulator_init_data vpll_init = {
384 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
390 static struct regulator_init_data vusb2_init = {
395 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
401 static struct regulator_init_data vvideo_init = {
407 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
411 .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
412 .consumer_supplies = vvideo_consumers,
415 static struct regulator_init_data vaudio_init = {
421 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
426 static struct regulator_init_data vsd_init = {
432 REGULATOR_CHANGE_VOLTAGE,
435 .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
436 .consumer_supplies = vsd_consumers,
439 static struct regulator_init_data vcam_init = {
445 REGULATOR_CHANGE_VOLTAGE |
446 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
447 .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
452 static struct regulator_init_data vgen1_init = {
458 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
464 static struct regulator_init_data vgen2_init = {
470 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
476 static struct regulator_init_data vgen3_init = {
482 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
488 static struct regulator_init_data gpo1_init = {
494 static struct regulator_init_data gpo2_init = {
500 static struct regulator_init_data gpo3_init = {
506 static struct regulator_init_data gpo4_init = {
512 static struct regulator_init_data pwgt1_init = {
514 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
517 .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
518 .consumer_supplies = pwgt1_consumer,
521 static struct regulator_init_data pwgt2_init = {
523 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
526 .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
527 .consumer_supplies = pwgt2_consumer,
530 static struct regulator_init_data vcoincell_init = {
536 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
538 .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
539 .consumer_supplies = coincell_consumer,
542 static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
543 { .id = MC13892_SW1, .init_data = &sw1_init },
544 { .id = MC13892_SW2, .init_data = &sw2_init },
545 { .id = MC13892_SW3, .init_data = &sw3_init },
546 { .id = MC13892_SW4, .init_data = &sw4_init },
547 { .id = MC13892_SWBST, .init_data = &swbst_init },
548 { .id = MC13892_VIOHI, .init_data = &viohi_init },
549 { .id = MC13892_VPLL, .init_data = &vpll_init },
550 { .id = MC13892_VDIG, .init_data = &vdig_init },
551 { .id = MC13892_VSD, .init_data = &vsd_init },
552 { .id = MC13892_VUSB2, .init_data = &vusb2_init },
553 { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
554 { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
555 { .id = MC13892_VCAM, .init_data = &vcam_init },
556 { .id = MC13892_VGEN1, .init_data = &vgen1_init },
557 { .id = MC13892_VGEN2, .init_data = &vgen2_init },
558 { .id = MC13892_VGEN3, .init_data = &vgen3_init },
559 { .id = MC13892_VUSB, .init_data = &vusb_init },
560 { .id = MC13892_GPO1, .init_data = &gpo1_init },
561 { .id = MC13892_GPO2, .init_data = &gpo2_init },
562 { .id = MC13892_GPO3, .init_data = &gpo3_init },
563 { .id = MC13892_GPO4, .init_data = &gpo4_init },
564 { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
565 { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
566 { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
569 static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
570 .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
572 .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
573 .regulators = mx51_efika_regulators,
577 static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
579 .modalias = "m25p80",
580 .max_speed_hz = 25000000,
583 .platform_data = &mx51_efika_spi_flash_data,
587 .modalias = "mc13892",
588 .max_speed_hz = 1000000,
591 .platform_data = &mx51_efika_mc13892_data,
592 .irq = gpio_to_irq(EFIKAMX_PMIC),
596 static int mx51_efika_spi_cs[] = {
601 static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
602 .chipselect = mx51_efika_spi_cs,
603 .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
606 void __init efika_board_common_init(void)
608 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
609 ARRAY_SIZE(mx51efika_pads));
610 imx51_add_imx_uart(0, &uart_pdata);
612 imx51_add_sdhci_esdhc_imx(0, NULL);
614 /* FIXME: comes from original code. check this. */
615 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
616 sw2_init.constraints.state_mem.uV = 1100000;
617 else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
618 sw2_init.constraints.state_mem.uV = 1250000;
619 sw1_init.constraints.state_mem.uV = 1000000;
621 if (machine_is_mx51_efikasb())
622 vgen1_init.constraints.max_uV = 1200000;
624 gpio_request(EFIKAMX_PMIC, "pmic irq");
625 gpio_direction_input(EFIKAMX_PMIC);
626 spi_register_board_info(mx51_efika_spi_board_info,
627 ARRAY_SIZE(mx51_efika_spi_board_info));
628 imx51_add_ecspi(0, &mx51_efika_spi_pdata);
630 #if defined(CONFIG_CPU_FREQ_IMX)
631 get_cpu_op = mx51_get_cpu_op;