arch/arm/mach-msm/devices-iommu.c

   1 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/bootmem.h>
  21 #include <mach/irqs.h>
  22 #include <mach/iommu.h>
  23
  24 static struct resource msm_iommu_jpegd_resources[] = {
  25         {
  26                 .start = 0x07300000,
  27                 .end   = 0x07300000 + SZ_1M - 1,
  28                 .name  = "physbase",
  29                 .flags = IORESOURCE_MEM,
  30         },
  31         {
  32                 .name = "nonsecure_irq",
  33                 .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
  34                 .end   = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
  35                 .flags = IORESOURCE_IRQ,
  36         },
  37         {
  38                 .name = "secure_irq",
  39                 .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
  40                 .end   = SMMU_JPEGD_CB_SC_SECURE_IRQ,
  41                 .flags = IORESOURCE_IRQ,
  42         },
  43 };
  44
  45 static struct resource msm_iommu_vpe_resources[] = {
  46         {
  47                 .start = 0x07400000,
  48                 .end   = 0x07400000 + SZ_1M - 1,
  49                 .name  = "physbase",
  50                 .flags = IORESOURCE_MEM,
  51         },
  52         {
  53                 .name = "nonsecure_irq",
  54                 .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
  55                 .end   = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
  56                 .flags = IORESOURCE_IRQ,
  57         },
  58         {
  59                 .name = "secure_irq",
  60                 .start = SMMU_VPE_CB_SC_SECURE_IRQ,
  61                 .end   = SMMU_VPE_CB_SC_SECURE_IRQ,
  62                 .flags = IORESOURCE_IRQ,
  63         },
  64 };
  65
  66 static struct resource msm_iommu_mdp0_resources[] = {
  67         {
  68                 .start = 0x07500000,
  69                 .end   = 0x07500000 + SZ_1M - 1,
  70                 .name  = "physbase",
  71                 .flags = IORESOURCE_MEM,
  72         },
  73         {
  74                 .name = "nonsecure_irq",
  75                 .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
  76                 .end   = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
  77                 .flags = IORESOURCE_IRQ,
  78         },
  79         {
  80                 .name = "secure_irq",
  81                 .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
  82                 .end   = SMMU_MDP0_CB_SC_SECURE_IRQ,
  83                 .flags = IORESOURCE_IRQ,
  84         },
  85 };
  86
  87 static struct resource msm_iommu_mdp1_resources[] = {
  88         {
  89                 .start = 0x07600000,
  90                 .end   = 0x07600000 + SZ_1M - 1,
  91                 .name  = "physbase",
  92                 .flags = IORESOURCE_MEM,
  93         },
  94         {
  95                 .name = "nonsecure_irq",
  96                 .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
  97                 .end   = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
  98                 .flags = IORESOURCE_IRQ,
  99         },
 100         {
 101                 .name = "secure_irq",
 102                 .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
 103                 .end   = SMMU_MDP1_CB_SC_SECURE_IRQ,
 104                 .flags = IORESOURCE_IRQ,
 105         },
 106 };
 107
 108 static struct resource msm_iommu_rot_resources[] = {
 109         {
 110                 .start = 0x07700000,
 111                 .end   = 0x07700000 + SZ_1M - 1,
 112                 .name  = "physbase",
 113                 .flags = IORESOURCE_MEM,
 114         },
 115         {
 116                 .name = "nonsecure_irq",
 117                 .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
 118                 .end   = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
 119                 .flags = IORESOURCE_IRQ,
 120         },
 121         {
 122                 .name = "secure_irq",
 123                 .start = SMMU_ROT_CB_SC_SECURE_IRQ,
 124                 .end   = SMMU_ROT_CB_SC_SECURE_IRQ,
 125                 .flags = IORESOURCE_IRQ,
 126         },
 127 };
 128
 129 static struct resource msm_iommu_ijpeg_resources[] = {
 130         {
 131                 .start = 0x07800000,
 132                 .end   = 0x07800000 + SZ_1M - 1,
 133                 .name  = "physbase",
 134                 .flags = IORESOURCE_MEM,
 135         },
 136         {
 137                 .name = "nonsecure_irq",
 138                 .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
 139                 .end   = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
 140                 .flags = IORESOURCE_IRQ,
 141         },
 142         {
 143                 .name = "secure_irq",
 144                 .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
 145                 .end   = SMMU_IJPEG_CB_SC_SECURE_IRQ,
 146                 .flags = IORESOURCE_IRQ,
 147         },
 148 };
 149
 150 static struct resource msm_iommu_vfe_resources[] = {
 151         {
 152                 .start = 0x07900000,
 153                 .end   = 0x07900000 + SZ_1M - 1,
 154                 .name  = "physbase",
 155                 .flags = IORESOURCE_MEM,
 156         },
 157         {
 158                 .name = "nonsecure_irq",
 159                 .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
 160                 .end   = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
 161                 .flags = IORESOURCE_IRQ,
 162         },
 163         {
 164                 .name = "secure_irq",
 165                 .start = SMMU_VFE_CB_SC_SECURE_IRQ,
 166                 .end   = SMMU_VFE_CB_SC_SECURE_IRQ,
 167                 .flags = IORESOURCE_IRQ,
 168         },
 169 };
 170
 171 static struct resource msm_iommu_vcodec_a_resources[] = {
 172         {
 173                 .start = 0x07A00000,
 174                 .end   = 0x07A00000 + SZ_1M - 1,
 175                 .name  = "physbase",
 176                 .flags = IORESOURCE_MEM,
 177         },
 178         {
 179                 .name = "nonsecure_irq",
 180                 .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
 181                 .end   = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
 182                 .flags = IORESOURCE_IRQ,
 183         },
 184         {
 185                 .name = "secure_irq",
 186                 .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
 187                 .end   = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
 188                 .flags = IORESOURCE_IRQ,
 189         },
 190 };
 191
 192 static struct resource msm_iommu_vcodec_b_resources[] = {
 193         {
 194                 .start = 0x07B00000,
 195                 .end   = 0x07B00000 + SZ_1M - 1,
 196                 .name  = "physbase",
 197                 .flags = IORESOURCE_MEM,
 198         },
 199         {
 200                 .name = "nonsecure_irq",
 201                 .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
 202                 .end   = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
 203                 .flags = IORESOURCE_IRQ,
 204         },
 205         {
 206                 .name = "secure_irq",
 207                 .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
 208                 .end   = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
 209                 .flags = IORESOURCE_IRQ,
 210         },
 211 };
 212
 213 static struct resource msm_iommu_gfx3d_resources[] = {
 214         {
 215                 .start = 0x07C00000,
 216                 .end   = 0x07C00000 + SZ_1M - 1,
 217                 .name  = "physbase",
 218                 .flags = IORESOURCE_MEM,
 219         },
 220         {
 221                 .name = "nonsecure_irq",
 222                 .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
 223                 .end   = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
 224                 .flags = IORESOURCE_IRQ,
 225         },
 226         {
 227                 .name = "secure_irq",
 228                 .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
 229                 .end   = SMMU_GFX3D_CB_SC_SECURE_IRQ,
 230                 .flags = IORESOURCE_IRQ,
 231         },
 232 };
 233
 234 static struct resource msm_iommu_gfx2d0_resources[] = {
 235         {
 236                 .start = 0x07D00000,
 237                 .end   = 0x07D00000 + SZ_1M - 1,
 238                 .name  = "physbase",
 239                 .flags = IORESOURCE_MEM,
 240         },
 241         {
 242                 .name = "nonsecure_irq",
 243                 .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
 244                 .end   = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
 245                 .flags = IORESOURCE_IRQ,
 246         },
 247         {
 248                 .name = "secure_irq",
 249                 .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
 250                 .end   = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
 251                 .flags = IORESOURCE_IRQ,
 252         },
 253 };
 254
 255 static struct resource msm_iommu_gfx2d1_resources[] = {
 256         {
 257                 .start = 0x07E00000,
 258                 .end   = 0x07E00000 + SZ_1M - 1,
 259                 .name  = "physbase",
 260                 .flags = IORESOURCE_MEM,
 261         },
 262         {
 263                 .name = "nonsecure_irq",
 264                 .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
 265                 .end   = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
 266                 .flags = IORESOURCE_IRQ,
 267         },
 268         {
 269                 .name = "secure_irq",
 270                 .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
 271                 .end   = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
 272                 .flags = IORESOURCE_IRQ,
 273         },
 274 };
 275
 276 static struct platform_device msm_root_iommu_dev = {
 277         .name = "msm_iommu",
 278         .id = -1,
 279 };
 280
 281 static struct msm_iommu_dev jpegd_iommu = {
 282         .name = "jpegd",
 283         .clk_rate = -1
 284 };
 285
 286 static struct msm_iommu_dev vpe_iommu = {
 287         .name = "vpe"
 288 };
 289
 290 static struct msm_iommu_dev mdp0_iommu = {
 291         .name = "mdp0"
 292 };
 293
 294 static struct msm_iommu_dev mdp1_iommu = {
 295         .name = "mdp1"
 296 };
 297
 298 static struct msm_iommu_dev rot_iommu = {
 299         .name = "rot"
 300 };
 301
 302 static struct msm_iommu_dev ijpeg_iommu = {
 303         .name = "ijpeg"
 304 };
 305
 306 static struct msm_iommu_dev vfe_iommu = {
 307         .name = "vfe",
 308         .clk_rate = -1
 309 };
 310
 311 static struct msm_iommu_dev vcodec_a_iommu = {
 312         .name = "vcodec_a"
 313 };
 314
 315 static struct msm_iommu_dev vcodec_b_iommu = {
 316         .name = "vcodec_b"
 317 };
 318
 319 static struct msm_iommu_dev gfx3d_iommu = {
 320         .name = "gfx3d",
 321         .clk_rate = 27000000
 322 };
 323
 324 static struct msm_iommu_dev gfx2d0_iommu = {
 325         .name = "gfx2d0",
 326         .clk_rate = 27000000
 327 };
 328
 329 static struct msm_iommu_dev gfx2d1_iommu = {
 330         .name = "gfx2d1",
 331         .clk_rate = 27000000
 332 };
 333
 334 static struct platform_device msm_device_iommu_jpegd = {
 335         .name = "msm_iommu",
 336         .id = 0,
 337         .dev = {
 338                 .parent = &msm_root_iommu_dev.dev,
 339         },
 340         .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
 341         .resource = msm_iommu_jpegd_resources,
 342 };
 343
 344 static struct platform_device msm_device_iommu_vpe = {
 345         .name = "msm_iommu",
 346         .id = 1,
 347         .dev = {
 348                 .parent = &msm_root_iommu_dev.dev,
 349         },
 350         .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
 351         .resource = msm_iommu_vpe_resources,
 352 };
 353
 354 static struct platform_device msm_device_iommu_mdp0 = {
 355         .name = "msm_iommu",
 356         .id = 2,
 357         .dev = {
 358                 .parent = &msm_root_iommu_dev.dev,
 359         },
 360         .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
 361         .resource = msm_iommu_mdp0_resources,
 362 };
 363
 364 static struct platform_device msm_device_iommu_mdp1 = {
 365         .name = "msm_iommu",
 366         .id = 3,
 367         .dev = {
 368                 .parent = &msm_root_iommu_dev.dev,
 369         },
 370         .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
 371         .resource = msm_iommu_mdp1_resources,
 372 };
 373
 374 static struct platform_device msm_device_iommu_rot = {
 375         .name = "msm_iommu",
 376         .id = 4,
 377         .dev = {
 378                 .parent = &msm_root_iommu_dev.dev,
 379         },
 380         .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
 381         .resource = msm_iommu_rot_resources,
 382 };
 383
 384 static struct platform_device msm_device_iommu_ijpeg = {
 385         .name = "msm_iommu",
 386         .id = 5,
 387         .dev = {
 388                 .parent = &msm_root_iommu_dev.dev,
 389         },
 390         .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
 391         .resource = msm_iommu_ijpeg_resources,
 392 };
 393
 394 static struct platform_device msm_device_iommu_vfe = {
 395         .name = "msm_iommu",
 396         .id = 6,
 397         .dev = {
 398                 .parent = &msm_root_iommu_dev.dev,
 399         },
 400         .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
 401         .resource = msm_iommu_vfe_resources,
 402 };
 403
 404 static struct platform_device msm_device_iommu_vcodec_a = {
 405         .name = "msm_iommu",
 406         .id = 7,
 407         .dev = {
 408                 .parent = &msm_root_iommu_dev.dev,
 409         },
 410         .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
 411         .resource = msm_iommu_vcodec_a_resources,
 412 };
 413
 414 static struct platform_device msm_device_iommu_vcodec_b = {
 415         .name = "msm_iommu",
 416         .id = 8,
 417         .dev = {
 418                 .parent = &msm_root_iommu_dev.dev,
 419         },
 420         .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
 421         .resource = msm_iommu_vcodec_b_resources,
 422 };
 423
 424 static struct platform_device msm_device_iommu_gfx3d = {
 425         .name = "msm_iommu",
 426         .id = 9,
 427         .dev = {
 428                 .parent = &msm_root_iommu_dev.dev,
 429         },
 430         .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
 431         .resource = msm_iommu_gfx3d_resources,
 432 };
 433
 434 static struct platform_device msm_device_iommu_gfx2d0 = {
 435         .name = "msm_iommu",
 436         .id = 10,
 437         .dev = {
 438                 .parent = &msm_root_iommu_dev.dev,
 439         },
 440         .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
 441         .resource = msm_iommu_gfx2d0_resources,
 442 };
 443
 444 struct platform_device msm_device_iommu_gfx2d1 = {
 445         .name = "msm_iommu",
 446         .id = 11,
 447         .dev = {
 448                 .parent = &msm_root_iommu_dev.dev,
 449         },
 450         .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
 451         .resource = msm_iommu_gfx2d1_resources,
 452 };
 453
 454 static struct msm_iommu_ctx_dev jpegd_src_ctx = {
 455         .name = "jpegd_src",
 456         .num = 0,
 457         .mids = {0, -1}
 458 };
 459
 460 static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
 461         .name = "jpegd_dst",
 462         .num = 1,
 463         .mids = {1, -1}
 464 };
 465
 466 static struct msm_iommu_ctx_dev vpe_src_ctx = {
 467         .name = "vpe_src",
 468         .num = 0,
 469         .mids = {0, -1}
 470 };
 471
 472 static struct msm_iommu_ctx_dev vpe_dst_ctx = {
 473         .name = "vpe_dst",
 474         .num = 1,
 475         .mids = {1, -1}
 476 };
 477
 478 static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
 479         .name = "mdp_vg1",
 480         .num = 0,
 481         .mids = {0, 2, -1}
 482 };
 483
 484 static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
 485         .name = "mdp_rgb1",
 486         .num = 1,
 487         .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
 488 };
 489
 490 static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
 491         .name = "mdp_vg2",
 492         .num = 0,
 493         .mids = {0, 2, -1}
 494 };
 495
 496 static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
 497         .name = "mdp_rgb2",
 498         .num = 1,
 499         .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
 500 };
 501
 502 static struct msm_iommu_ctx_dev rot_src_ctx = {
 503         .name = "rot_src",
 504         .num = 0,
 505         .mids = {0, -1}
 506 };
 507
 508 static struct msm_iommu_ctx_dev rot_dst_ctx = {
 509         .name = "rot_dst",
 510         .num = 1,
 511         .mids = {1, -1}
 512 };
 513
 514 static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
 515         .name = "ijpeg_src",
 516         .num = 0,
 517         .mids = {0, -1}
 518 };
 519
 520 static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
 521         .name = "ijpeg_dst",
 522         .num = 1,
 523         .mids = {1, -1}
 524 };
 525
 526 static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
 527         .name = "vfe_imgwr",
 528         .num = 0,
 529         .mids = {2, 3, 4, 5, 6, 7, 8, -1}
 530 };
 531
 532 static struct msm_iommu_ctx_dev vfe_misc_ctx = {
 533         .name = "vfe_misc",
 534         .num = 1,
 535         .mids = {0, 1, 9, -1}
 536 };
 537
 538 static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
 539         .name = "vcodec_a_stream",
 540         .num = 0,
 541         .mids = {2, 5, -1}
 542 };
 543
 544 static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
 545         .name = "vcodec_a_mm1",
 546         .num = 1,
 547         .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
 548 };
 549
 550 static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
 551         .name = "vcodec_b_mm2",
 552         .num = 0,
 553         .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
 554 };
 555
 556 static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
 557         .name = "gfx3d_user",
 558         .num = 0,
 559         .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
 560 };
 561
 562 static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
 563         .name = "gfx3d_priv",
 564         .num = 1,
 565         .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
 566                  31, -1}
 567 };
 568
 569 static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
 570         .name = "gfx2d0_2d0",
 571         .num = 0,
 572         .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
 573 };
 574
 575 static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
 576         .name = "gfx2d1_2d1",
 577         .num = 0,
 578         .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
 579 };
 580
 581 static struct platform_device msm_device_jpegd_src_ctx = {
 582         .name = "msm_iommu_ctx",
 583         .id = 0,
 584         .dev = {
 585                 .parent = &msm_device_iommu_jpegd.dev,
 586         },
 587 };
 588
 589 static struct platform_device msm_device_jpegd_dst_ctx = {
 590         .name = "msm_iommu_ctx",
 591         .id = 1,
 592         .dev = {
 593                 .parent = &msm_device_iommu_jpegd.dev,
 594         },
 595 };
 596
 597 static struct platform_device msm_device_vpe_src_ctx = {
 598         .name = "msm_iommu_ctx",
 599         .id = 2,
 600         .dev = {
 601                 .parent = &msm_device_iommu_vpe.dev,
 602         },
 603 };
 604
 605 static struct platform_device msm_device_vpe_dst_ctx = {
 606         .name = "msm_iommu_ctx",
 607         .id = 3,
 608         .dev = {
 609                 .parent = &msm_device_iommu_vpe.dev,
 610         },
 611 };
 612
 613 static struct platform_device msm_device_mdp_vg1_ctx = {
 614         .name = "msm_iommu_ctx",
 615         .id = 4,
 616         .dev = {
 617                 .parent = &msm_device_iommu_mdp0.dev,
 618         },
 619 };
 620
 621 static struct platform_device msm_device_mdp_rgb1_ctx = {
 622         .name = "msm_iommu_ctx",
 623         .id = 5,
 624         .dev = {
 625                 .parent = &msm_device_iommu_mdp0.dev,
 626         },
 627 };
 628
 629 static struct platform_device msm_device_mdp_vg2_ctx = {
 630         .name = "msm_iommu_ctx",
 631         .id = 6,
 632         .dev = {
 633                 .parent = &msm_device_iommu_mdp1.dev,
 634         },
 635 };
 636
 637 static struct platform_device msm_device_mdp_rgb2_ctx = {
 638         .name = "msm_iommu_ctx",
 639         .id = 7,
 640         .dev = {
 641                 .parent = &msm_device_iommu_mdp1.dev,
 642         },
 643 };
 644
 645 static struct platform_device msm_device_rot_src_ctx = {
 646         .name = "msm_iommu_ctx",
 647         .id = 8,
 648         .dev = {
 649                 .parent = &msm_device_iommu_rot.dev,
 650         },
 651 };
 652
 653 static struct platform_device msm_device_rot_dst_ctx = {
 654         .name = "msm_iommu_ctx",
 655         .id = 9,
 656         .dev = {
 657                 .parent = &msm_device_iommu_rot.dev,
 658         },
 659 };
 660
 661 static struct platform_device msm_device_ijpeg_src_ctx = {
 662         .name = "msm_iommu_ctx",
 663         .id = 10,
 664         .dev = {
 665                 .parent = &msm_device_iommu_ijpeg.dev,
 666         },
 667 };
 668
 669 static struct platform_device msm_device_ijpeg_dst_ctx = {
 670         .name = "msm_iommu_ctx",
 671         .id = 11,
 672         .dev = {
 673                 .parent = &msm_device_iommu_ijpeg.dev,
 674         },
 675 };
 676
 677 static struct platform_device msm_device_vfe_imgwr_ctx = {
 678         .name = "msm_iommu_ctx",
 679         .id = 12,
 680         .dev = {
 681                 .parent = &msm_device_iommu_vfe.dev,
 682         },
 683 };
 684
 685 static struct platform_device msm_device_vfe_misc_ctx = {
 686         .name = "msm_iommu_ctx",
 687         .id = 13,
 688         .dev = {
 689                 .parent = &msm_device_iommu_vfe.dev,
 690         },
 691 };
 692
 693 static struct platform_device msm_device_vcodec_a_stream_ctx = {
 694         .name = "msm_iommu_ctx",
 695         .id = 14,
 696         .dev = {
 697                 .parent = &msm_device_iommu_vcodec_a.dev,
 698         },
 699 };
 700
 701 static struct platform_device msm_device_vcodec_a_mm1_ctx = {
 702         .name = "msm_iommu_ctx",
 703         .id = 15,
 704         .dev = {
 705                 .parent = &msm_device_iommu_vcodec_a.dev,
 706         },
 707 };
 708
 709 static struct platform_device msm_device_vcodec_b_mm2_ctx = {
 710         .name = "msm_iommu_ctx",
 711         .id = 16,
 712         .dev = {
 713                 .parent = &msm_device_iommu_vcodec_b.dev,
 714         },
 715 };
 716
 717 static struct platform_device msm_device_gfx3d_user_ctx = {
 718         .name = "msm_iommu_ctx",
 719         .id = 17,
 720         .dev = {
 721                 .parent = &msm_device_iommu_gfx3d.dev,
 722         },
 723 };
 724
 725 static struct platform_device msm_device_gfx3d_priv_ctx = {
 726         .name = "msm_iommu_ctx",
 727         .id = 18,
 728         .dev = {
 729                 .parent = &msm_device_iommu_gfx3d.dev,
 730         },
 731 };
 732
 733 static struct platform_device msm_device_gfx2d0_2d0_ctx = {
 734         .name = "msm_iommu_ctx",
 735         .id = 19,
 736         .dev = {
 737                 .parent = &msm_device_iommu_gfx2d0.dev,
 738         },
 739 };
 740
 741 static struct platform_device msm_device_gfx2d1_2d1_ctx = {
 742         .name = "msm_iommu_ctx",
 743         .id = 20,
 744         .dev = {
 745                 .parent = &msm_device_iommu_gfx2d1.dev,
 746         },
 747 };
 748
 749 static struct platform_device *msm_iommu_devs[] = {
 750         &msm_device_iommu_jpegd,
 751         &msm_device_iommu_vpe,
 752         &msm_device_iommu_mdp0,
 753         &msm_device_iommu_mdp1,
 754         &msm_device_iommu_rot,
 755         &msm_device_iommu_ijpeg,
 756         &msm_device_iommu_vfe,
 757         &msm_device_iommu_vcodec_a,
 758         &msm_device_iommu_vcodec_b,
 759         &msm_device_iommu_gfx3d,
 760         &msm_device_iommu_gfx2d0,
 761         &msm_device_iommu_gfx2d1,
 762 };
 763
 764 static struct msm_iommu_dev *msm_iommu_data[] = {
 765         &jpegd_iommu,
 766         &vpe_iommu,
 767         &mdp0_iommu,
 768         &mdp1_iommu,
 769         &rot_iommu,
 770         &ijpeg_iommu,
 771         &vfe_iommu,
 772         &vcodec_a_iommu,
 773         &vcodec_b_iommu,
 774         &gfx3d_iommu,
 775         &gfx2d0_iommu,
 776         &gfx2d1_iommu,
 777 };
 778
 779 static struct platform_device *msm_iommu_ctx_devs[] = {
 780         &msm_device_jpegd_src_ctx,
 781         &msm_device_jpegd_dst_ctx,
 782         &msm_device_vpe_src_ctx,
 783         &msm_device_vpe_dst_ctx,
 784         &msm_device_mdp_vg1_ctx,
 785         &msm_device_mdp_rgb1_ctx,
 786         &msm_device_mdp_vg2_ctx,
 787         &msm_device_mdp_rgb2_ctx,
 788         &msm_device_rot_src_ctx,
 789         &msm_device_rot_dst_ctx,
 790         &msm_device_ijpeg_src_ctx,
 791         &msm_device_ijpeg_dst_ctx,
 792         &msm_device_vfe_imgwr_ctx,
 793         &msm_device_vfe_misc_ctx,
 794         &msm_device_vcodec_a_stream_ctx,
 795         &msm_device_vcodec_a_mm1_ctx,
 796         &msm_device_vcodec_b_mm2_ctx,
 797         &msm_device_gfx3d_user_ctx,
 798         &msm_device_gfx3d_priv_ctx,
 799         &msm_device_gfx2d0_2d0_ctx,
 800         &msm_device_gfx2d1_2d1_ctx,
 801 };
 802
 803 static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
 804         &jpegd_src_ctx,
 805         &jpegd_dst_ctx,
 806         &vpe_src_ctx,
 807         &vpe_dst_ctx,
 808         &mdp_vg1_ctx,
 809         &mdp_rgb1_ctx,
 810         &mdp_vg2_ctx,
 811         &mdp_rgb2_ctx,
 812         &rot_src_ctx,
 813         &rot_dst_ctx,
 814         &ijpeg_src_ctx,
 815         &ijpeg_dst_ctx,
 816         &vfe_imgwr_ctx,
 817         &vfe_misc_ctx,
 818         &vcodec_a_stream_ctx,
 819         &vcodec_a_mm1_ctx,
 820         &vcodec_b_mm2_ctx,
 821         &gfx3d_user_ctx,
 822         &gfx3d_priv_ctx,
 823         &gfx2d0_2d0_ctx,
 824         &gfx2d1_2d1_ctx,
 825 };
 826
 827 static int __init msm8x60_iommu_init(void)
 828 {
 829         int ret, i;
 830
 831         ret = platform_device_register(&msm_root_iommu_dev);
 832         if (ret != 0) {
 833                 pr_err("Failed to register root IOMMU device!\n");
 834                 goto failure;
 835         }
 836
 837         for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
 838                 ret = platform_device_add_data(msm_iommu_devs[i],
 839                                                msm_iommu_data[i],
 840                                                sizeof(struct msm_iommu_dev));
 841                 if (ret != 0) {
 842                         pr_err("platform_device_add_data failed, "
 843                                "i = %d\n", i);
 844                         goto failure_unwind;
 845                 }
 846
 847                 ret = platform_device_register(msm_iommu_devs[i]);
 848
 849                 if (ret != 0) {
 850                         pr_err("platform_device_register iommu failed, "
 851                                "i = %d\n", i);
 852                         goto failure_unwind;
 853                 }
 854         }
 855
 856         for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
 857                 ret = platform_device_add_data(msm_iommu_ctx_devs[i],
 858                                                msm_iommu_ctx_data[i],
 859                                                sizeof(*msm_iommu_ctx_devs[i]));
 860                 if (ret != 0) {
 861                         pr_err("platform_device_add_data iommu failed, "
 862                                "i = %d\n", i);
 863                         goto failure_unwind2;
 864                 }
 865
 866                 ret = platform_device_register(msm_iommu_ctx_devs[i]);
 867                 if (ret != 0) {
 868                         pr_err("platform_device_register ctx failed, "
 869                                "i = %d\n", i);
 870                         goto failure_unwind2;
 871                 }
 872         }
 873         return 0;
 874
 875 failure_unwind2:
 876         while (--i >= 0)
 877                 platform_device_unregister(msm_iommu_ctx_devs[i]);
 878 failure_unwind:
 879         while (--i >= 0)
 880                 platform_device_unregister(msm_iommu_devs[i]);
 881
 882         platform_device_unregister(&msm_root_iommu_dev);
 883 failure:
 884         return ret;
 885 }
 886
 887 static void __exit msm8x60_iommu_exit(void)
 888 {
 889         int i;
 890
 891         for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
 892                 platform_device_unregister(msm_iommu_ctx_devs[i]);
 893
 894         for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
 895                 platform_device_unregister(msm_iommu_devs[i]);
 896
 897         platform_device_unregister(&msm_root_iommu_dev);
 898 }
 899
 900 subsys_initcall(msm8x60_iommu_init);
 901 module_exit(msm8x60_iommu_exit);
 902
 903 MODULE_LICENSE("GPL v2");
 904 MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");