1 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 #include <linux/kernel.h>
19 #include <linux/platform_device.h>
20 #include <linux/bootmem.h>
21 #include <mach/irqs.h>
22 #include <mach/iommu.h>
24 static struct resource msm_iommu_jpegd_resources[] = {
27 .end = 0x07300000 + SZ_1M - 1,
29 .flags = IORESOURCE_MEM,
32 .name = "nonsecure_irq",
33 .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
34 .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
35 .flags = IORESOURCE_IRQ,
39 .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
40 .end = SMMU_JPEGD_CB_SC_SECURE_IRQ,
41 .flags = IORESOURCE_IRQ,
45 static struct resource msm_iommu_vpe_resources[] = {
48 .end = 0x07400000 + SZ_1M - 1,
50 .flags = IORESOURCE_MEM,
53 .name = "nonsecure_irq",
54 .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
55 .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
56 .flags = IORESOURCE_IRQ,
60 .start = SMMU_VPE_CB_SC_SECURE_IRQ,
61 .end = SMMU_VPE_CB_SC_SECURE_IRQ,
62 .flags = IORESOURCE_IRQ,
66 static struct resource msm_iommu_mdp0_resources[] = {
69 .end = 0x07500000 + SZ_1M - 1,
71 .flags = IORESOURCE_MEM,
74 .name = "nonsecure_irq",
75 .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
76 .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
77 .flags = IORESOURCE_IRQ,
81 .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
82 .end = SMMU_MDP0_CB_SC_SECURE_IRQ,
83 .flags = IORESOURCE_IRQ,
87 static struct resource msm_iommu_mdp1_resources[] = {
90 .end = 0x07600000 + SZ_1M - 1,
92 .flags = IORESOURCE_MEM,
95 .name = "nonsecure_irq",
96 .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
97 .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
98 .flags = IORESOURCE_IRQ,
101 .name = "secure_irq",
102 .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
103 .end = SMMU_MDP1_CB_SC_SECURE_IRQ,
104 .flags = IORESOURCE_IRQ,
108 static struct resource msm_iommu_rot_resources[] = {
111 .end = 0x07700000 + SZ_1M - 1,
113 .flags = IORESOURCE_MEM,
116 .name = "nonsecure_irq",
117 .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
118 .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
119 .flags = IORESOURCE_IRQ,
122 .name = "secure_irq",
123 .start = SMMU_ROT_CB_SC_SECURE_IRQ,
124 .end = SMMU_ROT_CB_SC_SECURE_IRQ,
125 .flags = IORESOURCE_IRQ,
129 static struct resource msm_iommu_ijpeg_resources[] = {
132 .end = 0x07800000 + SZ_1M - 1,
134 .flags = IORESOURCE_MEM,
137 .name = "nonsecure_irq",
138 .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
139 .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
140 .flags = IORESOURCE_IRQ,
143 .name = "secure_irq",
144 .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
145 .end = SMMU_IJPEG_CB_SC_SECURE_IRQ,
146 .flags = IORESOURCE_IRQ,
150 static struct resource msm_iommu_vfe_resources[] = {
153 .end = 0x07900000 + SZ_1M - 1,
155 .flags = IORESOURCE_MEM,
158 .name = "nonsecure_irq",
159 .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
160 .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
161 .flags = IORESOURCE_IRQ,
164 .name = "secure_irq",
165 .start = SMMU_VFE_CB_SC_SECURE_IRQ,
166 .end = SMMU_VFE_CB_SC_SECURE_IRQ,
167 .flags = IORESOURCE_IRQ,
171 static struct resource msm_iommu_vcodec_a_resources[] = {
174 .end = 0x07A00000 + SZ_1M - 1,
176 .flags = IORESOURCE_MEM,
179 .name = "nonsecure_irq",
180 .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
181 .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
182 .flags = IORESOURCE_IRQ,
185 .name = "secure_irq",
186 .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
187 .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
188 .flags = IORESOURCE_IRQ,
192 static struct resource msm_iommu_vcodec_b_resources[] = {
195 .end = 0x07B00000 + SZ_1M - 1,
197 .flags = IORESOURCE_MEM,
200 .name = "nonsecure_irq",
201 .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
202 .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
203 .flags = IORESOURCE_IRQ,
206 .name = "secure_irq",
207 .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
208 .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
209 .flags = IORESOURCE_IRQ,
213 static struct resource msm_iommu_gfx3d_resources[] = {
216 .end = 0x07C00000 + SZ_1M - 1,
218 .flags = IORESOURCE_MEM,
221 .name = "nonsecure_irq",
222 .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
223 .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
224 .flags = IORESOURCE_IRQ,
227 .name = "secure_irq",
228 .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
229 .end = SMMU_GFX3D_CB_SC_SECURE_IRQ,
230 .flags = IORESOURCE_IRQ,
234 static struct resource msm_iommu_gfx2d0_resources[] = {
237 .end = 0x07D00000 + SZ_1M - 1,
239 .flags = IORESOURCE_MEM,
242 .name = "nonsecure_irq",
243 .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
244 .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
245 .flags = IORESOURCE_IRQ,
248 .name = "secure_irq",
249 .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
250 .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
251 .flags = IORESOURCE_IRQ,
255 static struct resource msm_iommu_gfx2d1_resources[] = {
258 .end = 0x07E00000 + SZ_1M - 1,
260 .flags = IORESOURCE_MEM,
263 .name = "nonsecure_irq",
264 .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
265 .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
266 .flags = IORESOURCE_IRQ,
269 .name = "secure_irq",
270 .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
271 .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
272 .flags = IORESOURCE_IRQ,
276 static struct platform_device msm_root_iommu_dev = {
281 static struct msm_iommu_dev jpegd_iommu = {
286 static struct msm_iommu_dev vpe_iommu = {
291 static struct msm_iommu_dev mdp0_iommu = {
296 static struct msm_iommu_dev mdp1_iommu = {
301 static struct msm_iommu_dev rot_iommu = {
306 static struct msm_iommu_dev ijpeg_iommu = {
311 static struct msm_iommu_dev vfe_iommu = {
316 static struct msm_iommu_dev vcodec_a_iommu = {
321 static struct msm_iommu_dev vcodec_b_iommu = {
326 static struct msm_iommu_dev gfx3d_iommu = {
331 static struct msm_iommu_dev gfx2d0_iommu = {
336 static struct msm_iommu_dev gfx2d1_iommu = {
341 static struct platform_device msm_device_iommu_jpegd = {
345 .parent = &msm_root_iommu_dev.dev,
347 .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
348 .resource = msm_iommu_jpegd_resources,
351 static struct platform_device msm_device_iommu_vpe = {
355 .parent = &msm_root_iommu_dev.dev,
357 .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
358 .resource = msm_iommu_vpe_resources,
361 static struct platform_device msm_device_iommu_mdp0 = {
365 .parent = &msm_root_iommu_dev.dev,
367 .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
368 .resource = msm_iommu_mdp0_resources,
371 static struct platform_device msm_device_iommu_mdp1 = {
375 .parent = &msm_root_iommu_dev.dev,
377 .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
378 .resource = msm_iommu_mdp1_resources,
381 static struct platform_device msm_device_iommu_rot = {
385 .parent = &msm_root_iommu_dev.dev,
387 .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
388 .resource = msm_iommu_rot_resources,
391 static struct platform_device msm_device_iommu_ijpeg = {
395 .parent = &msm_root_iommu_dev.dev,
397 .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
398 .resource = msm_iommu_ijpeg_resources,
401 static struct platform_device msm_device_iommu_vfe = {
405 .parent = &msm_root_iommu_dev.dev,
407 .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
408 .resource = msm_iommu_vfe_resources,
411 static struct platform_device msm_device_iommu_vcodec_a = {
415 .parent = &msm_root_iommu_dev.dev,
417 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
418 .resource = msm_iommu_vcodec_a_resources,
421 static struct platform_device msm_device_iommu_vcodec_b = {
425 .parent = &msm_root_iommu_dev.dev,
427 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
428 .resource = msm_iommu_vcodec_b_resources,
431 static struct platform_device msm_device_iommu_gfx3d = {
435 .parent = &msm_root_iommu_dev.dev,
437 .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
438 .resource = msm_iommu_gfx3d_resources,
441 static struct platform_device msm_device_iommu_gfx2d0 = {
445 .parent = &msm_root_iommu_dev.dev,
447 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
448 .resource = msm_iommu_gfx2d0_resources,
451 struct platform_device msm_device_iommu_gfx2d1 = {
455 .parent = &msm_root_iommu_dev.dev,
457 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
458 .resource = msm_iommu_gfx2d1_resources,
461 static struct msm_iommu_ctx_dev jpegd_src_ctx = {
467 static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
473 static struct msm_iommu_ctx_dev vpe_src_ctx = {
479 static struct msm_iommu_ctx_dev vpe_dst_ctx = {
485 static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
491 static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
494 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
497 static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
503 static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
506 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
509 static struct msm_iommu_ctx_dev rot_src_ctx = {
515 static struct msm_iommu_ctx_dev rot_dst_ctx = {
521 static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
527 static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
533 static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
536 .mids = {2, 3, 4, 5, 6, 7, 8, -1}
539 static struct msm_iommu_ctx_dev vfe_misc_ctx = {
542 .mids = {0, 1, 9, -1}
545 static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
546 .name = "vcodec_a_stream",
551 static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
552 .name = "vcodec_a_mm1",
554 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
557 static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
558 .name = "vcodec_b_mm2",
560 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
563 static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
564 .name = "gfx3d_user",
566 .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
569 static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
570 .name = "gfx3d_priv",
572 .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
576 static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
577 .name = "gfx2d0_2d0",
579 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
582 static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
583 .name = "gfx2d1_2d1",
585 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
588 static struct platform_device msm_device_jpegd_src_ctx = {
589 .name = "msm_iommu_ctx",
592 .parent = &msm_device_iommu_jpegd.dev,
596 static struct platform_device msm_device_jpegd_dst_ctx = {
597 .name = "msm_iommu_ctx",
600 .parent = &msm_device_iommu_jpegd.dev,
604 static struct platform_device msm_device_vpe_src_ctx = {
605 .name = "msm_iommu_ctx",
608 .parent = &msm_device_iommu_vpe.dev,
612 static struct platform_device msm_device_vpe_dst_ctx = {
613 .name = "msm_iommu_ctx",
616 .parent = &msm_device_iommu_vpe.dev,
620 static struct platform_device msm_device_mdp_vg1_ctx = {
621 .name = "msm_iommu_ctx",
624 .parent = &msm_device_iommu_mdp0.dev,
628 static struct platform_device msm_device_mdp_rgb1_ctx = {
629 .name = "msm_iommu_ctx",
632 .parent = &msm_device_iommu_mdp0.dev,
636 static struct platform_device msm_device_mdp_vg2_ctx = {
637 .name = "msm_iommu_ctx",
640 .parent = &msm_device_iommu_mdp1.dev,
644 static struct platform_device msm_device_mdp_rgb2_ctx = {
645 .name = "msm_iommu_ctx",
648 .parent = &msm_device_iommu_mdp1.dev,
652 static struct platform_device msm_device_rot_src_ctx = {
653 .name = "msm_iommu_ctx",
656 .parent = &msm_device_iommu_rot.dev,
660 static struct platform_device msm_device_rot_dst_ctx = {
661 .name = "msm_iommu_ctx",
664 .parent = &msm_device_iommu_rot.dev,
668 static struct platform_device msm_device_ijpeg_src_ctx = {
669 .name = "msm_iommu_ctx",
672 .parent = &msm_device_iommu_ijpeg.dev,
676 static struct platform_device msm_device_ijpeg_dst_ctx = {
677 .name = "msm_iommu_ctx",
680 .parent = &msm_device_iommu_ijpeg.dev,
684 static struct platform_device msm_device_vfe_imgwr_ctx = {
685 .name = "msm_iommu_ctx",
688 .parent = &msm_device_iommu_vfe.dev,
692 static struct platform_device msm_device_vfe_misc_ctx = {
693 .name = "msm_iommu_ctx",
696 .parent = &msm_device_iommu_vfe.dev,
700 static struct platform_device msm_device_vcodec_a_stream_ctx = {
701 .name = "msm_iommu_ctx",
704 .parent = &msm_device_iommu_vcodec_a.dev,
708 static struct platform_device msm_device_vcodec_a_mm1_ctx = {
709 .name = "msm_iommu_ctx",
712 .parent = &msm_device_iommu_vcodec_a.dev,
716 static struct platform_device msm_device_vcodec_b_mm2_ctx = {
717 .name = "msm_iommu_ctx",
720 .parent = &msm_device_iommu_vcodec_b.dev,
724 static struct platform_device msm_device_gfx3d_user_ctx = {
725 .name = "msm_iommu_ctx",
728 .parent = &msm_device_iommu_gfx3d.dev,
732 static struct platform_device msm_device_gfx3d_priv_ctx = {
733 .name = "msm_iommu_ctx",
736 .parent = &msm_device_iommu_gfx3d.dev,
740 static struct platform_device msm_device_gfx2d0_2d0_ctx = {
741 .name = "msm_iommu_ctx",
744 .parent = &msm_device_iommu_gfx2d0.dev,
748 static struct platform_device msm_device_gfx2d1_2d1_ctx = {
749 .name = "msm_iommu_ctx",
752 .parent = &msm_device_iommu_gfx2d1.dev,
756 static struct platform_device *msm_iommu_devs[] = {
757 &msm_device_iommu_jpegd,
758 &msm_device_iommu_vpe,
759 &msm_device_iommu_mdp0,
760 &msm_device_iommu_mdp1,
761 &msm_device_iommu_rot,
762 &msm_device_iommu_ijpeg,
763 &msm_device_iommu_vfe,
764 &msm_device_iommu_vcodec_a,
765 &msm_device_iommu_vcodec_b,
766 &msm_device_iommu_gfx3d,
767 &msm_device_iommu_gfx2d0,
768 &msm_device_iommu_gfx2d1,
771 static struct msm_iommu_dev *msm_iommu_data[] = {
786 static struct platform_device *msm_iommu_ctx_devs[] = {
787 &msm_device_jpegd_src_ctx,
788 &msm_device_jpegd_dst_ctx,
789 &msm_device_vpe_src_ctx,
790 &msm_device_vpe_dst_ctx,
791 &msm_device_mdp_vg1_ctx,
792 &msm_device_mdp_rgb1_ctx,
793 &msm_device_mdp_vg2_ctx,
794 &msm_device_mdp_rgb2_ctx,
795 &msm_device_rot_src_ctx,
796 &msm_device_rot_dst_ctx,
797 &msm_device_ijpeg_src_ctx,
798 &msm_device_ijpeg_dst_ctx,
799 &msm_device_vfe_imgwr_ctx,
800 &msm_device_vfe_misc_ctx,
801 &msm_device_vcodec_a_stream_ctx,
802 &msm_device_vcodec_a_mm1_ctx,
803 &msm_device_vcodec_b_mm2_ctx,
804 &msm_device_gfx3d_user_ctx,
805 &msm_device_gfx3d_priv_ctx,
806 &msm_device_gfx2d0_2d0_ctx,
807 &msm_device_gfx2d1_2d1_ctx,
810 static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
825 &vcodec_a_stream_ctx,
834 static int __init msm8x60_iommu_init(void)
838 ret = platform_device_register(&msm_root_iommu_dev);
840 pr_err("Failed to register root IOMMU device!\n");
844 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
845 ret = platform_device_add_data(msm_iommu_devs[i],
847 sizeof(struct msm_iommu_dev));
849 pr_err("platform_device_add_data failed, "
854 ret = platform_device_register(msm_iommu_devs[i]);
857 pr_err("platform_device_register iommu failed, "
863 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
864 ret = platform_device_add_data(msm_iommu_ctx_devs[i],
865 msm_iommu_ctx_data[i],
866 sizeof(*msm_iommu_ctx_devs[i]));
868 pr_err("platform_device_add_data iommu failed, "
870 goto failure_unwind2;
873 ret = platform_device_register(msm_iommu_ctx_devs[i]);
875 pr_err("platform_device_register ctx failed, "
877 goto failure_unwind2;
884 platform_device_unregister(msm_iommu_ctx_devs[i]);
887 platform_device_unregister(msm_iommu_devs[i]);
889 platform_device_unregister(&msm_root_iommu_dev);
894 static void __exit msm8x60_iommu_exit(void)
898 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
899 platform_device_unregister(msm_iommu_ctx_devs[i]);
901 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
902 platform_device_unregister(msm_iommu_devs[i]);
904 platform_device_unregister(&msm_root_iommu_dev);
907 subsys_initcall(msm8x60_iommu_init);
908 module_exit(msm8x60_iommu_exit);
910 MODULE_LICENSE("GPL v2");
911 MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");