2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/delay.h>
17 #include <linux/slab.h>
18 #include <linux/jiffies.h>
19 #include <linux/err.h>
22 #define PLL_NUM_OFFSET 0x10
23 #define PLL_DENOM_OFFSET 0x20
25 #define BM_PLL_POWER (0x1 << 12)
26 #define BM_PLL_LOCK (0x1 << 31)
29 * struct clk_pllv3 - IMX PLL clock version 3
30 * @clk_hw: clock source
31 * @base: base address of PLL registers
32 * @powerup_set: set POWER bit to power up the PLL
33 * @div_mask: mask of divider bits
35 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
36 * is actually a multiplier, and always sits at bit 0.
45 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
47 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
49 unsigned long timeout = jiffies + msecs_to_jiffies(10);
50 u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
52 /* No need to wait for lock when pll is not powered up */
53 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
56 /* Wait for PLL to lock */
58 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
60 if (time_after(jiffies, timeout))
62 usleep_range(50, 500);
65 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
68 static int clk_pllv3_prepare(struct clk_hw *hw)
70 struct clk_pllv3 *pll = to_clk_pllv3(hw);
73 val = readl_relaxed(pll->base);
78 writel_relaxed(val, pll->base);
80 return clk_pllv3_wait_lock(pll);
83 static void clk_pllv3_unprepare(struct clk_hw *hw)
85 struct clk_pllv3 *pll = to_clk_pllv3(hw);
88 val = readl_relaxed(pll->base);
93 writel_relaxed(val, pll->base);
96 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
97 unsigned long parent_rate)
99 struct clk_pllv3 *pll = to_clk_pllv3(hw);
100 u32 div = readl_relaxed(pll->base) & pll->div_mask;
102 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
105 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long *prate)
108 unsigned long parent_rate = *prate;
110 return (rate >= parent_rate * 22) ? parent_rate * 22 :
114 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
115 unsigned long parent_rate)
117 struct clk_pllv3 *pll = to_clk_pllv3(hw);
120 if (rate == parent_rate * 22)
122 else if (rate == parent_rate * 20)
127 val = readl_relaxed(pll->base);
128 val &= ~pll->div_mask;
130 writel_relaxed(val, pll->base);
132 return clk_pllv3_wait_lock(pll);
135 static const struct clk_ops clk_pllv3_ops = {
136 .prepare = clk_pllv3_prepare,
137 .unprepare = clk_pllv3_unprepare,
138 .recalc_rate = clk_pllv3_recalc_rate,
139 .round_rate = clk_pllv3_round_rate,
140 .set_rate = clk_pllv3_set_rate,
143 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
144 unsigned long parent_rate)
146 struct clk_pllv3 *pll = to_clk_pllv3(hw);
147 u32 div = readl_relaxed(pll->base) & pll->div_mask;
149 return parent_rate * div / 2;
152 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
153 unsigned long *prate)
155 unsigned long parent_rate = *prate;
156 unsigned long min_rate = parent_rate * 54 / 2;
157 unsigned long max_rate = parent_rate * 108 / 2;
162 else if (rate < min_rate)
164 div = rate * 2 / parent_rate;
166 return parent_rate * div / 2;
169 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
170 unsigned long parent_rate)
172 struct clk_pllv3 *pll = to_clk_pllv3(hw);
173 unsigned long min_rate = parent_rate * 54 / 2;
174 unsigned long max_rate = parent_rate * 108 / 2;
177 if (rate < min_rate || rate > max_rate)
180 div = rate * 2 / parent_rate;
181 val = readl_relaxed(pll->base);
182 val &= ~pll->div_mask;
184 writel_relaxed(val, pll->base);
186 return clk_pllv3_wait_lock(pll);
189 static const struct clk_ops clk_pllv3_sys_ops = {
190 .prepare = clk_pllv3_prepare,
191 .unprepare = clk_pllv3_unprepare,
192 .recalc_rate = clk_pllv3_sys_recalc_rate,
193 .round_rate = clk_pllv3_sys_round_rate,
194 .set_rate = clk_pllv3_sys_set_rate,
197 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
198 unsigned long parent_rate)
200 struct clk_pllv3 *pll = to_clk_pllv3(hw);
201 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
202 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
203 u32 div = readl_relaxed(pll->base) & pll->div_mask;
205 return (parent_rate * div) + ((parent_rate / mfd) * mfn);
208 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
209 unsigned long *prate)
211 unsigned long parent_rate = *prate;
212 unsigned long min_rate = parent_rate * 27;
213 unsigned long max_rate = parent_rate * 54;
215 u32 mfn, mfd = 1000000;
220 else if (rate < min_rate)
223 div = rate / parent_rate;
224 temp64 = (u64) (rate - div * parent_rate);
226 do_div(temp64, parent_rate);
229 return parent_rate * div + parent_rate / mfd * mfn;
232 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
233 unsigned long parent_rate)
235 struct clk_pllv3 *pll = to_clk_pllv3(hw);
236 unsigned long min_rate = parent_rate * 27;
237 unsigned long max_rate = parent_rate * 54;
239 u32 mfn, mfd = 1000000;
242 if (rate < min_rate || rate > max_rate)
245 div = rate / parent_rate;
246 temp64 = (u64) (rate - div * parent_rate);
248 do_div(temp64, parent_rate);
251 val = readl_relaxed(pll->base);
252 val &= ~pll->div_mask;
254 writel_relaxed(val, pll->base);
255 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
256 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
258 return clk_pllv3_wait_lock(pll);
261 static const struct clk_ops clk_pllv3_av_ops = {
262 .prepare = clk_pllv3_prepare,
263 .unprepare = clk_pllv3_unprepare,
264 .recalc_rate = clk_pllv3_av_recalc_rate,
265 .round_rate = clk_pllv3_av_round_rate,
266 .set_rate = clk_pllv3_av_set_rate,
269 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
270 unsigned long parent_rate)
275 static const struct clk_ops clk_pllv3_enet_ops = {
276 .prepare = clk_pllv3_prepare,
277 .unprepare = clk_pllv3_unprepare,
278 .recalc_rate = clk_pllv3_enet_recalc_rate,
281 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
282 const char *parent_name, void __iomem *base,
285 struct clk_pllv3 *pll;
286 const struct clk_ops *ops;
288 struct clk_init_data init;
290 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
292 return ERR_PTR(-ENOMEM);
296 ops = &clk_pllv3_sys_ops;
299 ops = &clk_pllv3_ops;
300 pll->powerup_set = true;
303 ops = &clk_pllv3_av_ops;
306 ops = &clk_pllv3_enet_ops;
309 ops = &clk_pllv3_ops;
312 pll->div_mask = div_mask;
317 init.parent_names = &parent_name;
318 init.num_parents = 1;
320 pll->hw.init = &init;
322 clk = clk_register(NULL, &pll->hw);