4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/kernel.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/uaccess.h>
20 #include <asm/irq_regs.h>
22 #include <asm/stacktrace.h>
25 armpmu_map_cache_event(const unsigned (*cache_map)
26 [PERF_COUNT_HW_CACHE_MAX]
27 [PERF_COUNT_HW_CACHE_OP_MAX]
28 [PERF_COUNT_HW_CACHE_RESULT_MAX],
31 unsigned int cache_type, cache_op, cache_result, ret;
33 cache_type = (config >> 0) & 0xff;
34 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
37 cache_op = (config >> 8) & 0xff;
38 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
41 cache_result = (config >> 16) & 0xff;
42 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
45 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
47 if (ret == CACHE_OP_UNSUPPORTED)
54 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
56 int mapping = (*event_map)[config];
57 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
61 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
63 return (int)(config & raw_event_mask);
67 armpmu_map_event(struct perf_event *event,
68 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
69 const unsigned (*cache_map)
70 [PERF_COUNT_HW_CACHE_MAX]
71 [PERF_COUNT_HW_CACHE_OP_MAX]
72 [PERF_COUNT_HW_CACHE_RESULT_MAX],
75 u64 config = event->attr.config;
77 switch (event->attr.type) {
78 case PERF_TYPE_HARDWARE:
79 return armpmu_map_hw_event(event_map, config);
80 case PERF_TYPE_HW_CACHE:
81 return armpmu_map_cache_event(cache_map, config);
83 return armpmu_map_raw_event(raw_event_mask, config);
90 armpmu_event_set_period(struct perf_event *event,
91 struct hw_perf_event *hwc,
94 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
95 s64 left = local64_read(&hwc->period_left);
96 s64 period = hwc->sample_period;
99 if (unlikely(left <= -period)) {
101 local64_set(&hwc->period_left, left);
102 hwc->last_period = period;
106 if (unlikely(left <= 0)) {
108 local64_set(&hwc->period_left, left);
109 hwc->last_period = period;
113 if (left > (s64)armpmu->max_period)
114 left = armpmu->max_period;
116 local64_set(&hwc->prev_count, (u64)-left);
118 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
120 perf_event_update_userpage(event);
126 armpmu_event_update(struct perf_event *event,
127 struct hw_perf_event *hwc,
130 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
131 u64 delta, prev_raw_count, new_raw_count;
134 prev_raw_count = local64_read(&hwc->prev_count);
135 new_raw_count = armpmu->read_counter(idx);
137 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
138 new_raw_count) != prev_raw_count)
141 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
143 local64_add(delta, &event->count);
144 local64_sub(delta, &hwc->period_left);
146 return new_raw_count;
150 armpmu_read(struct perf_event *event)
152 struct hw_perf_event *hwc = &event->hw;
154 /* Don't read disabled counters! */
158 armpmu_event_update(event, hwc, hwc->idx);
162 armpmu_stop(struct perf_event *event, int flags)
164 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
165 struct hw_perf_event *hwc = &event->hw;
168 * ARM pmu always has to update the counter, so ignore
169 * PERF_EF_UPDATE, see comments in armpmu_start().
171 if (!(hwc->state & PERF_HES_STOPPED)) {
172 armpmu->disable(hwc, hwc->idx);
173 armpmu_event_update(event, hwc, hwc->idx);
174 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
179 armpmu_start(struct perf_event *event, int flags)
181 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
182 struct hw_perf_event *hwc = &event->hw;
185 * ARM pmu always has to reprogram the period, so ignore
186 * PERF_EF_RELOAD, see the comment below.
188 if (flags & PERF_EF_RELOAD)
189 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
193 * Set the period again. Some counters can't be stopped, so when we
194 * were stopped we simply disabled the IRQ source and the counter
195 * may have been left counting. If we don't do this step then we may
196 * get an interrupt too soon or *way* too late if the overflow has
197 * happened since disabling.
199 armpmu_event_set_period(event, hwc, hwc->idx);
200 armpmu->enable(hwc, hwc->idx);
204 armpmu_del(struct perf_event *event, int flags)
206 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
207 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
208 struct hw_perf_event *hwc = &event->hw;
213 armpmu_stop(event, PERF_EF_UPDATE);
214 hw_events->events[idx] = NULL;
215 clear_bit(idx, hw_events->used_mask);
217 perf_event_update_userpage(event);
221 armpmu_add(struct perf_event *event, int flags)
223 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
224 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
225 struct hw_perf_event *hwc = &event->hw;
229 perf_pmu_disable(event->pmu);
231 /* If we don't have a space for the counter then finish early. */
232 idx = armpmu->get_event_idx(hw_events, hwc);
239 * If there is an event in the counter we are going to use then make
240 * sure it is disabled.
243 armpmu->disable(hwc, idx);
244 hw_events->events[idx] = event;
246 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
247 if (flags & PERF_EF_START)
248 armpmu_start(event, PERF_EF_RELOAD);
250 /* Propagate our changes to the userspace mapping. */
251 perf_event_update_userpage(event);
254 perf_pmu_enable(event->pmu);
259 validate_event(struct pmu_hw_events *hw_events,
260 struct perf_event *event)
262 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
263 struct hw_perf_event fake_event = event->hw;
264 struct pmu *leader_pmu = event->group_leader->pmu;
266 if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
269 return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
273 validate_group(struct perf_event *event)
275 struct perf_event *sibling, *leader = event->group_leader;
276 struct pmu_hw_events fake_pmu;
277 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
280 * Initialise the fake PMU. We only need to populate the
281 * used_mask for the purposes of validation.
283 memset(fake_used_mask, 0, sizeof(fake_used_mask));
284 fake_pmu.used_mask = fake_used_mask;
286 if (!validate_event(&fake_pmu, leader))
289 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
290 if (!validate_event(&fake_pmu, sibling))
294 if (!validate_event(&fake_pmu, event))
300 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
302 struct arm_pmu *armpmu = (struct arm_pmu *) dev;
303 struct platform_device *plat_device = armpmu->plat_device;
304 struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
306 return plat->handle_irq(irq, dev, armpmu->handle_irq);
310 armpmu_release_hardware(struct arm_pmu *armpmu)
313 struct platform_device *pmu_device = armpmu->plat_device;
315 irqs = min(pmu_device->num_resources, num_possible_cpus());
317 for (i = 0; i < irqs; ++i) {
318 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
320 irq = platform_get_irq(pmu_device, i);
322 free_irq(irq, armpmu);
325 pm_runtime_put_sync(&pmu_device->dev);
329 armpmu_reserve_hardware(struct arm_pmu *armpmu)
331 struct arm_pmu_platdata *plat;
332 irq_handler_t handle_irq;
333 int i, err, irq, irqs;
334 struct platform_device *pmu_device = armpmu->plat_device;
339 plat = dev_get_platdata(&pmu_device->dev);
340 if (plat && plat->handle_irq)
341 handle_irq = armpmu_platform_irq;
343 handle_irq = armpmu->handle_irq;
345 irqs = min(pmu_device->num_resources, num_possible_cpus());
347 pr_err("no irqs for PMUs defined\n");
351 pm_runtime_get_sync(&pmu_device->dev);
353 for (i = 0; i < irqs; ++i) {
355 irq = platform_get_irq(pmu_device, i);
360 * If we have a single PMU interrupt that we can't shift,
361 * assume that we're running on a uniprocessor machine and
362 * continue. Otherwise, continue without this interrupt.
364 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
365 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
370 err = request_irq(irq, handle_irq,
371 IRQF_DISABLED | IRQF_NOBALANCING,
374 pr_err("unable to request IRQ%d for ARM PMU counters\n",
376 armpmu_release_hardware(armpmu);
380 cpumask_set_cpu(i, &armpmu->active_irqs);
387 hw_perf_event_destroy(struct perf_event *event)
389 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
390 atomic_t *active_events = &armpmu->active_events;
391 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
393 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
394 armpmu_release_hardware(armpmu);
395 mutex_unlock(pmu_reserve_mutex);
400 event_requires_mode_exclusion(struct perf_event_attr *attr)
402 return attr->exclude_idle || attr->exclude_user ||
403 attr->exclude_kernel || attr->exclude_hv;
407 __hw_perf_event_init(struct perf_event *event)
409 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
410 struct hw_perf_event *hwc = &event->hw;
413 mapping = armpmu->map_event(event);
416 pr_debug("event %x:%llx not supported\n", event->attr.type,
422 * We don't assign an index until we actually place the event onto
423 * hardware. Use -1 to signify that we haven't decided where to put it
424 * yet. For SMP systems, each core has it's own PMU so we can't do any
425 * clever allocation or constraints checking at this point.
428 hwc->config_base = 0;
433 * Check whether we need to exclude the counter from certain modes.
435 if ((!armpmu->set_event_filter ||
436 armpmu->set_event_filter(hwc, &event->attr)) &&
437 event_requires_mode_exclusion(&event->attr)) {
438 pr_debug("ARM performance counters do not support "
444 * Store the event encoding into the config_base field.
446 hwc->config_base |= (unsigned long)mapping;
448 if (!hwc->sample_period) {
450 * For non-sampling runs, limit the sample_period to half
451 * of the counter width. That way, the new counter value
452 * is far less likely to overtake the previous one unless
453 * you have some serious IRQ latency issues.
455 hwc->sample_period = armpmu->max_period >> 1;
456 hwc->last_period = hwc->sample_period;
457 local64_set(&hwc->period_left, hwc->sample_period);
461 if (event->group_leader != event) {
462 err = validate_group(event);
470 static int armpmu_event_init(struct perf_event *event)
472 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
474 atomic_t *active_events = &armpmu->active_events;
476 /* does not support taken branch sampling */
477 if (has_branch_stack(event))
480 if (armpmu->map_event(event) == -ENOENT)
483 event->destroy = hw_perf_event_destroy;
485 if (!atomic_inc_not_zero(active_events)) {
486 mutex_lock(&armpmu->reserve_mutex);
487 if (atomic_read(active_events) == 0)
488 err = armpmu_reserve_hardware(armpmu);
491 atomic_inc(active_events);
492 mutex_unlock(&armpmu->reserve_mutex);
498 err = __hw_perf_event_init(event);
500 hw_perf_event_destroy(event);
505 static void armpmu_enable(struct pmu *pmu)
507 struct arm_pmu *armpmu = to_arm_pmu(pmu);
508 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
509 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
515 static void armpmu_disable(struct pmu *pmu)
517 struct arm_pmu *armpmu = to_arm_pmu(pmu);
521 #ifdef CONFIG_PM_RUNTIME
522 static int armpmu_runtime_resume(struct device *dev)
524 struct arm_pmu_platdata *plat = dev_get_platdata(dev);
526 if (plat && plat->runtime_resume)
527 return plat->runtime_resume(dev);
532 static int armpmu_runtime_suspend(struct device *dev)
534 struct arm_pmu_platdata *plat = dev_get_platdata(dev);
536 if (plat && plat->runtime_suspend)
537 return plat->runtime_suspend(dev);
543 const struct dev_pm_ops armpmu_dev_pm_ops = {
544 SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
547 static void __init armpmu_init(struct arm_pmu *armpmu)
549 atomic_set(&armpmu->active_events, 0);
550 mutex_init(&armpmu->reserve_mutex);
552 armpmu->pmu = (struct pmu) {
553 .pmu_enable = armpmu_enable,
554 .pmu_disable = armpmu_disable,
555 .event_init = armpmu_event_init,
558 .start = armpmu_start,
564 int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
567 pr_info("enabled with %s PMU driver, %d counters available\n",
568 armpmu->name, armpmu->num_events);
569 return perf_pmu_register(&armpmu->pmu, name, type);
573 * Callchain handling code.
577 * The registers we're interested in are at the end of the variable
578 * length saved register structure. The fp points at the end of this
579 * structure so the address of this struct is:
580 * (struct frame_tail *)(xxx->fp)-1
582 * This code has been adapted from the ARM OProfile support.
585 struct frame_tail __user *fp;
588 } __attribute__((packed));
591 * Get the return address for a single stackframe and return a pointer to the
594 static struct frame_tail __user *
595 user_backtrace(struct frame_tail __user *tail,
596 struct perf_callchain_entry *entry)
598 struct frame_tail buftail;
600 /* Also check accessibility of one struct frame_tail beyond */
601 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
603 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
606 perf_callchain_store(entry, buftail.lr);
609 * Frame pointers should strictly progress back up the stack
610 * (towards higher addresses).
612 if (tail + 1 >= buftail.fp)
615 return buftail.fp - 1;
619 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
621 struct frame_tail __user *tail;
624 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
626 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
627 tail && !((unsigned long)tail & 0x3))
628 tail = user_backtrace(tail, entry);
632 * Gets called by walk_stackframe() for every stackframe. This will be called
633 * whist unwinding the stackframe and is like a subroutine return so we use
637 callchain_trace(struct stackframe *fr,
640 struct perf_callchain_entry *entry = data;
641 perf_callchain_store(entry, fr->pc);
646 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
648 struct stackframe fr;
650 fr.fp = regs->ARM_fp;
651 fr.sp = regs->ARM_sp;
652 fr.lr = regs->ARM_lr;
653 fr.pc = regs->ARM_pc;
654 walk_stackframe(&fr, callchain_trace, entry);