arch/arm/boot/dts/sun9i-a80.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 #include "skeleton64.dtsi"
  51
  52 #include <dt-bindings/pinctrl/sun4i-a10.h>
  53
  54 / {
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 serial0 = &uart0;
  59                 serial1 = &uart1;
  60                 serial2 = &uart2;
  61                 serial3 = &uart3;
  62                 serial4 = &uart4;
  63                 serial5 = &uart5;
  64                 serial6 = &r_uart;
  65         };
  66
  67         cpus {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70
  71                 cpu0: cpu@0 {
  72                         compatible = "arm,cortex-a7";
  73                         device_type = "cpu";
  74                         reg = <0x0>;
  75                 };
  76
  77                 cpu1: cpu@1 {
  78                         compatible = "arm,cortex-a7";
  79                         device_type = "cpu";
  80                         reg = <0x1>;
  81                 };
  82
  83                 cpu2: cpu@2 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <0x2>;
  87                 };
  88
  89                 cpu3: cpu@3 {
  90                         compatible = "arm,cortex-a7";
  91                         device_type = "cpu";
  92                         reg = <0x3>;
  93                 };
  94
  95                 cpu4: cpu@100 {
  96                         compatible = "arm,cortex-a15";
  97                         device_type = "cpu";
  98                         reg = <0x100>;
  99                 };
 100
 101                 cpu5: cpu@101 {
 102                         compatible = "arm,cortex-a15";
 103                         device_type = "cpu";
 104                         reg = <0x101>;
 105                 };
 106
 107                 cpu6: cpu@102 {
 108                         compatible = "arm,cortex-a15";
 109                         device_type = "cpu";
 110                         reg = <0x102>;
 111                 };
 112
 113                 cpu7: cpu@103 {
 114                         compatible = "arm,cortex-a15";
 115                         device_type = "cpu";
 116                         reg = <0x103>;
 117                 };
 118         };
 119
 120         memory {
 121                 /* 8GB max. with LPAE */
 122                 reg = <0 0x20000000 0x02 0>;
 123         };
 124
 125         clocks {
 126                 #address-cells = <1>;
 127                 #size-cells = <1>;
 128                 /*
 129                  * map 64 bit address range down to 32 bits,
 130                  * as the peripherals are all under 512MB.
 131                  */
 132                 ranges = <0 0 0 0x20000000>;
 133
 134                 osc24M: osc24M_clk {
 135                         #clock-cells = <0>;
 136                         compatible = "fixed-clock";
 137                         clock-frequency = <24000000>;
 138                         clock-output-names = "osc24M";
 139                 };
 140
 141                 osc32k: osc32k_clk {
 142                         #clock-cells = <0>;
 143                         compatible = "fixed-clock";
 144                         clock-frequency = <32768>;
 145                         clock-output-names = "osc32k";
 146                 };
 147
 148                 pll4: clk@0600000c {
 149                         #clock-cells = <0>;
 150                         compatible = "allwinner,sun9i-a80-pll4-clk";
 151                         reg = <0x0600000c 0x4>;
 152                         clocks = <&osc24M>;
 153                         clock-output-names = "pll4";
 154                 };
 155
 156                 pll12: clk@0600002c {
 157                         #clock-cells = <0>;
 158                         compatible = "allwinner,sun9i-a80-pll4-clk";
 159                         reg = <0x0600002c 0x4>;
 160                         clocks = <&osc24M>;
 161                         clock-output-names = "pll12";
 162                 };
 163
 164                 gt_clk: clk@0600005c {
 165                         #clock-cells = <0>;
 166                         compatible = "allwinner,sun9i-a80-gt-clk";
 167                         reg = <0x0600005c 0x4>;
 168                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 169                         clock-output-names = "gt";
 170                 };
 171
 172                 ahb0: clk@06000060 {
 173                         #clock-cells = <0>;
 174                         compatible = "allwinner,sun9i-a80-ahb-clk";
 175                         reg = <0x06000060 0x4>;
 176                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 177                         clock-output-names = "ahb0";
 178                 };
 179
 180                 ahb1: clk@06000064 {
 181                         #clock-cells = <0>;
 182                         compatible = "allwinner,sun9i-a80-ahb-clk";
 183                         reg = <0x06000064 0x4>;
 184                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 185                         clock-output-names = "ahb1";
 186                 };
 187
 188                 ahb2: clk@06000068 {
 189                         #clock-cells = <0>;
 190                         compatible = "allwinner,sun9i-a80-ahb-clk";
 191                         reg = <0x06000068 0x4>;
 192                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 193                         clock-output-names = "ahb2";
 194                 };
 195
 196                 apb0: clk@06000070 {
 197                         #clock-cells = <0>;
 198                         compatible = "allwinner,sun9i-a80-apb0-clk";
 199                         reg = <0x06000070 0x4>;
 200                         clocks = <&osc24M>, <&pll4>;
 201                         clock-output-names = "apb0";
 202                 };
 203
 204                 apb1: clk@06000074 {
 205                         #clock-cells = <0>;
 206                         compatible = "allwinner,sun9i-a80-apb1-clk";
 207                         reg = <0x06000074 0x4>;
 208                         clocks = <&osc24M>, <&pll4>;
 209                         clock-output-names = "apb1";
 210                 };
 211
 212                 cci400_clk: clk@06000078 {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun9i-a80-gt-clk";
 215                         reg = <0x06000078 0x4>;
 216                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 217                         clock-output-names = "cci400";
 218                 };
 219
 220                 ahb0_gates: clk@06000580 {
 221                         #clock-cells = <1>;
 222                         compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
 223                         reg = <0x06000580 0x4>;
 224                         clocks = <&ahb0>;
 225                         clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
 226                                         "ahb0_ss", "ahb0_sd", "ahb0_nand1",
 227                                         "ahb0_nand0", "ahb0_sdram",
 228                                         "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
 229                                         "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
 230                                         "ahb0_spi3";
 231                 };
 232
 233                 ahb1_gates: clk@06000584 {
 234                         #clock-cells = <1>;
 235                         compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
 236                         reg = <0x06000584 0x4>;
 237                         clocks = <&ahb1>;
 238                         clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
 239                                         "ahb1_gmac", "ahb1_msgbox",
 240                                         "ahb1_spinlock", "ahb1_hstimer",
 241                                         "ahb1_dma";
 242                 };
 243
 244                 ahb2_gates: clk@06000588 {
 245                         #clock-cells = <1>;
 246                         compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
 247                         reg = <0x06000588 0x4>;
 248                         clocks = <&ahb2>;
 249                         clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
 250                                         "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
 251                                         "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
 252                 };
 253
 254                 apb0_gates: clk@06000590 {
 255                         #clock-cells = <1>;
 256                         compatible = "allwinner,sun9i-a80-apb0-gates-clk";
 257                         reg = <0x06000590 0x4>;
 258                         clocks = <&apb0>;
 259                         clock-output-names = "apb0_spdif", "apb0_pio",
 260                                         "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
 261                                         "apb0_lradc", "apb0_gpadc", "apb0_twd",
 262                                         "apb0_cirtx";
 263                 };
 264
 265                 apb1_gates: clk@06000594 {
 266                         #clock-cells = <1>;
 267                         compatible = "allwinner,sun9i-a80-apb1-gates-clk";
 268                         reg = <0x06000594 0x4>;
 269                         clocks = <&apb1>;
 270                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 271                                         "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
 272                                         "apb1_uart0", "apb1_uart1",
 273                                         "apb1_uart2", "apb1_uart3",
 274                                         "apb1_uart4", "apb1_uart5";
 275                 };
 276         };
 277
 278         soc {
 279                 compatible = "simple-bus";
 280                 #address-cells = <1>;
 281                 #size-cells = <1>;
 282                 /*
 283                  * map 64 bit address range down to 32 bits,
 284                  * as the peripherals are all under 512MB.
 285                  */
 286                 ranges = <0 0 0 0x20000000>;
 287
 288                 gic: interrupt-controller@01c41000 {
 289                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 290                         reg = <0x01c41000 0x1000>,
 291                               <0x01c42000 0x1000>,
 292                               <0x01c44000 0x2000>,
 293                               <0x01c46000 0x2000>;
 294                         interrupt-controller;
 295                         #interrupt-cells = <3>;
 296                         interrupts = <1 9 0xf04>;
 297                 };
 298
 299                 ahb0_resets: reset@060005a0 {
 300                         #reset-cells = <1>;
 301                         compatible = "allwinner,sun6i-a31-clock-reset";
 302                         reg = <0x060005a0 0x4>;
 303                 };
 304
 305                 ahb1_resets: reset@060005a4 {
 306                         #reset-cells = <1>;
 307                         compatible = "allwinner,sun6i-a31-clock-reset";
 308                         reg = <0x060005a4 0x4>;
 309                 };
 310
 311                 ahb2_resets: reset@060005a8 {
 312                         #reset-cells = <1>;
 313                         compatible = "allwinner,sun6i-a31-clock-reset";
 314                         reg = <0x060005a8 0x4>;
 315                 };
 316
 317                 apb0_resets: reset@060005b0 {
 318                         #reset-cells = <1>;
 319                         compatible = "allwinner,sun6i-a31-clock-reset";
 320                         reg = <0x060005b0 0x4>;
 321                 };
 322
 323                 apb1_resets: reset@060005b4 {
 324                         #reset-cells = <1>;
 325                         compatible = "allwinner,sun6i-a31-clock-reset";
 326                         reg = <0x060005b4 0x4>;
 327                 };
 328
 329                 timer@06000c00 {
 330                         compatible = "allwinner,sun4i-a10-timer";
 331                         reg = <0x06000c00 0xa0>;
 332                         interrupts = <0 18 4>,
 333                                      <0 19 4>,
 334                                      <0 20 4>,
 335                                      <0 21 4>,
 336                                      <0 22 4>,
 337                                      <0 23 4>;
 338
 339                         clocks = <&osc24M>;
 340                 };
 341
 342                 pio: pinctrl@06000800 {
 343                         compatible = "allwinner,sun9i-a80-pinctrl";
 344                         reg = <0x06000800 0x400>;
 345                         interrupts = <0 11 4>,
 346                                      <0 15 4>,
 347                                      <0 16 4>,
 348                                      <0 17 4>,
 349                                      <0 120 4>;
 350                         clocks = <&apb0_gates 5>;
 351                         gpio-controller;
 352                         interrupt-controller;
 353                         #interrupt-cells = <2>;
 354                         #size-cells = <0>;
 355                         #gpio-cells = <3>;
 356
 357                         i2c3_pins_a: i2c3@0 {
 358                                 allwinner,pins = "PG10", "PG11";
 359                                 allwinner,function = "i2c3";
 360                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 361                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 362                         };
 363
 364                         uart0_pins_a: uart0@0 {
 365                                 allwinner,pins = "PH12", "PH13";
 366                                 allwinner,function = "uart0";
 367                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 368                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 369                         };
 370
 371                         uart4_pins_a: uart4@0 {
 372                                 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
 373                                 allwinner,function = "uart4";
 374                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 375                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 376                         };
 377                 };
 378
 379                 uart0: serial@07000000 {
 380                         compatible = "snps,dw-apb-uart";
 381                         reg = <0x07000000 0x400>;
 382                         interrupts = <0 0 4>;
 383                         reg-shift = <2>;
 384                         reg-io-width = <4>;
 385                         clocks = <&apb1_gates 16>;
 386                         resets = <&apb1_resets 16>;
 387                         status = "disabled";
 388                 };
 389
 390                 uart1: serial@07000400 {
 391                         compatible = "snps,dw-apb-uart";
 392                         reg = <0x07000400 0x400>;
 393                         interrupts = <0 1 4>;
 394                         reg-shift = <2>;
 395                         reg-io-width = <4>;
 396                         clocks = <&apb1_gates 17>;
 397                         resets = <&apb1_resets 17>;
 398                         status = "disabled";
 399                 };
 400
 401                 uart2: serial@07000800 {
 402                         compatible = "snps,dw-apb-uart";
 403                         reg = <0x07000800 0x400>;
 404                         interrupts = <0 2 4>;
 405                         reg-shift = <2>;
 406                         reg-io-width = <4>;
 407                         clocks = <&apb1_gates 18>;
 408                         resets = <&apb1_resets 18>;
 409                         status = "disabled";
 410                 };
 411
 412                 uart3: serial@07000c00 {
 413                         compatible = "snps,dw-apb-uart";
 414                         reg = <0x07000c00 0x400>;
 415                         interrupts = <0 3 4>;
 416                         reg-shift = <2>;
 417                         reg-io-width = <4>;
 418                         clocks = <&apb1_gates 19>;
 419                         resets = <&apb1_resets 19>;
 420                         status = "disabled";
 421                 };
 422
 423                 uart4: serial@07001000 {
 424                         compatible = "snps,dw-apb-uart";
 425                         reg = <0x07001000 0x400>;
 426                         interrupts = <0 4 4>;
 427                         reg-shift = <2>;
 428                         reg-io-width = <4>;
 429                         clocks = <&apb1_gates 20>;
 430                         resets = <&apb1_resets 20>;
 431                         status = "disabled";
 432                 };
 433
 434                 uart5: serial@07001400 {
 435                         compatible = "snps,dw-apb-uart";
 436                         reg = <0x07001400 0x400>;
 437                         interrupts = <0 5 4>;
 438                         reg-shift = <2>;
 439                         reg-io-width = <4>;
 440                         clocks = <&apb1_gates 21>;
 441                         resets = <&apb1_resets 21>;
 442                         status = "disabled";
 443                 };
 444
 445                 i2c0: i2c@07002800 {
 446                         compatible = "allwinner,sun6i-a31-i2c";
 447                         reg = <0x07002800 0x400>;
 448                         interrupts = <0 6 4>;
 449                         clocks = <&apb1_gates 0>;
 450                         resets = <&apb1_resets 0>;
 451                         status = "disabled";
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                 };
 455
 456                 i2c1: i2c@07002c00 {
 457                         compatible = "allwinner,sun6i-a31-i2c";
 458                         reg = <0x07002c00 0x400>;
 459                         interrupts = <0 7 4>;
 460                         clocks = <&apb1_gates 1>;
 461                         resets = <&apb1_resets 1>;
 462                         status = "disabled";
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                 };
 466
 467                 i2c2: i2c@07003000 {
 468                         compatible = "allwinner,sun6i-a31-i2c";
 469                         reg = <0x07003000 0x400>;
 470                         interrupts = <0 8 4>;
 471                         clocks = <&apb1_gates 2>;
 472                         resets = <&apb1_resets 2>;
 473                         status = "disabled";
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                 };
 477
 478                 i2c3: i2c@07003400 {
 479                         compatible = "allwinner,sun6i-a31-i2c";
 480                         reg = <0x07003400 0x400>;
 481                         interrupts = <0 9 4>;
 482                         clocks = <&apb1_gates 3>;
 483                         resets = <&apb1_resets 3>;
 484                         status = "disabled";
 485                         #address-cells = <1>;
 486                         #size-cells = <0>;
 487                 };
 488
 489                 i2c4: i2c@07003800 {
 490                         compatible = "allwinner,sun6i-a31-i2c";
 491                         reg = <0x07003800 0x400>;
 492                         interrupts = <0 10 4>;
 493                         clocks = <&apb1_gates 4>;
 494                         resets = <&apb1_resets 4>;
 495                         status = "disabled";
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                 };
 499
 500                 r_wdt: watchdog@08001000 {
 501                         compatible = "allwinner,sun6i-a31-wdt";
 502                         reg = <0x08001000 0x20>;
 503                         interrupts = <0 36 4>;
 504                 };
 505
 506                 r_uart: serial@08002800 {
 507                         compatible = "snps,dw-apb-uart";
 508                         reg = <0x08002800 0x400>;
 509                         interrupts = <0 38 4>;
 510                         reg-shift = <2>;
 511                         reg-io-width = <4>;
 512                         clocks = <&osc24M>;
 513                         status = "disabled";
 514                 };
 515         };
 516 };