arch/arm/boot/dts/imx51.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx51-pinfunc.h"
  15
  16 / {
  17         aliases {
  18                 serial0 = &uart1;
  19                 serial1 = &uart2;
  20                 serial2 = &uart3;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25         };
  26
  27         tzic: tz-interrupt-controller@e0000000 {
  28                 compatible = "fsl,imx51-tzic", "fsl,tzic";
  29                 interrupt-controller;
  30                 #interrupt-cells = <1>;
  31                 reg = <0xe0000000 0x4000>;
  32         };
  33
  34         clocks {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 ckil {
  39                         compatible = "fsl,imx-ckil", "fixed-clock";
  40                         clock-frequency = <32768>;
  41                 };
  42
  43                 ckih1 {
  44                         compatible = "fsl,imx-ckih1", "fixed-clock";
  45                         clock-frequency = <22579200>;
  46                 };
  47
  48                 ckih2 {
  49                         compatible = "fsl,imx-ckih2", "fixed-clock";
  50                         clock-frequency = <0>;
  51                 };
  52
  53                 osc {
  54                         compatible = "fsl,imx-osc", "fixed-clock";
  55                         clock-frequency = <24000000>;
  56                 };
  57         };
  58
  59         soc {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 compatible = "simple-bus";
  63                 interrupt-parent = <&tzic>;
  64                 ranges;
  65
  66                 ipu: ipu@40000000 {
  67                         #crtc-cells = <1>;
  68                         compatible = "fsl,imx51-ipu";
  69                         reg = <0x40000000 0x20000000>;
  70                         interrupts = <11 10>;
  71                 };
  72
  73                 aips@70000000 { /* AIPS1 */
  74                         compatible = "fsl,aips-bus", "simple-bus";
  75                         #address-cells = <1>;
  76                         #size-cells = <1>;
  77                         reg = <0x70000000 0x10000000>;
  78                         ranges;
  79
  80                         spba@70000000 {
  81                                 compatible = "fsl,spba-bus", "simple-bus";
  82                                 #address-cells = <1>;
  83                                 #size-cells = <1>;
  84                                 reg = <0x70000000 0x40000>;
  85                                 ranges;
  86
  87                                 esdhc1: esdhc@70004000 {
  88                                         compatible = "fsl,imx51-esdhc";
  89                                         reg = <0x70004000 0x4000>;
  90                                         interrupts = <1>;
  91                                         clocks = <&clks 44>, <&clks 0>, <&clks 71>;
  92                                         clock-names = "ipg", "ahb", "per";
  93                                         status = "disabled";
  94                                 };
  95
  96                                 esdhc2: esdhc@70008000 {
  97                                         compatible = "fsl,imx51-esdhc";
  98                                         reg = <0x70008000 0x4000>;
  99                                         interrupts = <2>;
 100                                         clocks = <&clks 45>, <&clks 0>, <&clks 72>;
 101                                         clock-names = "ipg", "ahb", "per";
 102                                         bus-width = <4>;
 103                                         status = "disabled";
 104                                 };
 105
 106                                 uart3: serial@7000c000 {
 107                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 108                                         reg = <0x7000c000 0x4000>;
 109                                         interrupts = <33>;
 110                                         clocks = <&clks 32>, <&clks 33>;
 111                                         clock-names = "ipg", "per";
 112                                         status = "disabled";
 113                                 };
 114
 115                                 ecspi1: ecspi@70010000 {
 116                                         #address-cells = <1>;
 117                                         #size-cells = <0>;
 118                                         compatible = "fsl,imx51-ecspi";
 119                                         reg = <0x70010000 0x4000>;
 120                                         interrupts = <36>;
 121                                         clocks = <&clks 51>, <&clks 52>;
 122                                         clock-names = "ipg", "per";
 123                                         status = "disabled";
 124                                 };
 125
 126                                 ssi2: ssi@70014000 {
 127                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 128                                         reg = <0x70014000 0x4000>;
 129                                         interrupts = <30>;
 130                                         clocks = <&clks 49>;
 131                                         fsl,fifo-depth = <15>;
 132                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 133                                         status = "disabled";
 134                                 };
 135
 136                                 esdhc3: esdhc@70020000 {
 137                                         compatible = "fsl,imx51-esdhc";
 138                                         reg = <0x70020000 0x4000>;
 139                                         interrupts = <3>;
 140                                         clocks = <&clks 46>, <&clks 0>, <&clks 73>;
 141                                         clock-names = "ipg", "ahb", "per";
 142                                         bus-width = <4>;
 143                                         status = "disabled";
 144                                 };
 145
 146                                 esdhc4: esdhc@70024000 {
 147                                         compatible = "fsl,imx51-esdhc";
 148                                         reg = <0x70024000 0x4000>;
 149                                         interrupts = <4>;
 150                                         clocks = <&clks 47>, <&clks 0>, <&clks 74>;
 151                                         clock-names = "ipg", "ahb", "per";
 152                                         bus-width = <4>;
 153                                         status = "disabled";
 154                                 };
 155                         };
 156
 157                         usbotg: usb@73f80000 {
 158                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 159                                 reg = <0x73f80000 0x0200>;
 160                                 interrupts = <18>;
 161                                 status = "disabled";
 162                         };
 163
 164                         usbh1: usb@73f80200 {
 165                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 166                                 reg = <0x73f80200 0x0200>;
 167                                 interrupts = <14>;
 168                                 status = "disabled";
 169                         };
 170
 171                         usbh2: usb@73f80400 {
 172                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 173                                 reg = <0x73f80400 0x0200>;
 174                                 interrupts = <16>;
 175                                 status = "disabled";
 176                         };
 177
 178                         usbh3: usb@73f80600 {
 179                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 180                                 reg = <0x73f80600 0x0200>;
 181                                 interrupts = <17>;
 182                                 status = "disabled";
 183                         };
 184
 185                         gpio1: gpio@73f84000 {
 186                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 187                                 reg = <0x73f84000 0x4000>;
 188                                 interrupts = <50 51>;
 189                                 gpio-controller;
 190                                 #gpio-cells = <2>;
 191                                 interrupt-controller;
 192                                 #interrupt-cells = <2>;
 193                         };
 194
 195                         gpio2: gpio@73f88000 {
 196                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 197                                 reg = <0x73f88000 0x4000>;
 198                                 interrupts = <52 53>;
 199                                 gpio-controller;
 200                                 #gpio-cells = <2>;
 201                                 interrupt-controller;
 202                                 #interrupt-cells = <2>;
 203                         };
 204
 205                         gpio3: gpio@73f8c000 {
 206                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 207                                 reg = <0x73f8c000 0x4000>;
 208                                 interrupts = <54 55>;
 209                                 gpio-controller;
 210                                 #gpio-cells = <2>;
 211                                 interrupt-controller;
 212                                 #interrupt-cells = <2>;
 213                         };
 214
 215                         gpio4: gpio@73f90000 {
 216                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 217                                 reg = <0x73f90000 0x4000>;
 218                                 interrupts = <56 57>;
 219                                 gpio-controller;
 220                                 #gpio-cells = <2>;
 221                                 interrupt-controller;
 222                                 #interrupt-cells = <2>;
 223                         };
 224
 225                         kpp: kpp@73f94000 {
 226                                 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
 227                                 reg = <0x73f94000 0x4000>;
 228                                 interrupts = <60>;
 229                                 clocks = <&clks 0>;
 230                                 status = "disabled";
 231                         };
 232
 233                         wdog1: wdog@73f98000 {
 234                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 235                                 reg = <0x73f98000 0x4000>;
 236                                 interrupts = <58>;
 237                                 clocks = <&clks 0>;
 238                         };
 239
 240                         wdog2: wdog@73f9c000 {
 241                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 242                                 reg = <0x73f9c000 0x4000>;
 243                                 interrupts = <59>;
 244                                 clocks = <&clks 0>;
 245                                 status = "disabled";
 246                         };
 247
 248                         iomuxc: iomuxc@73fa8000 {
 249                                 compatible = "fsl,imx51-iomuxc";
 250                                 reg = <0x73fa8000 0x4000>;
 251
 252                                 audmux {
 253                                         pinctrl_audmux_1: audmuxgrp-1 {
 254                                                 fsl,pins = <
 255                                                         MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
 256                                                         MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
 257                                                         MX51_PAD_AUD3_BB_CK__AUD3_TXC  0x80000000
 258                                                         MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
 259                                                 >;
 260                                         };
 261                                 };
 262
 263                                 fec {
 264                                         pinctrl_fec_1: fecgrp-1 {
 265                                                 fsl,pins = <
 266                                                         MX51_PAD_EIM_EB2__FEC_MDIO         0x80000000
 267                                                         MX51_PAD_EIM_EB3__FEC_RDATA1       0x80000000
 268                                                         MX51_PAD_EIM_CS2__FEC_RDATA2       0x80000000
 269                                                         MX51_PAD_EIM_CS3__FEC_RDATA3       0x80000000
 270                                                         MX51_PAD_EIM_CS4__FEC_RX_ER        0x80000000
 271                                                         MX51_PAD_EIM_CS5__FEC_CRS          0x80000000
 272                                                         MX51_PAD_NANDF_RB2__FEC_COL        0x80000000
 273                                                         MX51_PAD_NANDF_RB3__FEC_RX_CLK     0x80000000
 274                                                         MX51_PAD_NANDF_D9__FEC_RDATA0      0x80000000
 275                                                         MX51_PAD_NANDF_D8__FEC_TDATA0      0x80000000
 276                                                         MX51_PAD_NANDF_CS2__FEC_TX_ER      0x80000000
 277                                                         MX51_PAD_NANDF_CS3__FEC_MDC        0x80000000
 278                                                         MX51_PAD_NANDF_CS4__FEC_TDATA1     0x80000000
 279                                                         MX51_PAD_NANDF_CS5__FEC_TDATA2     0x80000000
 280                                                         MX51_PAD_NANDF_CS6__FEC_TDATA3     0x80000000
 281                                                         MX51_PAD_NANDF_CS7__FEC_TX_EN      0x80000000
 282                                                         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
 283                                                 >;
 284                                         };
 285
 286                                         pinctrl_fec_2: fecgrp-2 {
 287                                                 fsl,pins = <
 288                                                         MX51_PAD_DI_GP3__FEC_TX_ER        0x80000000
 289                                                         MX51_PAD_DI2_PIN4__FEC_CRS        0x80000000
 290                                                         MX51_PAD_DI2_PIN2__FEC_MDC        0x80000000
 291                                                         MX51_PAD_DI2_PIN3__FEC_MDIO       0x80000000
 292                                                         MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
 293                                                         MX51_PAD_DI_GP4__FEC_RDATA2       0x80000000
 294                                                         MX51_PAD_DISP2_DAT0__FEC_RDATA3   0x80000000
 295                                                         MX51_PAD_DISP2_DAT1__FEC_RX_ER    0x80000000
 296                                                         MX51_PAD_DISP2_DAT6__FEC_TDATA1   0x80000000
 297                                                         MX51_PAD_DISP2_DAT7__FEC_TDATA2   0x80000000
 298                                                         MX51_PAD_DISP2_DAT8__FEC_TDATA3   0x80000000
 299                                                         MX51_PAD_DISP2_DAT9__FEC_TX_EN    0x80000000
 300                                                         MX51_PAD_DISP2_DAT10__FEC_COL     0x80000000
 301                                                         MX51_PAD_DISP2_DAT11__FEC_RX_CLK  0x80000000
 302                                                         MX51_PAD_DISP2_DAT12__FEC_RX_DV   0x80000000
 303                                                         MX51_PAD_DISP2_DAT13__FEC_TX_CLK  0x80000000
 304                                                         MX51_PAD_DISP2_DAT14__FEC_RDATA0  0x80000000
 305                                                         MX51_PAD_DISP2_DAT15__FEC_TDATA0  0x80000000
 306                                                 >;
 307                                         };
 308                                 };
 309
 310                                 ecspi1 {
 311                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 312                                                 fsl,pins = <
 313                                                         MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
 314                                                         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
 315                                                         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
 316                                                 >;
 317                                         };
 318                                 };
 319
 320                                 ecspi2 {
 321                                         pinctrl_ecspi2_1: ecspi2grp-1 {
 322                                                 fsl,pins = <
 323                                                         MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
 324                                                         MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
 325                                                         MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
 326                                                 >;
 327                                         };
 328                                 };
 329
 330                                 esdhc1 {
 331                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 332                                                 fsl,pins = <
 333                                                         MX51_PAD_SD1_CMD__SD1_CMD     0x400020d5
 334                                                         MX51_PAD_SD1_CLK__SD1_CLK     0x20d5
 335                                                         MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
 336                                                         MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
 337                                                         MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
 338                                                         MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
 339                                                 >;
 340                                         };
 341                                 };
 342
 343                                 esdhc2 {
 344                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 345                                                 fsl,pins = <
 346                                                         MX51_PAD_SD2_CMD__SD2_CMD     0x400020d5
 347                                                         MX51_PAD_SD2_CLK__SD2_CLK     0x20d5
 348                                                         MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
 349                                                         MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
 350                                                         MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
 351                                                         MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
 352                                                 >;
 353                                         };
 354                                 };
 355
 356                                 i2c2 {
 357                                         pinctrl_i2c2_1: i2c2grp-1 {
 358                                                 fsl,pins = <
 359                                                         MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
 360                                                         MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
 361                                                 >;
 362                                         };
 363
 364                                         pinctrl_i2c2_2: i2c2grp-2 {
 365                                                 fsl,pins = <
 366                                                         MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
 367                                                         MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
 368                                                 >;
 369                                         };
 370                                 };
 371
 372                                 ipu_disp1 {
 373                                         pinctrl_ipu_disp1_1: ipudisp1grp-1 {
 374                                                 fsl,pins = <
 375                                                         MX51_PAD_DISP1_DAT0__DISP1_DAT0   0x5
 376                                                         MX51_PAD_DISP1_DAT1__DISP1_DAT1   0x5
 377                                                         MX51_PAD_DISP1_DAT2__DISP1_DAT2   0x5
 378                                                         MX51_PAD_DISP1_DAT3__DISP1_DAT3   0x5
 379                                                         MX51_PAD_DISP1_DAT4__DISP1_DAT4   0x5
 380                                                         MX51_PAD_DISP1_DAT5__DISP1_DAT5   0x5
 381                                                         MX51_PAD_DISP1_DAT6__DISP1_DAT6   0x5
 382                                                         MX51_PAD_DISP1_DAT7__DISP1_DAT7   0x5
 383                                                         MX51_PAD_DISP1_DAT8__DISP1_DAT8   0x5
 384                                                         MX51_PAD_DISP1_DAT9__DISP1_DAT9   0x5
 385                                                         MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
 386                                                         MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
 387                                                         MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
 388                                                         MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
 389                                                         MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
 390                                                         MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
 391                                                         MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
 392                                                         MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
 393                                                         MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
 394                                                         MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
 395                                                         MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
 396                                                         MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
 397                                                         MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
 398                                                         MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
 399                                                         MX51_PAD_DI1_PIN2__DI1_PIN2       0x5 /* hsync */
 400                                                         MX51_PAD_DI1_PIN3__DI1_PIN3       0x5 /* vsync */
 401                                                 >;
 402                                         };
 403                                 };
 404
 405                                 ipu_disp2 {
 406                                         pinctrl_ipu_disp2_1: ipudisp2grp-1 {
 407                                                 fsl,pins = <
 408                                                         MX51_PAD_DISP2_DAT0__DISP2_DAT0     0x5
 409                                                         MX51_PAD_DISP2_DAT1__DISP2_DAT1     0x5
 410                                                         MX51_PAD_DISP2_DAT2__DISP2_DAT2     0x5
 411                                                         MX51_PAD_DISP2_DAT3__DISP2_DAT3     0x5
 412                                                         MX51_PAD_DISP2_DAT4__DISP2_DAT4     0x5
 413                                                         MX51_PAD_DISP2_DAT5__DISP2_DAT5     0x5
 414                                                         MX51_PAD_DISP2_DAT6__DISP2_DAT6     0x5
 415                                                         MX51_PAD_DISP2_DAT7__DISP2_DAT7     0x5
 416                                                         MX51_PAD_DISP2_DAT8__DISP2_DAT8     0x5
 417                                                         MX51_PAD_DISP2_DAT9__DISP2_DAT9     0x5
 418                                                         MX51_PAD_DISP2_DAT10__DISP2_DAT10   0x5
 419                                                         MX51_PAD_DISP2_DAT11__DISP2_DAT11   0x5
 420                                                         MX51_PAD_DISP2_DAT12__DISP2_DAT12   0x5
 421                                                         MX51_PAD_DISP2_DAT13__DISP2_DAT13   0x5
 422                                                         MX51_PAD_DISP2_DAT14__DISP2_DAT14   0x5
 423                                                         MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5
 424                                                         MX51_PAD_DI2_PIN2__DI2_PIN2         0x5 /* hsync */
 425                                                         MX51_PAD_DI2_PIN3__DI2_PIN3         0x5 /* vsync */
 426                                                         MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
 427                                                         MX51_PAD_DI_GP4__DI2_PIN15          0x5
 428                                                 >;
 429                                         };
 430                                 };
 431
 432                                 uart1 {
 433                                         pinctrl_uart1_1: uart1grp-1 {
 434                                                 fsl,pins = <
 435                                                         MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
 436                                                         MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
 437                                                         MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
 438                                                         MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
 439                                                 >;
 440                                         };
 441                                 };
 442
 443                                 uart2 {
 444                                         pinctrl_uart2_1: uart2grp-1 {
 445                                                 fsl,pins = <
 446                                                         MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
 447                                                         MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
 448                                                 >;
 449                                         };
 450                                 };
 451
 452                                 uart3 {
 453                                         pinctrl_uart3_1: uart3grp-1 {
 454                                                 fsl,pins = <
 455                                                         MX51_PAD_EIM_D25__UART3_RXD 0x1c5
 456                                                         MX51_PAD_EIM_D26__UART3_TXD 0x1c5
 457                                                         MX51_PAD_EIM_D27__UART3_RTS 0x1c5
 458                                                         MX51_PAD_EIM_D24__UART3_CTS 0x1c5
 459                                                 >;
 460                                         };
 461
 462                                         pinctrl_uart3_2: uart3grp-2 {
 463                                                 fsl,pins = <
 464                                                         MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
 465                                                         MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
 466                                                 >;
 467                                         };
 468                                 };
 469
 470                                 kpp {
 471                                         pinctrl_kpp_1: kppgrp-1 {
 472                                                 fsl,pins = <
 473                                                         MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
 474                                                         MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
 475                                                         MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
 476                                                         MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
 477                                                         MX51_PAD_KEY_COL0__KEY_COL0 0xe8
 478                                                         MX51_PAD_KEY_COL1__KEY_COL1 0xe8
 479                                                         MX51_PAD_KEY_COL2__KEY_COL2 0xe8
 480                                                         MX51_PAD_KEY_COL3__KEY_COL3 0xe8
 481                                                 >;
 482                                         };
 483                                 };
 484                         };
 485
 486                         pwm1: pwm@73fb4000 {
 487                                 #pwm-cells = <2>;
 488                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 489                                 reg = <0x73fb4000 0x4000>;
 490                                 clocks = <&clks 37>, <&clks 38>;
 491                                 clock-names = "ipg", "per";
 492                                 interrupts = <61>;
 493                         };
 494
 495                         pwm2: pwm@73fb8000 {
 496                                 #pwm-cells = <2>;
 497                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 498                                 reg = <0x73fb8000 0x4000>;
 499                                 clocks = <&clks 39>, <&clks 40>;
 500                                 clock-names = "ipg", "per";
 501                                 interrupts = <94>;
 502                         };
 503
 504                         uart1: serial@73fbc000 {
 505                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 506                                 reg = <0x73fbc000 0x4000>;
 507                                 interrupts = <31>;
 508                                 clocks = <&clks 28>, <&clks 29>;
 509                                 clock-names = "ipg", "per";
 510                                 status = "disabled";
 511                         };
 512
 513                         uart2: serial@73fc0000 {
 514                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 515                                 reg = <0x73fc0000 0x4000>;
 516                                 interrupts = <32>;
 517                                 clocks = <&clks 30>, <&clks 31>;
 518                                 clock-names = "ipg", "per";
 519                                 status = "disabled";
 520                         };
 521
 522                         clks: ccm@73fd4000{
 523                                 compatible = "fsl,imx51-ccm";
 524                                 reg = <0x73fd4000 0x4000>;
 525                                 interrupts = <0 71 0x04 0 72 0x04>;
 526                                 #clock-cells = <1>;
 527                         };
 528                 };
 529
 530                 aips@80000000 { /* AIPS2 */
 531                         compatible = "fsl,aips-bus", "simple-bus";
 532                         #address-cells = <1>;
 533                         #size-cells = <1>;
 534                         reg = <0x80000000 0x10000000>;
 535                         ranges;
 536
 537                         ecspi2: ecspi@83fac000 {
 538                                 #address-cells = <1>;
 539                                 #size-cells = <0>;
 540                                 compatible = "fsl,imx51-ecspi";
 541                                 reg = <0x83fac000 0x4000>;
 542                                 interrupts = <37>;
 543                                 clocks = <&clks 53>, <&clks 54>;
 544                                 clock-names = "ipg", "per";
 545                                 status = "disabled";
 546                         };
 547
 548                         sdma: sdma@83fb0000 {
 549                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 550                                 reg = <0x83fb0000 0x4000>;
 551                                 interrupts = <6>;
 552                                 clocks = <&clks 56>, <&clks 56>;
 553                                 clock-names = "ipg", "ahb";
 554                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
 555                         };
 556
 557                         cspi: cspi@83fc0000 {
 558                                 #address-cells = <1>;
 559                                 #size-cells = <0>;
 560                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 561                                 reg = <0x83fc0000 0x4000>;
 562                                 interrupts = <38>;
 563                                 clocks = <&clks 55>, <&clks 0>;
 564                                 clock-names = "ipg", "per";
 565                                 status = "disabled";
 566                         };
 567
 568                         i2c2: i2c@83fc4000 {
 569                                 #address-cells = <1>;
 570                                 #size-cells = <0>;
 571                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 572                                 reg = <0x83fc4000 0x4000>;
 573                                 interrupts = <63>;
 574                                 clocks = <&clks 35>;
 575                                 status = "disabled";
 576                         };
 577
 578                         i2c1: i2c@83fc8000 {
 579                                 #address-cells = <1>;
 580                                 #size-cells = <0>;
 581                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 582                                 reg = <0x83fc8000 0x4000>;
 583                                 interrupts = <62>;
 584                                 clocks = <&clks 34>;
 585                                 status = "disabled";
 586                         };
 587
 588                         ssi1: ssi@83fcc000 {
 589                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 590                                 reg = <0x83fcc000 0x4000>;
 591                                 interrupts = <29>;
 592                                 clocks = <&clks 48>;
 593                                 fsl,fifo-depth = <15>;
 594                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 595                                 status = "disabled";
 596                         };
 597
 598                         audmux: audmux@83fd0000 {
 599                                 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
 600                                 reg = <0x83fd0000 0x4000>;
 601                                 status = "disabled";
 602                         };
 603
 604                         nfc: nand@83fdb000 {
 605                                 compatible = "fsl,imx51-nand";
 606                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
 607                                 interrupts = <8>;
 608                                 clocks = <&clks 60>;
 609                                 status = "disabled";
 610                         };
 611
 612                         ssi3: ssi@83fe8000 {
 613                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 614                                 reg = <0x83fe8000 0x4000>;
 615                                 interrupts = <96>;
 616                                 clocks = <&clks 50>;
 617                                 fsl,fifo-depth = <15>;
 618                                 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
 619                                 status = "disabled";
 620                         };
 621
 622                         fec: ethernet@83fec000 {
 623                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
 624                                 reg = <0x83fec000 0x4000>;
 625                                 interrupts = <87>;
 626                                 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
 627                                 clock-names = "ipg", "ahb", "ptp";
 628                                 status = "disabled";
 629                         };
 630                 };
 631         };
 632 };