5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory" if MMU
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 default DRAM_BASE if !MMU
227 Please provide the physical address corresponding to the
228 location of main memory in your system.
234 source "init/Kconfig"
236 source "kernel/Kconfig.freezer"
241 bool "MMU-based Paged Memory Management Support"
244 Select if you want MMU-based virtualised addressing space
245 support by paged memory management. If unsure, say 'Y'.
248 # The "ARM system type" choice list is ordered alphabetically by option
249 # text. Please add new entries in the option alphabetic order.
252 prompt "ARM system type"
253 default ARCH_VERSATILE
255 config ARCH_INTEGRATOR
256 bool "ARM Ltd. Integrator family"
258 select ARCH_HAS_CPUFREQ
260 select HAVE_MACH_CLKDEV
262 select GENERIC_CLOCKEVENTS
263 select PLAT_VERSATILE
264 select PLAT_VERSATILE_FPGA_IRQ
265 select NEED_MACH_MEMORY_H
267 Support for ARM's Integrator platform.
270 bool "ARM Ltd. RealView family"
273 select HAVE_MACH_CLKDEV
275 select GENERIC_CLOCKEVENTS
276 select ARCH_WANT_OPTIONAL_GPIOLIB
277 select PLAT_VERSATILE
278 select PLAT_VERSATILE_CLCD
279 select ARM_TIMER_SP804
280 select GPIO_PL061 if GPIOLIB
281 select NEED_MACH_MEMORY_H
283 This enables support for ARM Ltd RealView boards.
285 config ARCH_VERSATILE
286 bool "ARM Ltd. Versatile family"
290 select HAVE_MACH_CLKDEV
292 select GENERIC_CLOCKEVENTS
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 select PLAT_VERSATILE_FPGA_IRQ
297 select ARM_TIMER_SP804
299 This enables support for ARM Ltd Versatile board.
302 bool "ARM Ltd. Versatile Express family"
303 select ARCH_WANT_OPTIONAL_GPIOLIB
305 select ARM_TIMER_SP804
307 select HAVE_MACH_CLKDEV
308 select GENERIC_CLOCKEVENTS
310 select HAVE_PATA_PLATFORM
312 select PLAT_VERSATILE
313 select PLAT_VERSATILE_CLCD
315 This enables support for the ARM Ltd Versatile Express boards.
319 select ARCH_REQUIRE_GPIOLIB
323 This enables support for systems based on the Atmel AT91RM9200,
324 AT91SAM9 and AT91CAP9 processors.
327 bool "Broadcom BCMRING"
331 select ARM_TIMER_SP804
333 select GENERIC_CLOCKEVENTS
334 select ARCH_WANT_OPTIONAL_GPIOLIB
336 Support for Broadcom's BCMRing platform.
339 bool "Calxeda Highbank-based"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select ARM_TIMER_SP804
346 select GENERIC_CLOCKEVENTS
350 Support for the Calxeda Highbank SoC based boards.
353 bool "Cirrus Logic CLPS711x/EP721x-based"
355 select ARCH_USES_GETTIMEOFFSET
356 select NEED_MACH_MEMORY_H
358 Support for Cirrus Logic 711x/721x based boards.
361 bool "Cavium Networks CNS3XXX family"
363 select GENERIC_CLOCKEVENTS
365 select MIGHT_HAVE_PCI
366 select PCI_DOMAINS if PCI
368 Support for Cavium Networks CNS3XXX platform.
371 bool "Cortina Systems Gemini"
373 select ARCH_REQUIRE_GPIOLIB
374 select ARCH_USES_GETTIMEOFFSET
376 Support for the Cortina Systems Gemini family SoCs
379 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
382 select GENERIC_CLOCKEVENTS
384 select GENERIC_IRQ_CHIP
388 Support for CSR SiRFSoC ARM Cortex A9 Platform
395 select ARCH_USES_GETTIMEOFFSET
396 select NEED_MACH_MEMORY_H
398 This is an evaluation board for the StrongARM processor available
399 from Digital. It has limited hardware on-board, including an
400 Ethernet interface, two PCMCIA sockets, two serial ports and a
409 select ARCH_REQUIRE_GPIOLIB
410 select ARCH_HAS_HOLES_MEMORYMODEL
411 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_MEMORY_H
414 This enables support for the Cirrus EP93xx series of CPUs.
416 config ARCH_FOOTBRIDGE
420 select GENERIC_CLOCKEVENTS
422 select NEED_MACH_MEMORY_H
424 Support for systems based on the DC21285 companion chip
425 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
428 bool "Freescale MXC/iMX-based"
429 select GENERIC_CLOCKEVENTS
430 select ARCH_REQUIRE_GPIOLIB
433 select GENERIC_IRQ_CHIP
434 select HAVE_SCHED_CLOCK
435 select MULTI_IRQ_HANDLER
437 Support for Freescale MXC/iMX-based family of processors
440 bool "Freescale MXS-based"
441 select GENERIC_CLOCKEVENTS
442 select ARCH_REQUIRE_GPIOLIB
446 Support for Freescale MXS-based family of processors
449 bool "Hilscher NetX based"
453 select GENERIC_CLOCKEVENTS
455 This enables support for systems based on the Hilscher NetX Soc
458 bool "Hynix HMS720x-based"
461 select ARCH_USES_GETTIMEOFFSET
463 This enables support for systems based on the Hynix HMS720x
471 select ARCH_SUPPORTS_MSI
473 select NEED_MACH_MEMORY_H
475 Support for Intel's IOP13XX (XScale) family of processors.
483 select ARCH_REQUIRE_GPIOLIB
485 Support for Intel's 80219 and IOP32X (XScale) family of
494 select ARCH_REQUIRE_GPIOLIB
496 Support for Intel's IOP33X (XScale) family of processors.
503 select ARCH_USES_GETTIMEOFFSET
504 select NEED_MACH_MEMORY_H
506 Support for Intel's IXP23xx (XScale) family of processors.
509 bool "IXP2400/2800-based"
513 select ARCH_USES_GETTIMEOFFSET
514 select NEED_MACH_MEMORY_H
516 Support for Intel's IXP2400/2800 (XScale) family of processors.
523 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
525 select HAVE_SCHED_CLOCK
526 select MIGHT_HAVE_PCI
527 select DMABOUNCE if PCI
529 Support for Intel's IXP4XX (XScale) family of processors.
535 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
539 Support for the Marvell Dove SoC 88AP510
542 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
550 Support for the following Marvell Kirkwood series SoCs:
551 88F6180, 88F6192 and 88F6281.
557 select ARCH_REQUIRE_GPIOLIB
560 select USB_ARCH_HAS_OHCI
562 select GENERIC_CLOCKEVENTS
564 Support for the NXP LPC32XX family of processors
567 bool "Marvell MV78xx0"
570 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_CLOCKEVENTS
574 Support for the following Marvell MV78xx0 series SoCs:
582 select ARCH_REQUIRE_GPIOLIB
583 select GENERIC_CLOCKEVENTS
586 Support for the following Marvell Orion 5x series SoCs:
587 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
588 Orion-2 (5281), Orion-1-90 (6183).
591 bool "Marvell PXA168/910/MMP2"
593 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS
596 select HAVE_SCHED_CLOCK
600 select GENERIC_ALLOCATOR
602 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
605 bool "Micrel/Kendin KS8695"
607 select ARCH_REQUIRE_GPIOLIB
608 select ARCH_USES_GETTIMEOFFSET
609 select NEED_MACH_MEMORY_H
611 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
612 System-on-Chip devices.
615 bool "Nuvoton W90X900 CPU"
617 select ARCH_REQUIRE_GPIOLIB
620 select GENERIC_CLOCKEVENTS
622 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
623 At present, the w90x900 has been renamed nuc900, regarding
624 the ARM series product line, you can login the following
625 link address to know more.
627 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
628 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
634 select GENERIC_CLOCKEVENTS
637 select HAVE_SCHED_CLOCK
638 select ARCH_HAS_CPUFREQ
640 This enables support for NVIDIA Tegra based systems (Tegra APX,
641 Tegra 6xx and Tegra 2 series).
643 config ARCH_PICOXCELL
644 bool "Picochip picoXcell"
645 select ARCH_REQUIRE_GPIOLIB
646 select ARM_PATCH_PHYS_VIRT
650 select GENERIC_CLOCKEVENTS
652 select HAVE_SCHED_CLOCK
657 This enables support for systems based on the Picochip picoXcell
658 family of Femtocell devices. The picoxcell support requires device tree
662 bool "Philips Nexperia PNX4008 Mobile"
665 select ARCH_USES_GETTIMEOFFSET
667 This enables support for Philips PNX4008 mobile platform.
670 bool "PXA2xx/PXA3xx-based"
673 select ARCH_HAS_CPUFREQ
676 select ARCH_REQUIRE_GPIOLIB
677 select GENERIC_CLOCKEVENTS
678 select HAVE_SCHED_CLOCK
683 select MULTI_IRQ_HANDLER
684 select ARM_CPU_SUSPEND if PM
687 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
692 select GENERIC_CLOCKEVENTS
693 select ARCH_REQUIRE_GPIOLIB
696 Support for Qualcomm MSM/QSD based systems. This runs on the
697 apps processor of the MSM/QSD and depends on a shared memory
698 interface to the modem processor which runs the baseband
699 stack and controls some vital subsystems
700 (clock and power control, etc).
703 bool "Renesas SH-Mobile / R-Mobile"
706 select HAVE_MACH_CLKDEV
707 select GENERIC_CLOCKEVENTS
710 select MULTI_IRQ_HANDLER
711 select PM_GENERIC_DOMAINS if PM
712 select NEED_MACH_MEMORY_H
714 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
721 select ARCH_MAY_HAVE_PC_FDC
722 select HAVE_PATA_PLATFORM
725 select ARCH_SPARSEMEM_ENABLE
726 select ARCH_USES_GETTIMEOFFSET
728 select NEED_MACH_MEMORY_H
730 On the Acorn Risc-PC, Linux can support the internal IDE disk and
731 CD-ROM interface, serial and parallel port, and the floppy drive.
738 select ARCH_SPARSEMEM_ENABLE
740 select ARCH_HAS_CPUFREQ
742 select GENERIC_CLOCKEVENTS
744 select HAVE_SCHED_CLOCK
746 select ARCH_REQUIRE_GPIOLIB
748 select NEED_MACH_MEMORY_H
750 Support for StrongARM 11x0 based boards.
753 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
755 select ARCH_HAS_CPUFREQ
758 select ARCH_USES_GETTIMEOFFSET
759 select HAVE_S3C2410_I2C if I2C
761 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
762 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
763 the Samsung SMDK2410 development board (and derivatives).
765 Note, the S3C2416 and the S3C2450 are so close that they even share
766 the same SoC ID code. This means that there is no separate machine
767 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
770 bool "Samsung S3C64XX"
778 select ARCH_USES_GETTIMEOFFSET
779 select ARCH_HAS_CPUFREQ
780 select ARCH_REQUIRE_GPIOLIB
781 select SAMSUNG_CLKSRC
782 select SAMSUNG_IRQ_VIC_TIMER
783 select S3C_GPIO_TRACK
785 select USB_ARCH_HAS_OHCI
786 select SAMSUNG_GPIOLIB_4BIT
787 select HAVE_S3C2410_I2C if I2C
788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 Samsung S3C64XX series based systems
793 bool "Samsung S5P6440 S5P6450"
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 select GENERIC_CLOCKEVENTS
801 select HAVE_SCHED_CLOCK
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C_RTC if RTC_CLASS
805 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
809 bool "Samsung S5PC100"
814 select ARM_L1_CACHE_SHIFT_6
815 select ARCH_USES_GETTIMEOFFSET
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C_RTC if RTC_CLASS
818 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 Samsung S5PC100 series based systems
823 bool "Samsung S5PV210/S5PC110"
825 select ARCH_SPARSEMEM_ENABLE
826 select ARCH_HAS_HOLES_MEMORYMODEL
831 select ARM_L1_CACHE_SHIFT_6
832 select ARCH_HAS_CPUFREQ
833 select GENERIC_CLOCKEVENTS
834 select HAVE_SCHED_CLOCK
835 select HAVE_S3C2410_I2C if I2C
836 select HAVE_S3C_RTC if RTC_CLASS
837 select HAVE_S3C2410_WATCHDOG if WATCHDOG
838 select NEED_MACH_MEMORY_H
840 Samsung S5PV210/S5PC110 series based systems
843 bool "SAMSUNG EXYNOS"
845 select ARCH_SPARSEMEM_ENABLE
846 select ARCH_HAS_HOLES_MEMORYMODEL
850 select ARCH_HAS_CPUFREQ
851 select GENERIC_CLOCKEVENTS
852 select HAVE_S3C_RTC if RTC_CLASS
853 select HAVE_S3C2410_I2C if I2C
854 select HAVE_S3C2410_WATCHDOG if WATCHDOG
855 select NEED_MACH_MEMORY_H
857 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
866 select ARCH_USES_GETTIMEOFFSET
867 select NEED_MACH_MEMORY_H
869 Support for the StrongARM based Digital DNARD machine, also known
870 as "Shark" (<http://www.shark-linux.de/shark.html>).
873 bool "Telechips TCC ARM926-based systems"
878 select GENERIC_CLOCKEVENTS
880 Support for Telechips TCC ARM926-based systems.
883 bool "ST-Ericsson U300 Series"
887 select HAVE_SCHED_CLOCK
890 select ARM_PATCH_PHYS_VIRT
892 select GENERIC_CLOCKEVENTS
894 select HAVE_MACH_CLKDEV
896 select ARCH_REQUIRE_GPIOLIB
897 select NEED_MACH_MEMORY_H
899 Support for ST-Ericsson U300 series mobile platforms.
902 bool "ST-Ericsson U8500 Series"
905 select GENERIC_CLOCKEVENTS
907 select ARCH_REQUIRE_GPIOLIB
908 select ARCH_HAS_CPUFREQ
910 Support for ST-Ericsson's Ux500 architecture
913 bool "STMicroelectronics Nomadik"
918 select GENERIC_CLOCKEVENTS
919 select ARCH_REQUIRE_GPIOLIB
921 Support for the Nomadik platform by ST-Ericsson
925 select GENERIC_CLOCKEVENTS
926 select ARCH_REQUIRE_GPIOLIB
930 select GENERIC_ALLOCATOR
931 select GENERIC_IRQ_CHIP
932 select ARCH_HAS_HOLES_MEMORYMODEL
934 Support for TI's DaVinci platform.
939 select ARCH_REQUIRE_GPIOLIB
940 select ARCH_HAS_CPUFREQ
942 select GENERIC_CLOCKEVENTS
943 select HAVE_SCHED_CLOCK
944 select ARCH_HAS_HOLES_MEMORYMODEL
946 Support for TI's OMAP platform (OMAP1/2/3/4).
951 select ARCH_REQUIRE_GPIOLIB
954 select GENERIC_CLOCKEVENTS
957 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
960 bool "VIA/WonderMedia 85xx"
963 select ARCH_HAS_CPUFREQ
964 select GENERIC_CLOCKEVENTS
965 select ARCH_REQUIRE_GPIOLIB
968 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
971 bool "Xilinx Zynq ARM Cortex A9 Platform"
973 select GENERIC_CLOCKEVENTS
980 Support for Xilinx Zynq ARM Cortex A9 Platform
984 # This is sorted alphabetically by mach-* pathname. However, plat-*
985 # Kconfigs may be included either alphabetically (according to the
986 # plat- suffix) or along side the corresponding mach-* source.
988 source "arch/arm/mach-at91/Kconfig"
990 source "arch/arm/mach-bcmring/Kconfig"
992 source "arch/arm/mach-clps711x/Kconfig"
994 source "arch/arm/mach-cns3xxx/Kconfig"
996 source "arch/arm/mach-davinci/Kconfig"
998 source "arch/arm/mach-dove/Kconfig"
1000 source "arch/arm/mach-ep93xx/Kconfig"
1002 source "arch/arm/mach-footbridge/Kconfig"
1004 source "arch/arm/mach-gemini/Kconfig"
1006 source "arch/arm/mach-h720x/Kconfig"
1008 source "arch/arm/mach-integrator/Kconfig"
1010 source "arch/arm/mach-iop32x/Kconfig"
1012 source "arch/arm/mach-iop33x/Kconfig"
1014 source "arch/arm/mach-iop13xx/Kconfig"
1016 source "arch/arm/mach-ixp4xx/Kconfig"
1018 source "arch/arm/mach-ixp2000/Kconfig"
1020 source "arch/arm/mach-ixp23xx/Kconfig"
1022 source "arch/arm/mach-kirkwood/Kconfig"
1024 source "arch/arm/mach-ks8695/Kconfig"
1026 source "arch/arm/mach-lpc32xx/Kconfig"
1028 source "arch/arm/mach-msm/Kconfig"
1030 source "arch/arm/mach-mv78xx0/Kconfig"
1032 source "arch/arm/plat-mxc/Kconfig"
1034 source "arch/arm/mach-mxs/Kconfig"
1036 source "arch/arm/mach-netx/Kconfig"
1038 source "arch/arm/mach-nomadik/Kconfig"
1039 source "arch/arm/plat-nomadik/Kconfig"
1041 source "arch/arm/plat-omap/Kconfig"
1043 source "arch/arm/mach-omap1/Kconfig"
1045 source "arch/arm/mach-omap2/Kconfig"
1047 source "arch/arm/mach-orion5x/Kconfig"
1049 source "arch/arm/mach-pxa/Kconfig"
1050 source "arch/arm/plat-pxa/Kconfig"
1052 source "arch/arm/mach-mmp/Kconfig"
1054 source "arch/arm/mach-realview/Kconfig"
1056 source "arch/arm/mach-sa1100/Kconfig"
1058 source "arch/arm/plat-samsung/Kconfig"
1059 source "arch/arm/plat-s3c24xx/Kconfig"
1060 source "arch/arm/plat-s5p/Kconfig"
1062 source "arch/arm/plat-spear/Kconfig"
1064 source "arch/arm/plat-tcc/Kconfig"
1067 source "arch/arm/mach-s3c2410/Kconfig"
1068 source "arch/arm/mach-s3c2412/Kconfig"
1069 source "arch/arm/mach-s3c2416/Kconfig"
1070 source "arch/arm/mach-s3c2440/Kconfig"
1071 source "arch/arm/mach-s3c2443/Kconfig"
1075 source "arch/arm/mach-s3c64xx/Kconfig"
1078 source "arch/arm/mach-s5p64x0/Kconfig"
1080 source "arch/arm/mach-s5pc100/Kconfig"
1082 source "arch/arm/mach-s5pv210/Kconfig"
1084 source "arch/arm/mach-exynos/Kconfig"
1086 source "arch/arm/mach-shmobile/Kconfig"
1088 source "arch/arm/mach-tegra/Kconfig"
1090 source "arch/arm/mach-u300/Kconfig"
1092 source "arch/arm/mach-ux500/Kconfig"
1094 source "arch/arm/mach-versatile/Kconfig"
1096 source "arch/arm/mach-vexpress/Kconfig"
1097 source "arch/arm/plat-versatile/Kconfig"
1099 source "arch/arm/mach-vt8500/Kconfig"
1101 source "arch/arm/mach-w90x900/Kconfig"
1103 # Definitions to make life easier
1109 select GENERIC_CLOCKEVENTS
1110 select HAVE_SCHED_CLOCK
1115 select GENERIC_IRQ_CHIP
1116 select HAVE_SCHED_CLOCK
1121 config PLAT_VERSATILE
1124 config ARM_TIMER_SP804
1128 source arch/arm/mm/Kconfig
1131 bool "Enable iWMMXt support"
1132 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1133 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1135 Enable support for iWMMXt context switching at run time if
1136 running on a CPU that supports it.
1138 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1141 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1145 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1146 (!ARCH_OMAP3 || OMAP3_EMU)
1150 config MULTI_IRQ_HANDLER
1153 Allow each machine to specify it's own IRQ handler at run time.
1156 source "arch/arm/Kconfig-nommu"
1159 config ARM_ERRATA_326103
1160 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1163 Executing a SWP instruction to read-only memory does not set bit 11
1164 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1165 treat the access as a read, preventing a COW from occurring and
1166 causing the faulting task to livelock.
1168 config ARM_ERRATA_411920
1169 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1170 depends on CPU_V6 || CPU_V6K
1172 Invalidation of the Instruction Cache operation can
1173 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1174 It does not affect the MPCore. This option enables the ARM Ltd.
1175 recommended workaround.
1177 config ARM_ERRATA_430973
1178 bool "ARM errata: Stale prediction on replaced interworking branch"
1181 This option enables the workaround for the 430973 Cortex-A8
1182 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1183 interworking branch is replaced with another code sequence at the
1184 same virtual address, whether due to self-modifying code or virtual
1185 to physical address re-mapping, Cortex-A8 does not recover from the
1186 stale interworking branch prediction. This results in Cortex-A8
1187 executing the new code sequence in the incorrect ARM or Thumb state.
1188 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1189 and also flushes the branch target cache at every context switch.
1190 Note that setting specific bits in the ACTLR register may not be
1191 available in non-secure mode.
1193 config ARM_ERRATA_458693
1194 bool "ARM errata: Processor deadlock when a false hazard is created"
1197 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1198 erratum. For very specific sequences of memory operations, it is
1199 possible for a hazard condition intended for a cache line to instead
1200 be incorrectly associated with a different cache line. This false
1201 hazard might then cause a processor deadlock. The workaround enables
1202 the L1 caching of the NEON accesses and disables the PLD instruction
1203 in the ACTLR register. Note that setting specific bits in the ACTLR
1204 register may not be available in non-secure mode.
1206 config ARM_ERRATA_460075
1207 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1210 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1211 erratum. Any asynchronous access to the L2 cache may encounter a
1212 situation in which recent store transactions to the L2 cache are lost
1213 and overwritten with stale memory contents from external memory. The
1214 workaround disables the write-allocate mode for the L2 cache via the
1215 ACTLR register. Note that setting specific bits in the ACTLR register
1216 may not be available in non-secure mode.
1218 config ARM_ERRATA_742230
1219 bool "ARM errata: DMB operation may be faulty"
1220 depends on CPU_V7 && SMP
1222 This option enables the workaround for the 742230 Cortex-A9
1223 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1224 between two write operations may not ensure the correct visibility
1225 ordering of the two writes. This workaround sets a specific bit in
1226 the diagnostic register of the Cortex-A9 which causes the DMB
1227 instruction to behave as a DSB, ensuring the correct behaviour of
1230 config ARM_ERRATA_742231
1231 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1232 depends on CPU_V7 && SMP
1234 This option enables the workaround for the 742231 Cortex-A9
1235 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1236 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1237 accessing some data located in the same cache line, may get corrupted
1238 data due to bad handling of the address hazard when the line gets
1239 replaced from one of the CPUs at the same time as another CPU is
1240 accessing it. This workaround sets specific bits in the diagnostic
1241 register of the Cortex-A9 which reduces the linefill issuing
1242 capabilities of the processor.
1244 config PL310_ERRATA_588369
1245 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1246 depends on CACHE_L2X0
1248 The PL310 L2 cache controller implements three types of Clean &
1249 Invalidate maintenance operations: by Physical Address
1250 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1251 They are architecturally defined to behave as the execution of a
1252 clean operation followed immediately by an invalidate operation,
1253 both performing to the same memory location. This functionality
1254 is not correctly implemented in PL310 as clean lines are not
1255 invalidated as a result of these operations.
1257 config ARM_ERRATA_720789
1258 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1261 This option enables the workaround for the 720789 Cortex-A9 (prior to
1262 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1263 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1264 As a consequence of this erratum, some TLB entries which should be
1265 invalidated are not, resulting in an incoherency in the system page
1266 tables. The workaround changes the TLB flushing routines to invalidate
1267 entries regardless of the ASID.
1269 config PL310_ERRATA_727915
1270 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1271 depends on CACHE_L2X0
1273 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1274 operation (offset 0x7FC). This operation runs in background so that
1275 PL310 can handle normal accesses while it is in progress. Under very
1276 rare circumstances, due to this erratum, write data can be lost when
1277 PL310 treats a cacheable write transaction during a Clean &
1278 Invalidate by Way operation.
1280 config ARM_ERRATA_743622
1281 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1284 This option enables the workaround for the 743622 Cortex-A9
1285 (r2p*) erratum. Under very rare conditions, a faulty
1286 optimisation in the Cortex-A9 Store Buffer may lead to data
1287 corruption. This workaround sets a specific bit in the diagnostic
1288 register of the Cortex-A9 which disables the Store Buffer
1289 optimisation, preventing the defect from occurring. This has no
1290 visible impact on the overall performance or power consumption of the
1293 config ARM_ERRATA_751472
1294 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1297 This option enables the workaround for the 751472 Cortex-A9 (prior
1298 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1299 completion of a following broadcasted operation if the second
1300 operation is received by a CPU before the ICIALLUIS has completed,
1301 potentially leading to corrupted entries in the cache or TLB.
1303 config PL310_ERRATA_753970
1304 bool "PL310 errata: cache sync operation may be faulty"
1305 depends on CACHE_PL310
1307 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1309 Under some condition the effect of cache sync operation on
1310 the store buffer still remains when the operation completes.
1311 This means that the store buffer is always asked to drain and
1312 this prevents it from merging any further writes. The workaround
1313 is to replace the normal offset of cache sync operation (0x730)
1314 by another offset targeting an unmapped PL310 register 0x740.
1315 This has the same effect as the cache sync operation: store buffer
1316 drain and waiting for all buffers empty.
1318 config ARM_ERRATA_754322
1319 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1322 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1323 r3p*) erratum. A speculative memory access may cause a page table walk
1324 which starts prior to an ASID switch but completes afterwards. This
1325 can populate the micro-TLB with a stale entry which may be hit with
1326 the new ASID. This workaround places two dsb instructions in the mm
1327 switching code so that no page table walks can cross the ASID switch.
1329 config ARM_ERRATA_754327
1330 bool "ARM errata: no automatic Store Buffer drain"
1331 depends on CPU_V7 && SMP
1333 This option enables the workaround for the 754327 Cortex-A9 (prior to
1334 r2p0) erratum. The Store Buffer does not have any automatic draining
1335 mechanism and therefore a livelock may occur if an external agent
1336 continuously polls a memory location waiting to observe an update.
1337 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1338 written polling loops from denying visibility of updates to memory.
1340 config ARM_ERRATA_364296
1341 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1342 depends on CPU_V6 && !SMP
1344 This options enables the workaround for the 364296 ARM1136
1345 r0p2 erratum (possible cache data corruption with
1346 hit-under-miss enabled). It sets the undocumented bit 31 in
1347 the auxiliary control register and the FI bit in the control
1348 register, thus disabling hit-under-miss without putting the
1349 processor into full low interrupt latency mode. ARM11MPCore
1352 config ARM_ERRATA_764369
1353 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1354 depends on CPU_V7 && SMP
1356 This option enables the workaround for erratum 764369
1357 affecting Cortex-A9 MPCore with two or more processors (all
1358 current revisions). Under certain timing circumstances, a data
1359 cache line maintenance operation by MVA targeting an Inner
1360 Shareable memory region may fail to proceed up to either the
1361 Point of Coherency or to the Point of Unification of the
1362 system. This workaround adds a DSB instruction before the
1363 relevant cache maintenance functions and sets a specific bit
1364 in the diagnostic control register of the SCU.
1366 config PL310_ERRATA_769419
1367 bool "PL310 errata: no automatic Store Buffer drain"
1368 depends on CACHE_L2X0
1370 On revisions of the PL310 prior to r3p2, the Store Buffer does
1371 not automatically drain. This can cause normal, non-cacheable
1372 writes to be retained when the memory system is idle, leading
1373 to suboptimal I/O performance for drivers using coherent DMA.
1374 This option adds a write barrier to the cpu_idle loop so that,
1375 on systems with an outer cache, the store buffer is drained
1380 source "arch/arm/common/Kconfig"
1390 Find out whether you have ISA slots on your motherboard. ISA is the
1391 name of a bus system, i.e. the way the CPU talks to the other stuff
1392 inside your box. Other bus systems are PCI, EISA, MicroChannel
1393 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1394 newer boards don't support it. If you have ISA, say Y, otherwise N.
1396 # Select ISA DMA controller support
1401 # Select ISA DMA interface
1406 bool "PCI support" if MIGHT_HAVE_PCI
1408 Find out whether you have a PCI motherboard. PCI is the name of a
1409 bus system, i.e. the way the CPU talks to the other stuff inside
1410 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1411 VESA. If you have PCI, say Y, otherwise N.
1417 config PCI_NANOENGINE
1418 bool "BSE nanoEngine PCI support"
1419 depends on SA1100_NANOENGINE
1421 Enable PCI on the BSE nanoEngine board.
1426 # Select the host bridge type
1427 config PCI_HOST_VIA82C505
1429 depends on PCI && ARCH_SHARK
1432 config PCI_HOST_ITE8152
1434 depends on PCI && MACH_ARMCORE
1438 source "drivers/pci/Kconfig"
1440 source "drivers/pcmcia/Kconfig"
1444 menu "Kernel Features"
1446 source "kernel/time/Kconfig"
1449 bool "Symmetric Multi-Processing"
1450 depends on CPU_V6K || CPU_V7
1451 depends on GENERIC_CLOCKEVENTS
1452 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1453 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1454 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1455 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1457 select USE_GENERIC_SMP_HELPERS
1458 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1460 This enables support for systems with more than one CPU. If you have
1461 a system with only one CPU, like most personal computers, say N. If
1462 you have a system with more than one CPU, say Y.
1464 If you say N here, the kernel will run on single and multiprocessor
1465 machines, but will use only one CPU of a multiprocessor machine. If
1466 you say Y here, the kernel will run on many, but not all, single
1467 processor machines. On a single processor machine, the kernel will
1468 run faster if you say N here.
1470 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1471 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1472 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1474 If you don't know what to do here, say N.
1477 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1478 depends on EXPERIMENTAL
1479 depends on SMP && !XIP_KERNEL
1482 SMP kernels contain instructions which fail on non-SMP processors.
1483 Enabling this option allows the kernel to modify itself to make
1484 these instructions safe. Disabling it allows about 1K of space
1487 If you don't know what to do here, say Y.
1489 config ARM_CPU_TOPOLOGY
1490 bool "Support cpu topology definition"
1491 depends on SMP && CPU_V7
1494 Support ARM cpu topology definition. The MPIDR register defines
1495 affinity between processors which is then used to describe the cpu
1496 topology of an ARM System.
1499 bool "Multi-core scheduler support"
1500 depends on ARM_CPU_TOPOLOGY
1502 Multi-core scheduler support improves the CPU scheduler's decision
1503 making when dealing with multi-core CPU chips at a cost of slightly
1504 increased overhead in some places. If unsure say N here.
1507 bool "SMT scheduler support"
1508 depends on ARM_CPU_TOPOLOGY
1510 Improves the CPU scheduler's decision making when dealing with
1511 MultiThreading at a cost of slightly increased overhead in some
1512 places. If unsure say N here.
1517 This option enables support for the ARM system coherency unit
1524 This options enables support for the ARM timer and watchdog unit
1527 prompt "Memory split"
1530 Select the desired split between kernel and user memory.
1532 If you are not absolutely sure what you are doing, leave this
1536 bool "3G/1G user/kernel split"
1538 bool "2G/2G user/kernel split"
1540 bool "1G/3G user/kernel split"
1545 default 0x40000000 if VMSPLIT_1G
1546 default 0x80000000 if VMSPLIT_2G
1550 int "Maximum number of CPUs (2-32)"
1556 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1557 depends on SMP && HOTPLUG && EXPERIMENTAL
1559 Say Y here to experiment with turning CPUs off and on. CPUs
1560 can be controlled through /sys/devices/system/cpu.
1563 bool "Use local timer interrupts"
1566 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1568 Enable support for local timers on SMP platforms, rather then the
1569 legacy IPI broadcast method. Local timers allows the system
1570 accounting to be spread across the timer interval, preventing a
1571 "thundering herd" at every timer tick.
1573 source kernel/Kconfig.preempt
1577 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1578 ARCH_S5PV210 || ARCH_EXYNOS4
1579 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1580 default AT91_TIMER_HZ if ARCH_AT91
1581 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1584 config THUMB2_KERNEL
1585 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1586 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1588 select ARM_ASM_UNIFIED
1591 By enabling this option, the kernel will be compiled in
1592 Thumb-2 mode. A compiler/assembler that understand the unified
1593 ARM-Thumb syntax is needed.
1597 config THUMB2_AVOID_R_ARM_THM_JUMP11
1598 bool "Work around buggy Thumb-2 short branch relocations in gas"
1599 depends on THUMB2_KERNEL && MODULES
1602 Various binutils versions can resolve Thumb-2 branches to
1603 locally-defined, preemptible global symbols as short-range "b.n"
1604 branch instructions.
1606 This is a problem, because there's no guarantee the final
1607 destination of the symbol, or any candidate locations for a
1608 trampoline, are within range of the branch. For this reason, the
1609 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1610 relocation in modules at all, and it makes little sense to add
1613 The symptom is that the kernel fails with an "unsupported
1614 relocation" error when loading some modules.
1616 Until fixed tools are available, passing
1617 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1618 code which hits this problem, at the cost of a bit of extra runtime
1619 stack usage in some cases.
1621 The problem is described in more detail at:
1622 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1624 Only Thumb-2 kernels are affected.
1626 Unless you are sure your tools don't have this problem, say Y.
1628 config ARM_ASM_UNIFIED
1632 bool "Use the ARM EABI to compile the kernel"
1634 This option allows for the kernel to be compiled using the latest
1635 ARM ABI (aka EABI). This is only useful if you are using a user
1636 space environment that is also compiled with EABI.
1638 Since there are major incompatibilities between the legacy ABI and
1639 EABI, especially with regard to structure member alignment, this
1640 option also changes the kernel syscall calling convention to
1641 disambiguate both ABIs and allow for backward compatibility support
1642 (selected with CONFIG_OABI_COMPAT).
1644 To use this you need GCC version 4.0.0 or later.
1647 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1648 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1651 This option preserves the old syscall interface along with the
1652 new (ARM EABI) one. It also provides a compatibility layer to
1653 intercept syscalls that have structure arguments which layout
1654 in memory differs between the legacy ABI and the new ARM EABI
1655 (only for non "thumb" binaries). This option adds a tiny
1656 overhead to all syscalls and produces a slightly larger kernel.
1657 If you know you'll be using only pure EABI user space then you
1658 can say N here. If this option is not selected and you attempt
1659 to execute a legacy ABI binary then the result will be
1660 UNPREDICTABLE (in fact it can be predicted that it won't work
1661 at all). If in doubt say Y.
1663 config ARCH_HAS_HOLES_MEMORYMODEL
1666 config ARCH_SPARSEMEM_ENABLE
1669 config ARCH_SPARSEMEM_DEFAULT
1670 def_bool ARCH_SPARSEMEM_ENABLE
1672 config ARCH_SELECT_MEMORY_MODEL
1673 def_bool ARCH_SPARSEMEM_ENABLE
1675 config HAVE_ARCH_PFN_VALID
1676 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1679 bool "High Memory Support"
1682 The address space of ARM processors is only 4 Gigabytes large
1683 and it has to accommodate user address space, kernel address
1684 space as well as some memory mapped IO. That means that, if you
1685 have a large amount of physical memory and/or IO, not all of the
1686 memory can be "permanently mapped" by the kernel. The physical
1687 memory that is not permanently mapped is called "high memory".
1689 Depending on the selected kernel/user memory split, minimum
1690 vmalloc space and actual amount of RAM, you may not need this
1691 option which should result in a slightly faster kernel.
1696 bool "Allocate 2nd-level pagetables from highmem"
1699 config HW_PERF_EVENTS
1700 bool "Enable hardware performance counter support for perf events"
1701 depends on PERF_EVENTS && CPU_HAS_PMU
1704 Enable hardware performance counter support for perf events. If
1705 disabled, perf events will use software events only.
1709 config FORCE_MAX_ZONEORDER
1710 int "Maximum zone order" if ARCH_SHMOBILE
1711 range 11 64 if ARCH_SHMOBILE
1712 default "9" if SA1111
1715 The kernel memory allocator divides physically contiguous memory
1716 blocks into "zones", where each zone is a power of two number of
1717 pages. This option selects the largest power of two that the kernel
1718 keeps in the memory allocator. If you need to allocate very large
1719 blocks of physically contiguous memory, then you may need to
1720 increase this value.
1722 This config option is actually maximum order plus one. For example,
1723 a value of 11 means that the largest free memory block is 2^10 pages.
1726 bool "Timer and CPU usage LEDs"
1727 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1728 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1729 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1730 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1731 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1732 ARCH_AT91 || ARCH_DAVINCI || \
1733 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1735 If you say Y here, the LEDs on your machine will be used
1736 to provide useful information about your current system status.
1738 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1739 be able to select which LEDs are active using the options below. If
1740 you are compiling a kernel for the EBSA-110 or the LART however, the
1741 red LED will simply flash regularly to indicate that the system is
1742 still functional. It is safe to say Y here if you have a CATS
1743 system, but the driver will do nothing.
1746 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1747 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1748 || MACH_OMAP_PERSEUS2
1750 depends on !GENERIC_CLOCKEVENTS
1751 default y if ARCH_EBSA110
1753 If you say Y here, one of the system LEDs (the green one on the
1754 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1755 will flash regularly to indicate that the system is still
1756 operational. This is mainly useful to kernel hackers who are
1757 debugging unstable kernels.
1759 The LART uses the same LED for both Timer LED and CPU usage LED
1760 functions. You may choose to use both, but the Timer LED function
1761 will overrule the CPU usage LED.
1764 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1766 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1767 || MACH_OMAP_PERSEUS2
1770 If you say Y here, the red LED will be used to give a good real
1771 time indication of CPU usage, by lighting whenever the idle task
1772 is not currently executing.
1774 The LART uses the same LED for both Timer LED and CPU usage LED
1775 functions. You may choose to use both, but the Timer LED function
1776 will overrule the CPU usage LED.
1778 config ALIGNMENT_TRAP
1780 depends on CPU_CP15_MMU
1781 default y if !ARCH_EBSA110
1782 select HAVE_PROC_CPU if PROC_FS
1784 ARM processors cannot fetch/store information which is not
1785 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1786 address divisible by 4. On 32-bit ARM processors, these non-aligned
1787 fetch/store instructions will be emulated in software if you say
1788 here, which has a severe performance impact. This is necessary for
1789 correct operation of some network protocols. With an IP-only
1790 configuration it is safe to say N, otherwise say Y.
1792 config UACCESS_WITH_MEMCPY
1793 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1794 depends on MMU && EXPERIMENTAL
1795 default y if CPU_FEROCEON
1797 Implement faster copy_to_user and clear_user methods for CPU
1798 cores where a 8-word STM instruction give significantly higher
1799 memory write throughput than a sequence of individual 32bit stores.
1801 A possible side effect is a slight increase in scheduling latency
1802 between threads sharing the same address space if they invoke
1803 such copy operations with large buffers.
1805 However, if the CPU data cache is using a write-allocate mode,
1806 this option is unlikely to provide any performance gain.
1810 prompt "Enable seccomp to safely compute untrusted bytecode"
1812 This kernel feature is useful for number crunching applications
1813 that may need to compute untrusted bytecode during their
1814 execution. By using pipes or other transports made available to
1815 the process as file descriptors supporting the read/write
1816 syscalls, it's possible to isolate those applications in
1817 their own address space using seccomp. Once seccomp is
1818 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1819 and the task is only allowed to execute a few safe syscalls
1820 defined by each seccomp mode.
1822 config CC_STACKPROTECTOR
1823 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1824 depends on EXPERIMENTAL
1826 This option turns on the -fstack-protector GCC feature. This
1827 feature puts, at the beginning of functions, a canary value on
1828 the stack just before the return address, and validates
1829 the value just before actually returning. Stack based buffer
1830 overflows (that need to overwrite this return address) now also
1831 overwrite the canary, which gets detected and the attack is then
1832 neutralized via a kernel panic.
1833 This feature requires gcc version 4.2 or above.
1835 config DEPRECATED_PARAM_STRUCT
1836 bool "Provide old way to pass kernel parameters"
1838 This was deprecated in 2001 and announced to live on for 5 years.
1839 Some old boot loaders still use this way.
1846 bool "Flattened Device Tree support"
1848 select OF_EARLY_FLATTREE
1851 Include support for flattened device tree machine descriptions.
1853 # Compressed boot loader in ROM. Yes, we really want to ask about
1854 # TEXT and BSS so we preserve their values in the config files.
1855 config ZBOOT_ROM_TEXT
1856 hex "Compressed ROM boot loader base address"
1859 The physical address at which the ROM-able zImage is to be
1860 placed in the target. Platforms which normally make use of
1861 ROM-able zImage formats normally set this to a suitable
1862 value in their defconfig file.
1864 If ZBOOT_ROM is not enabled, this has no effect.
1866 config ZBOOT_ROM_BSS
1867 hex "Compressed ROM boot loader BSS address"
1870 The base address of an area of read/write memory in the target
1871 for the ROM-able zImage which must be available while the
1872 decompressor is running. It must be large enough to hold the
1873 entire decompressed kernel plus an additional 128 KiB.
1874 Platforms which normally make use of ROM-able zImage formats
1875 normally set this to a suitable value in their defconfig file.
1877 If ZBOOT_ROM is not enabled, this has no effect.
1880 bool "Compressed boot loader in ROM/flash"
1881 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1883 Say Y here if you intend to execute your compressed kernel image
1884 (zImage) directly from ROM or flash. If unsure, say N.
1887 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1888 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1889 default ZBOOT_ROM_NONE
1891 Include experimental SD/MMC loading code in the ROM-able zImage.
1892 With this enabled it is possible to write the the ROM-able zImage
1893 kernel image to an MMC or SD card and boot the kernel straight
1894 from the reset vector. At reset the processor Mask ROM will load
1895 the first part of the the ROM-able zImage which in turn loads the
1896 rest the kernel image to RAM.
1898 config ZBOOT_ROM_NONE
1899 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1901 Do not load image from SD or MMC
1903 config ZBOOT_ROM_MMCIF
1904 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1906 Load image from MMCIF hardware block.
1908 config ZBOOT_ROM_SH_MOBILE_SDHI
1909 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1911 Load image from SDHI hardware block
1915 config ARM_APPENDED_DTB
1916 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1917 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1919 With this option, the boot code will look for a device tree binary
1920 (DTB) appended to zImage
1921 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1923 This is meant as a backward compatibility convenience for those
1924 systems with a bootloader that can't be upgraded to accommodate
1925 the documented boot protocol using a device tree.
1927 Beware that there is very little in terms of protection against
1928 this option being confused by leftover garbage in memory that might
1929 look like a DTB header after a reboot if no actual DTB is appended
1930 to zImage. Do not leave this option active in a production kernel
1931 if you don't intend to always append a DTB. Proper passing of the
1932 location into r2 of a bootloader provided DTB is always preferable
1935 config ARM_ATAG_DTB_COMPAT
1936 bool "Supplement the appended DTB with traditional ATAG information"
1937 depends on ARM_APPENDED_DTB
1939 Some old bootloaders can't be updated to a DTB capable one, yet
1940 they provide ATAGs with memory configuration, the ramdisk address,
1941 the kernel cmdline string, etc. Such information is dynamically
1942 provided by the bootloader and can't always be stored in a static
1943 DTB. To allow a device tree enabled kernel to be used with such
1944 bootloaders, this option allows zImage to extract the information
1945 from the ATAG list and store it at run time into the appended DTB.
1948 string "Default kernel command string"
1951 On some architectures (EBSA110 and CATS), there is currently no way
1952 for the boot loader to pass arguments to the kernel. For these
1953 architectures, you should supply some command-line options at build
1954 time by entering them here. As a minimum, you should specify the
1955 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1958 prompt "Kernel command line type" if CMDLINE != ""
1959 default CMDLINE_FROM_BOOTLOADER
1961 config CMDLINE_FROM_BOOTLOADER
1962 bool "Use bootloader kernel arguments if available"
1964 Uses the command-line options passed by the boot loader. If
1965 the boot loader doesn't provide any, the default kernel command
1966 string provided in CMDLINE will be used.
1968 config CMDLINE_EXTEND
1969 bool "Extend bootloader kernel arguments"
1971 The command-line arguments provided by the boot loader will be
1972 appended to the default kernel command string.
1974 config CMDLINE_FORCE
1975 bool "Always use the default kernel command string"
1977 Always use the default kernel command string, even if the boot
1978 loader passes other arguments to the kernel.
1979 This is useful if you cannot or don't want to change the
1980 command-line options your boot loader passes to the kernel.
1984 bool "Kernel Execute-In-Place from ROM"
1985 depends on !ZBOOT_ROM
1987 Execute-In-Place allows the kernel to run from non-volatile storage
1988 directly addressable by the CPU, such as NOR flash. This saves RAM
1989 space since the text section of the kernel is not loaded from flash
1990 to RAM. Read-write sections, such as the data section and stack,
1991 are still copied to RAM. The XIP kernel is not compressed since
1992 it has to run directly from flash, so it will take more space to
1993 store it. The flash address used to link the kernel object files,
1994 and for storing it, is configuration dependent. Therefore, if you
1995 say Y here, you must know the proper physical address where to
1996 store the kernel image depending on your own flash memory usage.
1998 Also note that the make target becomes "make xipImage" rather than
1999 "make zImage" or "make Image". The final kernel binary to put in
2000 ROM memory will be arch/arm/boot/xipImage.
2004 config XIP_PHYS_ADDR
2005 hex "XIP Kernel Physical Location"
2006 depends on XIP_KERNEL
2007 default "0x00080000"
2009 This is the physical address in your flash memory the kernel will
2010 be linked for and stored to. This address is dependent on your
2014 bool "Kexec system call (EXPERIMENTAL)"
2015 depends on EXPERIMENTAL
2017 kexec is a system call that implements the ability to shutdown your
2018 current kernel, and to start another kernel. It is like a reboot
2019 but it is independent of the system firmware. And like a reboot
2020 you can start any kernel with it, not just Linux.
2022 It is an ongoing process to be certain the hardware in a machine
2023 is properly shutdown, so do not be surprised if this code does not
2024 initially work for you. It may help to enable device hotplugging
2028 bool "Export atags in procfs"
2032 Should the atags used to boot the kernel be exported in an "atags"
2033 file in procfs. Useful with kexec.
2036 bool "Build kdump crash kernel (EXPERIMENTAL)"
2037 depends on EXPERIMENTAL
2039 Generate crash dump after being started by kexec. This should
2040 be normally only set in special crash dump kernels which are
2041 loaded in the main kernel with kexec-tools into a specially
2042 reserved region and then later executed after a crash by
2043 kdump/kexec. The crash dump kernel must be compiled to a
2044 memory address not used by the main kernel
2046 For more details see Documentation/kdump/kdump.txt
2048 config AUTO_ZRELADDR
2049 bool "Auto calculation of the decompressed kernel image address"
2050 depends on !ZBOOT_ROM && !ARCH_U300
2052 ZRELADDR is the physical address where the decompressed kernel
2053 image will be placed. If AUTO_ZRELADDR is selected, the address
2054 will be determined at run-time by masking the current IP with
2055 0xf8000000. This assumes the zImage being placed in the first 128MB
2056 from start of memory.
2060 menu "CPU Power Management"
2064 source "drivers/cpufreq/Kconfig"
2067 tristate "CPUfreq driver for i.MX CPUs"
2068 depends on ARCH_MXC && CPU_FREQ
2069 select CPU_FREQ_TABLE
2071 This enables the CPUfreq driver for i.MX CPUs.
2073 config CPU_FREQ_SA1100
2076 config CPU_FREQ_SA1110
2079 config CPU_FREQ_INTEGRATOR
2080 tristate "CPUfreq driver for ARM Integrator CPUs"
2081 depends on ARCH_INTEGRATOR && CPU_FREQ
2084 This enables the CPUfreq driver for ARM Integrator CPUs.
2086 For details, take a look at <file:Documentation/cpu-freq>.
2092 depends on CPU_FREQ && ARCH_PXA && PXA25x
2094 select CPU_FREQ_TABLE
2095 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2100 Internal configuration node for common cpufreq on Samsung SoC
2102 config CPU_FREQ_S3C24XX
2103 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2104 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2107 This enables the CPUfreq driver for the Samsung S3C24XX family
2110 For details, take a look at <file:Documentation/cpu-freq>.
2114 config CPU_FREQ_S3C24XX_PLL
2115 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2116 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2118 Compile in support for changing the PLL frequency from the
2119 S3C24XX series CPUfreq driver. The PLL takes time to settle
2120 after a frequency change, so by default it is not enabled.
2122 This also means that the PLL tables for the selected CPU(s) will
2123 be built which may increase the size of the kernel image.
2125 config CPU_FREQ_S3C24XX_DEBUG
2126 bool "Debug CPUfreq Samsung driver core"
2127 depends on CPU_FREQ_S3C24XX
2129 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2131 config CPU_FREQ_S3C24XX_IODEBUG
2132 bool "Debug CPUfreq Samsung driver IO timing"
2133 depends on CPU_FREQ_S3C24XX
2135 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2137 config CPU_FREQ_S3C24XX_DEBUGFS
2138 bool "Export debugfs for CPUFreq"
2139 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2141 Export status information via debugfs.
2145 source "drivers/cpuidle/Kconfig"
2149 menu "Floating point emulation"
2151 comment "At least one emulation must be selected"
2154 bool "NWFPE math emulation"
2155 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2157 Say Y to include the NWFPE floating point emulator in the kernel.
2158 This is necessary to run most binaries. Linux does not currently
2159 support floating point hardware so you need to say Y here even if
2160 your machine has an FPA or floating point co-processor podule.
2162 You may say N here if you are going to load the Acorn FPEmulator
2163 early in the bootup.
2166 bool "Support extended precision"
2167 depends on FPE_NWFPE
2169 Say Y to include 80-bit support in the kernel floating-point
2170 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2171 Note that gcc does not generate 80-bit operations by default,
2172 so in most cases this option only enlarges the size of the
2173 floating point emulator without any good reason.
2175 You almost surely want to say N here.
2178 bool "FastFPE math emulation (EXPERIMENTAL)"
2179 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2181 Say Y here to include the FAST floating point emulator in the kernel.
2182 This is an experimental much faster emulator which now also has full
2183 precision for the mantissa. It does not support any exceptions.
2184 It is very simple, and approximately 3-6 times faster than NWFPE.
2186 It should be sufficient for most programs. It may be not suitable
2187 for scientific calculations, but you have to check this for yourself.
2188 If you do not feel you need a faster FP emulation you should better
2192 bool "VFP-format floating point maths"
2193 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2195 Say Y to include VFP support code in the kernel. This is needed
2196 if your hardware includes a VFP unit.
2198 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2199 release notes and additional status information.
2201 Say N if your target does not have VFP hardware.
2209 bool "Advanced SIMD (NEON) Extension support"
2210 depends on VFPv3 && CPU_V7
2212 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2217 menu "Userspace binary formats"
2219 source "fs/Kconfig.binfmt"
2222 tristate "RISC OS personality"
2225 Say Y here to include the kernel code necessary if you want to run
2226 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2227 experimental; if this sounds frightening, say N and sleep in peace.
2228 You can also say M here to compile this support as a module (which
2229 will be called arthur).
2233 menu "Power management options"
2235 source "kernel/power/Kconfig"
2237 config ARCH_SUSPEND_POSSIBLE
2238 depends on !ARCH_S5PC100
2239 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2240 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2243 config ARM_CPU_SUSPEND
2248 source "net/Kconfig"
2250 source "drivers/Kconfig"
2254 source "arch/arm/Kconfig.debug"
2256 source "security/Kconfig"
2258 source "crypto/Kconfig"
2260 source "lib/Kconfig"