From 876787d3f9c701c281bc8fe3442d50d57198e97b Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 14 Jul 2011 17:34:04 +0530 Subject: [PATCH] omap2420h4: Remove this board because is not being maintained Discussed in this thread, http://groups.google.com/group/x-loader/browse_thread/thread/42ee3aa6df45a896/ea7296ba34155bad#ea7296ba34155bad Signed-off-by: Enric Balletbo i Serra Signed-off-by: Anand Gadiyar --- Makefile | 3 - board/omap2420h4/Makefile | 51 --- board/omap2420h4/config.mk | 26 -- board/omap2420h4/omap2420h4.c | 598 ---------------------------------- board/omap2420h4/platform.S | 218 ------------- board/omap2420h4/x-load.lds | 54 --- drivers/Makefile | 4 - include/configs/omap2420h4.h | 140 -------- 8 files changed, 1094 deletions(-) delete mode 100644 board/omap2420h4/Makefile delete mode 100644 board/omap2420h4/config.mk delete mode 100644 board/omap2420h4/omap2420h4.c delete mode 100644 board/omap2420h4/platform.S delete mode 100644 board/omap2420h4/x-load.lds delete mode 100644 include/configs/omap2420h4.h diff --git a/Makefile b/Makefile index 7f836e2..f378923 100644 --- a/Makefile +++ b/Makefile @@ -201,9 +201,6 @@ unconfig: ## OMAP2 (ARM1136) Systems ######################################################################### -omap2420h4_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 - omap2430sdp_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2430sdp diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile deleted file mode 100644 index e6f7629..0000000 --- a/board/omap2420h4/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap2420h4.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/omap2420h4/config.mk b/board/omap2420h4/config.mk deleted file mode 100644 index 1c770f3..0000000 --- a/board/omap2420h4/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2004 -# Texas Instruments, -# -# TI H4 board with OMAP2420 (ARM1136) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 -# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) ES2 will be configurable -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -# CONFIG_PARTIAL_SRAM must be defined to use this. -TEXT_BASE = 0x80e80000 - -# Used with full SRAM boot. -# This is either with a GP system or a signed boot image. -# easiest, and safest way to go if you can. -# Comment out //CONFIG_PARTIAL_SRAM for this one. -# -#TEXT_BASE = 0x40280000 - diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c deleted file mode 100644 index ef81b49..0000000 --- a/board/omap2420h4/omap2420h4.c +++ /dev/null @@ -1,598 +0,0 @@ -/* - * Copyright (C) 2005 Texas Instruments. - * Jian Zhang - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include - -#include -#include -#include - -static void wait_for_command_complete(unsigned int wd_base); -static void watchdog_init(void); -static void peripheral_enable(void); -static void muxSetupUART1(void); -static u32 get_cpu_rev(void); - - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -#ifdef CFG_SDRAM_DDR -void -config_sdram_ddr(u32 rev) -{ - /* ball D11, mode 0 */ - __raw_writeb(0x08, 0x48000032); - - /* SDRC_CS0 Configuration */ - if (rev == CPU_2420_2422_ES1) { - __raw_writel(H4_2422_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); - } else { - __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - } - - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - - /* - * CS0 SDRC Mode Register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - __raw_writel(0x00000032, SDRC_MR_0); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00000002, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00000002, SDRC_DLLB_CTRL); - } else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x - } - -} -#endif // CFG_SDRAM_DDR - - -#ifdef CFG_SDRAM_COMBO -void -config_sdram_combo(u32 rev) -{ - - u32 dllctrl=0; - - /* ball C12, mode 0 */ - __raw_writeb(0x00, 0x480000a1); - /* ball D11, mode 0 */ - __raw_writeb(0x00, 0x48000032); - /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */ - __raw_writeb(0x00, 0x480000a3); - - /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */ - __raw_writel(0x00000012, SDRC_SYSCONFIG); - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); - - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0); - - /* CS1 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* CS1 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_1); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_242X_ES1) - dllctrl = (BIT0|BIT3); - else - dllctrl = BIT0; - - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLA_CTRL); - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ? - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x - } -} - -#endif // CFG_SDRAM_COMBO - -#ifdef CFG_SDRAM_SDR -void -config_sdram_sdr(u32 rev) -{ - u32 dllctrl=0; - - /* ball D11, mode 0 */ - __raw_writeb(0x00, 0x48000032); - - __raw_writel(0x00000012, SDRC_SYSCONFIG); - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); - - /* Chip-level shared interface management */ - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */ - if (rev == CPU_2420_2422_ES1) - __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); - else - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX14: 32Mbx32 */ - __raw_writel(H4_2420_SDRC_MDCFG_0_SDR, SDRC_MCFG_0); /* diff from combo case */ - __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 2 - SDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2420_SDRC_MR_0_SDR, SDRC_MR_0); /* diff from combo case */ - - /* SDRC DLLA control register */ - /* Enable DLL, Load counter with 115 (middle of range) */ - /* Delay is 90 degrees */ - - if (rev == CPU_242X_ES1) - dllctrl = (BIT0|BIT3); - else - dllctrl = BIT0; - - if (rev == CPU_2420_2422_ES1) { - __raw_writel(0x00007306, SDRC_DLLA_CTRL); - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ - } - else { - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x - } - -} -#endif // CFG_SDRAM_SDR - -#ifdef CFG_SDRAM_STACKED -void -config_sdram_stacked(u32 rev) -{ - - /* Pin Muxing for SDRC */ - __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */ - __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */ - __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */ - __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */ - - /* configure sdrc 32 bit for COMBO ddr sdram */ - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */ - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */ - - /* SDRC_SHARING */ - /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */ - //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - __raw_writel(0x00004900, SDRC_SHARING); - - /* SDRC_CS0 Configuration */ - /* None for ES2.1 */ - - /* SDRC_CS1 Configuration */ - __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */ - - /* Disable power down of CKE */ - __raw_writel(0x00000085, SDRC_POWER); - - __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */ - __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */ - __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */ - __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */ - - /*Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(0x00000032, SDRC_MR_1); - __raw_writel(0x00000020, SDRC_EMR2_1); /* weak-strength driver */ - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x - } -} -#endif // CFG_SDRAM_STACKED - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ -int s_init(int skip) -{ - u32 rev; - - rev = get_cpu_rev(); - - watchdog_init(); - muxSetupUART1(); - delay(100); - - /*DPLL out = 2x DPLL --> core clock */ - __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); - - /*DPLL into low power bypass (others off) */ - __raw_writel(0x00000001, CM_CLKEN_PLL); - - /*MPU core clock = Core /2 = 300 */ - __raw_writel(MPU_DIV, CM_CLKSEL_MPU); - - /*DSPif=200, DSPif=100, IVA=200 */ - __raw_writel(DSP_DIV, CM_CLKSEL_DSP); - - /*GFX clock (L3/2) 50MHz */ - __raw_writel(GFX_DIV, CM_CLKSEL_GFX); - - /*L3=100, L4=100, DisplaySS=50 Vlync=96Mhz,ssi=100, usb=50 */ - __raw_writel(BUS_DIV, CM_CLKSEL1_CORE); - - /*12MHz apll src, 12/(1+1)*50=300 */ - __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); - - /*Valid the configuration */ - __raw_writel(0x00000001, PRCM_CLKCFG_CTRL); - delay(1000); - - /*Enable DPLL=300, 96MHz APLL locked. */ - __raw_writel(0x0000000F, CM_CLKEN_PLL); - delay(200000); - -#ifdef CFG_SDRAM_DDR - config_sdram_ddr(rev); -#elif defined(CFG_SDRAM_COMBO) - config_sdram_combo(rev); -#elif defined(CFG_SDRAM_SDR) - config_sdram_sdr(rev); -#elif defined(CFG_SDRAM_STACKED) - config_sdram_stacked(rev); -#else -#error SDRAM type not supported -#endif - - delay(20000); - peripheral_enable(); - return(0); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -static void watchdog_init(void) -{ -#define GP (BIT8|BIT9) - - /* There are 4 watch dogs. 1 secure, and 3 general purpose. - * I would expect that the ROM takes care of the secure one, - * but we will try also. Of the 3 GP ones, 1 can reset us - * directly, the other 2 only generate MPU interrupts. - */ - __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); - -#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/ - __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR); - wait_for_command_complete(WD3_BASE); - __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR); - - __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR); - wait_for_command_complete(WD4_BASE); - __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR); -#endif - -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -static void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base+WWPS); - } while (pending); -} - - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -static void peripheral_enable(void) -{ - unsigned int v, if_clks=0, func_clks=0; - - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */ - __raw_writel(v, CM_CLKSEL2_CORE); - __raw_writel(0x1, CM_CLKSEL_WKUP); - -#ifdef CFG_NS16550 - /* Enable UART1 clock */ - func_clks |= BIT21; - if_clks |= BIT21; -#endif - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - delay(1000); - -#ifndef KERNEL_UPDATED - { -#define V1 0xffffffff -#define V2 0x00000007 - - __raw_writel(V1, CM_FCLKEN1_CORE); - __raw_writel(V2, CM_FCLKEN2_CORE); - __raw_writel(V1, CM_ICLKEN1_CORE); - __raw_writel(V1, CM_ICLKEN2_CORE); - } -#endif - -} - -/* Pin Muxing registers used for UART1 */ -#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5) -#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6) -#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7) -#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8) -/**************************************** - * Routine: muxSetupUART1 (ostboot) - * Description: Set up uart1 muxing - *****************************************/ -static void muxSetupUART1(void) -{ - volatile unsigned char *MuxConfigReg; - - /* UART1_CTS pin configuration, PIN = D21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_RTS pin configuration, PIN = H21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_TX pin configuration, PIN = L20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_RX pin configuration, PIN = T21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -int nand_init(void) -{ - u32 rev; - - rev = get_cpu_rev(); - - - /* GPMC pin muxing */ - (*(volatile int*)0x48000070) &= 0x000000FF; - (*(volatile int*)0x48000074) &= 0x00000000; - (*(volatile int*)0x48000078) &= 0x00000000; - (*(volatile int*)0x4800007C) &= 0x00000000; - (*(volatile int*)0x48000080) &= 0xFF000000; - - /* GPMC_IO_DIR */ - (*(volatile int*)0x4800008C) = 0x19000000; - - /* GPMC Configuration */ - (*(volatile int*)0x6800A010) = 0x0000000A; - while (((*(volatile int *)0x6800A014) & 0x00000001) == 0); - - (*(volatile int*)0x6800A050) = 0x00000001; - (*(volatile int*)0x6800A060) = 0x00001800; - (*(volatile int*)0x6800A064) = 0x00141400; - (*(volatile int*)0x6800A068) = 0x00141400; - (*(volatile int*)0x6800A06C) = 0x0F010F01; - (*(volatile int*)0x6800A070) = 0x010C1414; - (*(volatile int*)0x6800A074) = 0x00000A80; - (*(volatile int*)0x6800A078) = 0x00000C44; //base 0x04000000 - - (*(volatile int*)0x6800A0A8) = 0x00000000; - delay(1000); -#ifdef CFG_SDRAM_STACKED - (*(volatile int*)0x6800A090) = 0x00011000; -#else - (*(volatile int*)0x6800A090) = 0x00011200; -#endif - (*(volatile int*)0x6800A094) = 0x001f1f00; - (*(volatile int*)0x6800A098) = 0x00080802; - (*(volatile int*)0x6800A09C) = 0x1C091C09; - (*(volatile int*)0x6800A0A0) = 0x031A1F1F; - (*(volatile int*)0x6800A0A4) = 0x000003C2; - (*(volatile int*)0x6800A0A8) = 0x00000F48; - - if (rev != CPU_2420_2422_ES1) - (*(volatile int*)0x6800A040) = 0x1FF0; // es2.x - - if (nand_chip()){ - printf("Unsupported Chip!\n"); - return 1; - } - return 0; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 v; - v = __raw_readl(TAP_IDCODE_REG); - v = v >> 28; - return(v+1); /* currently 2422 and 2420 match up */ -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{} - - - diff --git a/board/omap2420h4/platform.S b/board/omap2420h4/platform.S deleted file mode 100644 index 5cc37e5..0000000 --- a/board/omap2420h4/platform.S +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#ifdef CONFIG_PARTIAL_SRAM - -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = PRCM_CLKCFG_CTRL - addr of valid reg - * R1 = CM_CLKEN_PLL - addr dpll ctlr reg - * R2 = dpll value - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - ******************************************************************************/ -.global go_to_speed - go_to_speed: - sub sp, sp, #0x4 /* get some stack space */ - str r4, [sp] /* save r4's value */ - - /* move into fast relock bypass */ - ldr r8, pll_ctl_add - mov r4, #0x2 - str r4, [r8] - ldr r4, pll_stat -block: - ldr r8, [r4] /* wait for bypass to take effect */ - and r8, r8, #0x3 - cmp r8, #0x1 - bne block - - /* set new dpll dividers _after_ in bypass */ - ldr r4, pll_div_add - ldr r8, pll_div_val - str r8, [r4] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r4, cfg3_0_addr - ldr r8, cfg3_0_val - str r8, [r4] - ldr r4, cfg4_0_addr - ldr r8, cfg4_0_val - str r8, [r4] - ldr r4, cfg1_0_addr - ldr r8, [r4] - orr r8, r8, #0x3 /* up gpmc divider */ - str r8, [r4] - - /* setup to 2x loop though code. The first loop pre-loads the - * icache, the 2nd commits the prcm config, and locks the dpll - */ - mov r4, #0x1000 /* spin spin spin */ - mov r8, #0x4 /* first pass condition & set registers */ - cmp r8, #0x4 -2: - ldrne r8, [r3] /* DPLL lock check */ - and r8, r8, #0x7 - cmp r8, #0x2 - beq 4f -3: - subeq r8, r8, #0x1 - streq r8, [r0] /* commit dividers (2nd time) */ - nop -lloop1: - sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop1 - mov r4, #0x40000 - cmp r8, #0x1 - nop - streq r2, [r1] /* lock dpll (2nd time) */ - nop -lloop2: - sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop2 - mov r4, #0x40000 - cmp r8, #0x1 - nop - ldreq r8, [r3] /* get lock condition for dpll */ - cmp r8, #0x4 /* first time though? */ - bne 2b - moveq r8, #0x2 /* set to dpll check condition. */ - beq 3b /* if condition not true branch */ -4: - ldr r4, [sp] - add sp, sp, #0x4 /* return stack space */ - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -cfg3_0_addr: - .word GPMC_CONFIG3_0 -cfg3_0_val: - .word SMNAND_GPMC_CONFIG3 -cfg4_0_addr: - .word GPMC_CONFIG4_0 -cfg4_0_val: - .word SMNAND_GPMC_CONFIG4 -cfg1_0_addr: - .word GPMC_CONFIG1_0 -pll_ctl_add: - .word CM_CLKEN_PLL -pll_stat: - .word CM_IDLEST_CKGEN -pll_div_add: - .word CM_CLKSEL1_PLL -pll_div_val: - .word DPLL_VAL /* DPLL setting (300MHz default) */ -#endif - -.globl platformsetup -platformsetup: - mov r3, r0 /* save skip information */ -#ifdef CONFIG_APTIX - ldr r0, REG_SDRC_MCFG_0 - ldr r1, VAL_SDRC_MCFG_0 - str r1, [r0] - ldr r0, REG_SDRC_MR_0 - ldr r1, VAL_SDRC_MR_0 - str r1, [r0] - /* a ddr needs emr1 set here */ - ldr r0, REG_SDRC_SHARING - ldr r1, VAL_SDRC_SHARING - str r1, [r0] - ldr r0, REG_SDRC_RFR_CTRL_0 - ldr r1, VAL_SDRC_RFR_CTRL_0 - str r1, [r0] - - /* little delay after init */ - mov r2, #0x1800 -1: - subs r2, r2, #0x1 - bne 1b -#endif -#ifdef CONFIG_PARTIAL_SRAM - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - mov r0, r3 /* pass skip info to s_init */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ -#endif - - /* map interrupt controller */ - ldr r0, VAL_INTH_SETUP - mcr p15, 0, r0, c15, c2, 4 - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -VAL_INTH_SETUP: - .word PERIFERAL_PORT_BASE -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - - - - - - diff --git a/board/omap2420h4/x-load.lds b/board/omap2420h4/x-load.lds deleted file mode 100644 index f664ca7..0000000 --- a/board/omap2420h4/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm1136/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/drivers/Makefile b/drivers/Makefile index 25c5735..9fc61f6 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -48,10 +48,6 @@ ifeq ($(BOARD), overo) COBJS += k9f1g08r0a.o endif -ifeq ($(BOARD), omap2420h4) -COBJS += k9k1216.o -endif - ifeq ($(BOARD), omap2430sdp) COBJS += k9k1216.o endif diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h deleted file mode 100644 index 7495d7f..0000000 --- a/include/configs/omap2420h4.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2004 - 2005 Texas Instruments. - * - * X-Loader Configuation settings for the TI OMAP H4 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2420 1 /* which is in a 2420 */ -#define CONFIG_OMAP2420H4 1 /* and on a H4 board */ - -#define CONFIG_OMAP242X - -#define PRCM_CONFIG_II 1 -//#define PRCM_CONFIG_III 1 -#define CONFIG_PARTIAL_SRAM 1 - -//#define CFG_SDRAM_DDR 1 -#define CFG_SDRAM_COMBO 2 -//#define CFG_SDRAM_SDR 3 -//#define CFG_SDRAM_STACKED 4 - -/* Chipselect and NAND information : - Since we share the mem.h from u-boot, we define few macros here - so as to pick the right gpmc values from there for the macros in mem.h -*/ -/* NAND fixed at CS5 */ -#define OMAP24XX_GPMC_CS0 SMNAND -#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M -#define OMAP24XX_GPMC_CS0_MAP CFG_FLASH_BASE -#define CFG_NAND_BOOT -#define NAND_LEGACY - -#include /* get chip and board defs */ - -#define V_SCLK 12000000 -/* input clock of PLL */ -/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ -#define CONFIG_SYS_CLK_FREQ V_SCLK - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 OMAP2420_UART1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on H4 */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80000000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -/*----------------------------------------------------------------------- - * Board NAND Info. - */ -#define CFG_NAND_K9K1216 /* Samsung 16-bit 64MB chip */ - -#define NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ - -/* H4 NAND is partitioned: - * 0x0000000 - 0x0010000 Booting Image - * 0x0010000 - 0x0050000 U-Boot Image - * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care) - * 0x0080000 - 0x4000000 depends on application - */ -#define NAND_UBOOT_START 0x0040000 -#define NAND_UBOOT_END 0x0080000 -#define NAND_BLOCK_SIZE 0x4000 - -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0) -#define READ_NAND(adr) (*(volatile u16 *)0x6800A084) - -#define NAND_WAIT_READY() - -#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) -#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) - -#define NAND_CTL_CLRALE(adr) -#define NAND_CTL_SETALE(adr) -#define NAND_CTL_CLRCLE(adr) -#define NAND_CTL_SETCLE(adr) -#define NAND_DISABLE_CE() -#define NAND_ENABLE_CE() - - -#endif /* __CONFIG_H */ -- 2.39.2