From 440956a72fa42593e8dd9913356e95a77c59c87f Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 14 Jul 2011 17:34:12 +0530 Subject: [PATCH] omap2420sdp: Remove this board because is not being maintained Discussed in this thread, http://groups.google.com/group/x-loader/browse_thread/thread/42ee3aa6df45a896/ea7296ba34155bad#ea7296ba34155bad Signed-off-by: Enric Balletbo i Serra Signed-off-by: Anand Gadiyar --- Makefile | 3 - board/omap2430sdp/Makefile | 51 --- board/omap2430sdp/config.mk | 28 -- board/omap2430sdp/omap2430sdp.c | 746 -------------------------------- board/omap2430sdp/platform.S | 198 --------- board/omap2430sdp/x-load.lds | 54 --- drivers/Makefile | 4 - include/configs/omap2430sdp.h | 178 -------- 8 files changed, 1262 deletions(-) delete mode 100644 board/omap2430sdp/Makefile delete mode 100644 board/omap2430sdp/config.mk delete mode 100644 board/omap2430sdp/omap2430sdp.c delete mode 100644 board/omap2430sdp/platform.S delete mode 100644 board/omap2430sdp/x-load.lds delete mode 100644 include/configs/omap2430sdp.h diff --git a/Makefile b/Makefile index f378923..a4ea69e 100644 --- a/Makefile +++ b/Makefile @@ -201,9 +201,6 @@ unconfig: ## OMAP2 (ARM1136) Systems ######################################################################### -omap2430sdp_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm1136 omap2430sdp - ######################################################################### ## OMAP3 (ARM-CortexA8) Systems ######################################################################### diff --git a/board/omap2430sdp/Makefile b/board/omap2430sdp/Makefile deleted file mode 100644 index b6c984c..0000000 --- a/board/omap2430sdp/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap2430sdp.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/omap2430sdp/config.mk b/board/omap2430sdp/config.mk deleted file mode 100644 index 7bc5078..0000000 --- a/board/omap2430sdp/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2004 -# Texas Instruments, -# -# TI H4 board with OMAP2420 (ARM1136) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 -# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) ES2 will be configurable -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# 2430 h4 has same mem configuration as h4. - -# For use with external or internal boots. -# CONFIG_PARTIAL_SRAM must be defined to use this. -TEXT_BASE = 0x80e80000 - -# Used with full SRAM boot. -# This is either with a GP system or a signed boot image. -# easiest, and safest way to go if you can. -# Comment out //CONFIG_PARTIAL_SRAM for this one. -# -#TEXT_BASE = 0x40280000 - diff --git a/board/omap2430sdp/omap2430sdp.c b/board/omap2430sdp/omap2430sdp.c deleted file mode 100644 index f2a7b42..0000000 --- a/board/omap2430sdp/omap2430sdp.c +++ /dev/null @@ -1,746 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Texas Instruments, - * Jian Zhang - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include - -static void wait_for_command_complete(unsigned int wd_base); -static void watchdog_init(void); -static void peripheral_enable(void); -static void muxSetupAll(void); -static u32 get_cpu_rev(void); -static u32 get_device_type(void); -static void prcm_init(void); - - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 v; - v = __raw_readl(TAP_IDCODE_REG); - v = v >> 28; - return(v+1); /* currently 2422 and 2420 match up */ -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return(mode >>= 8); -} - -/************************************************************* - * Helper function to wait for the status of a register - *************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return(1); - if (i==bound) - return(0); - } while (1); -} - -/************************************************************* - * Support for multiple type of memory types - *************************************************************/ -#ifdef CFG_SDRAM_DDR -void -config_sdram_ddr(u32 rev) -{ - /* ball D11, mode 0 */ - __raw_writeb(0x08, 0x48000032); - - /* SDRC_CS0 Configuration */ - __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - - /* - * CS0 SDRC Mode Register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - __raw_writel(0x00000032, SDRC_MR_0); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x - -} -#endif // CFG_SDRAM_DDR - -#ifdef CFG_SDRAM_COMBO -void -config_sdram_combo(u32 rev) -{ - - u32 dllctrl=0; - - /* ball C12, mode 0 */ - __raw_writeb(0x00, 0x480000a1); - /* ball D11, mode 0 */ - __raw_writeb(0x00, 0x48000032); - /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */ - __raw_writeb(0x00, 0x480000a3); - - /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */ - __raw_writel(0x00000012, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */ - __raw_writel(0x00000000, SDRC_SYSCONFIG); - - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - if (rev == CPU_2420_2422_ES1) - __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); - else - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - - /* This is reqd only for ES1 */ - if (rev == CPU_242X_ES1) - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0); - - /* CS1 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); - /* This is reqd only for ES1 */ - if (rev == CPU_242X_ES1) - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, 0x680090d8); - __raw_writel(CMD_PRECHARGE, 0x680090d8); - __raw_writel(CMD_AUTOREFRESH, 0x680090d8); - __raw_writel(CMD_AUTOREFRESH, 0x680090d8); - - /* CS1 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, 0x680090b4); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - - if (rev == CPU_242X_ES1) - dllctrl = (BIT0|BIT3); - else - dllctrl = BIT0; - - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLA_CTRL); - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x - // __raw_writel(0x00009808, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ? - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x - //__raw_writel(0x00009808, SDRC_DLLB_CTRL); // ES2.x - } -} - -#endif // CFG_SDRAM_COMBO - -#ifdef CFG_2430SDRAM_DDR -void -config_2430sdram_ddr(u32 rev) -{ - u32 dllstat, dllctrl; - - __raw_writel(0x00000012, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */ - __raw_writel(0x00000000, SDRC_SYSCONFIG); - - /* Chip-level shared interface management */ - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */ - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX14: 32Mbx32 */ - __raw_writel(SDP_2430_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_2430_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - - __raw_writel(H4_2420_SDRC_RFR_CTRL, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 2 - SDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2420_SDRC_MR_0_DDR, SDRC_MR_0); - - /* Set up SDRC DLL values for 2430 DDR */ - dllctrl = (SDP_2430_SDRC_DLLAB_CTRL & ~BIT2); /* set target ctrl val */ - __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set lock mode */ - __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set lock mode */ - delay(0x1000); /* time to track to center */ - dllstat = __raw_readl(SDRC_DLLA_STATUS) & 0xFF00; /* get status */ - dllctrl = (dllctrl & 0x00FF) | dllstat | BIT2; /* build unlock value */ - __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set unlock mode */ - __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set unlock mode */ -} -#endif // CFG_2430SDRAM_DDR - -#ifdef CFG_SDRAM_STACKED -void -config_sdram_stacked(u32 rev) -{ - - /* Pin Muxing for SDRC */ - __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */ - __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */ - __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */ - __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */ - - /* configure sdrc 32 bit for COMBO ddr sdram */ - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */ - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */ - - /* SDRC_SHARING */ - /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */ - //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - __raw_writel(0x00004900, SDRC_SHARING); - - /* SDRC_CS0 Configuration */ - /* None for ES2.1 */ - - /* SDRC_CS1 Configuration */ - __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */ - - /* Disable power down of CKE */ - __raw_writel(0x00000085, SDRC_POWER); - - __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */ - __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */ - __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */ - __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */ - - /*Manual Command sequence */ - __raw_writel(0x00000000, 0x680090D8); - __raw_writel(0x00000001, 0x680090D8); - __raw_writel(0x00000002, 0x680090D8); - __raw_writel(0x00000002, 0x680090D8); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(0x00000032, 0x680090B4); - __raw_writel(0x00000020, 0x680090BC); /* weak-strength driver */ - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x - } -} -#endif // CFG_SDRAM_STACKED - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(u32 *shift) -{ -#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ -#define GPT_CTR OMAP24XX_GPT2+TCRR /* read counter address */ - u32 start, cstart, cend, cdiff, val; - unsigned int v, if_clks=0, func_clks=0 ; - - - - if(__raw_readl(PRCM_CLKSRC_CTRL) & BIT7){ /* if currently /2 */ - *shift = 1; - }else{ - *shift = 0; - } - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* mask for sys_clk use */ - __raw_writel(val, CM_CLKSEL2_CORE); /* timer2 source to sys_clk */ - __raw_writel(BIT4, CM_ICLKEN1_CORE); /* timer2 interface clock on */ - __raw_writel(BIT4, CM_FCLKEN1_CORE); /* timer2 function clock on */ - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - __raw_writel(0, OMAP24XX_GPT2+TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP24XX_GPT2+TCLR); /* enable clock */ - /* enable 32kHz source */ /* enabled out of reset */ - /* determine sys_clk via gauging */ - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles*/ - while(__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(GPT_CTR); /* get start sys_clk count */ - while(__raw_readl(S32K_CR) < (start+20)); /* wait for 40 cycles */ - cend = __raw_readl(GPT_CTR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - /* based on number of ticks assign speed */ - if(cdiff > (19000 >> *shift)) - return(S38_4M); - else if (cdiff > (15200 >> *shift)) - return(S26M); - else if (cdiff > (13000 >> *shift)) - return(S24M); - else if (cdiff > (9000 >> *shift)) - return(S19_2M); - else if (cdiff > (7600 >> *shift)) - return(S13M); - else - return(S12M); -} - -/********************************************************************************* - * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default). - * -- called from SRAM - *********************************************************************************/ -void -prcm_init() -{ - u32 div, speed, val, div_by_2; - - val = __raw_readl(PRCM_CLKSRC_CTRL) & ~(BIT1 | BIT0); -#if defined(OMAP2430_SQUARE_CLOCK_INPUT) - __raw_writel(val, PRCM_CLKSRC_CTRL); -#else - __raw_writel((val | BIT0), PRCM_CLKSRC_CTRL); -#endif - speed = get_osc_clk_speed(&div_by_2); - if((speed > S19_2M) && (!div_by_2)){ /* if fast && /2 off, enable it */ - val = ~(BIT6|BIT7) & __raw_readl(PRCM_CLKSRC_CTRL); - val |= (0x2 << 6); /* divide by 2 if (24,26,38.4) -> (12/13/19.2) */ - __raw_writel(val, PRCM_CLKSRC_CTRL); - } - - __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */ - __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */ - __raw_writel(0, CM_ICLKEN1_CORE); - __raw_writel(0, CM_ICLKEN2_CORE); - - /*DPLL into low power bypass (others off) */ - __raw_writel(0x00000001, CM_CLKEN_PLL); - - __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */ - __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */ - __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */ - __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */ - __raw_writel(MDM_DIV, CM_CLKSEL_MDM); /* set mdm dividers */ - - div = BUS_DIV; - __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/SSi dividers */ - delay(1000); - - /*13MHz apll src, PRCM 'x' DPLL rate */ - __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); - - /*Valid the configuration */ - __raw_writel(0x00000001, PRCM_CLKCFG_CTRL); - delay(1000); - - /* set up APLLS_CLKIN per crystal */ - if (speed > S19_2M) - speed >>= 1; /* if fast shift to /2 range */ - val = (0x2 << 23); /* default to 13Mhz for 2430c */ - if (speed == S12M) - val = (0x3 << 23); - else if (speed == S19_2M) - val = (0x0 << 23); - val |= (~(BIT23|BIT24|BIT25) & __raw_readl(CM_CLKSEL1_PLL)); - __raw_writel(val, CM_CLKSEL1_PLL); - - __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */ - wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);/* wait for apll lock */ - - delay(200000); -} - -void SEC_generic(void) -{ -/* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); /* REQ_INFO_PERMISSION_1 L*/ - __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ - __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); /* ADDR_MATCH_1 L*/ - - - __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ - - __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ - __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80); /* ADDR_MATCH_2 L*/ - - /* IVA Changes */ - __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for general use. - ***********************************************************/ -void try_unlock_sram(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - mode = get_device_type(); - - if ((mode == GP_DEVICE) || (mode == HS_DEVICE) || (mode == EMU_DEVICE) - || (mode == TST_DEVICE)) { - /* Secure or Emulation device - HS/E/T */ - SEC_generic(); - } - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -int s_init(int skip) -{ - u32 rev; - - rev = get_cpu_rev(); - - watchdog_init(); - try_unlock_sram(); - muxSetupAll(); - delay(100); - prcm_init(); - -#ifdef CFG_SDRAM_DDR - config_sdram_ddr(rev); -#elif defined(CFG_SDRAM_COMBO) - config_sdram_combo(rev); -#elif defined(CFG_2430SDRAM_DDR) - config_2430sdram_ddr(rev); -#elif defined(CFG_SDRAM_STACKED) - config_sdram_stacked(rev); -#else -#error SDRAM type not supported -#endif - - delay(20000); - peripheral_enable(); - return(0); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -static void watchdog_init(void) -{ -#define GP (BIT8|BIT9) - - /* There are 4 watch dogs. 1 secure, and 3 general purpose. - * I would expect that the ROM takes care of the secure one, - * but we will try also. Of the 3 GP ones, 1 can reset us - * directly, the other 2 only generate MPU interrupts. - */ - __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); - -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -static void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base+WWPS); - } while (pending); -} - - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -static void peripheral_enable(void) -{ - unsigned int v, if_clks=0, if_clks2 = 0, func_clks=0, func_clks2 = 0; - - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP24XX_GPT2 */ - __raw_writel(v, CM_CLKSEL2_CORE); - __raw_writel(0x1, CM_CLKSEL_WKUP); - -#ifdef CFG_NS16550 - /* Enable UART1 clock */ - func_clks |= BIT21; - if_clks |= BIT21; -#endif - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2; /* Interface clocks on */ - __raw_writel(v, CM_ICLKEN2_CORE); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN2_CORE); - delay(1000); - -} - -/* Do pin muxing for all the devices used in X-Loader */ -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writeb(VALUE, OMAP24XX_CTRL_BASE + OFFSET); -static void muxSetupAll(void) -{ - /* UART 1*/ - MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */ - MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */ - MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */ - MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */ - MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */ - MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */ - MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */ - MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */ - - /* Mux settings for SDRC */ - MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */ - MUX_VAL(0x0055, 0x1B) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */ - MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */ - MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */ - MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */ - /* GPMC */ - MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */ - MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */ - MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */ - MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */ - MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */ - MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */ - MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */ - MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */ - MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */ - MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */ - MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */ - MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */ -} - -int nand_init(void) -{ - u32 rev; - - /* GPMC Configuration */ - rev = get_cpu_rev(); - - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CFG_NAND - __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ -#endif - - /* Set the GPMC Vals . For NAND boot on 2430SDP, NAND is mapped at CS0 - * , NOR at CS1 and MPDB at CS5. And oneNAND boot, we map oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS in done in u-boot anyway. So we don't have to bother doing it here. - */ - __raw_writel(0, GPMC_CONFIG7_0); - sdelay(1000); - -#ifdef CFG_NAND - __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1_0); - __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2_0); - __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3_0); - __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4_0); - __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5_0); - __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6_0); - -#else /* CFG_ONENAND */ - __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1_0); - __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2_0); - __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3_0); - __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4_0); - __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5_0); - __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6_0); -#endif - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP24XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((OMAP24XX_GPMC_CS0_MAP>>24) & 0x3F) | - (1<<6) ), GPMC_CONFIG7_0); - sdelay(2000); -#ifdef CFG_NAND - if (nand_chip()){ -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } -#else - if (onenand_chip()){ -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - -#endif - return 0; -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} diff --git a/board/omap2430sdp/platform.S b/board/omap2430sdp/platform.S deleted file mode 100644 index f221d7e..0000000 --- a/board/omap2430sdp/platform.S +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2005 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = PRCM_CLKCFG_CTRL - addr of valid reg - * R1 = CM_CLKEN_PLL - addr dpll ctlr reg - * R2 = dpll value - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - ******************************************************************************/ -.global go_to_speed - go_to_speed: - sub sp, sp, #0x4 /* get some stack space */ - str r4, [sp] /* save r4's value */ - - /* move into fast relock bypass */ - ldr r8, pll_ctl_add - mov r4, #0x2 - str r4, [r8] - ldr r4, pll_stat -block: - ldr r8, [r4] /* wait for bypass to take effect */ - and r8, r8, #0x3 - cmp r8, #0x1 - bne block - - /* set new dpll dividers _after_ in bypass */ - ldr r4, pll_div_add - ldr r8, pll_div_val - str r8, [r4] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r4, flash_cfg3_addr - ldr r8, flash_cfg3_val - str r8, [r4] - ldr r4, flash_cfg4_addr - ldr r8, flash_cfg4_val - str r8, [r4] - ldr r4, flash_cfg1_addr - ldr r8, [r4] - orr r8, r8, #0x3 /* up gpmc divider */ - str r8, [r4] - - /* setup to 2x loop though code. The first loop pre-loads the - * icache, the 2nd commits the prcm config, and locks the dpll - */ - mov r4, #0x1000 /* spin spin spin */ - mov r8, #0x4 /* first pass condition & set registers */ - cmp r8, #0x4 -2: - ldrne r8, [r3] /* DPLL lock check */ - and r8, r8, #0x7 - cmp r8, #0x2 - beq 4f -3: - subeq r8, r8, #0x1 - streq r8, [r0] /* commit dividers (2nd time) */ - nop -lloop1: - sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop1 - mov r4, #0x40000 - cmp r8, #0x1 - nop - streq r2, [r1] /* lock dpll (2nd time) */ - nop -lloop2: - sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop2 - mov r4, #0x40000 - cmp r8, #0x1 - nop - ldreq r8, [r3] /* get lock condition for dpll */ - cmp r8, #0x4 /* first time though? */ - bne 2b - moveq r8, #0x2 /* set to dpll check condition. */ - beq 3b /* if condition not true branch */ -4: - ldr r4, [sp] - add sp, sp, #0x4 /* return stack space */ - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -#ifdef CFG_ONENAND -flash_cfg3_addr: - .word GPMC_CONFIG3_0 -flash_cfg3_val: - .word ONENAND_GPMC_CONFIG3 -flash_cfg4_addr: - .word GPMC_CONFIG4_0 -flash_cfg4_val: - .word ONENAND_GPMC_CONFIG4 -flash_cfg1_addr: - .word GPMC_CONFIG1_0 -#else -flash_cfg3_addr: - .word GPMC_CONFIG3_0 -flash_cfg3_val: - .word SMNAND_GPMC_CONFIG3 -flash_cfg4_addr: - .word GPMC_CONFIG4_0 -flash_cfg4_val: - .word SMNAND_GPMC_CONFIG4 -flash_cfg1_addr: - .word GPMC_CONFIG1_0 -#endif -pll_ctl_add: - .word CM_CLKEN_PLL -pll_stat: - .word CM_IDLEST_CKGEN -pll_div_add: - .word CM_CLKSEL1_PLL -pll_div_val: - .word DPLL_VAL /* DPLL setting (300MHz default) */ - -.globl platformsetup -platformsetup: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* map interrupt controller */ - ldr r0, VAL_INTH_SETUP - mcr p15, 0, r0, c15, c2, 4 - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -VAL_INTH_SETUP: - .word PERIFERAL_PORT_BASE -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - diff --git a/board/omap2430sdp/x-load.lds b/board/omap2430sdp/x-load.lds deleted file mode 100644 index f12e8f8..0000000 --- a/board/omap2430sdp/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004-2005 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm1136/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/drivers/Makefile b/drivers/Makefile index 9fc61f6..bd620c2 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -48,10 +48,6 @@ ifeq ($(BOARD), overo) COBJS += k9f1g08r0a.o endif -ifeq ($(BOARD), omap2430sdp) -COBJS += k9k1216.o -endif - ifeq ($(BOARD), igep00x0) COBJS += onenand.o endif diff --git a/include/configs/omap2430sdp.h b/include/configs/omap2430sdp.h deleted file mode 100644 index 3fda61f..0000000 --- a/include/configs/omap2430sdp.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * (C) Copyright 2004 Texas Instruments. - * - * X-Loader Configuation settings for the TI OMAP H4 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2430H4 1 /* and on a H4 board */ - -#define CONFIG_OMAP243X 1 - -//#define PRCM_CONFIG_5A 1 -#define PRCM_CONFIG_2 1 /* 2430 ES2+330ARM+DDR-165-PISMO */ - -#define OMAP2430_SQUARE_CLOCK_INPUT 1 - -/* Memory type */ -//#define CFG_SDRAM_DDR 1 /* not tested */ -//#define CFG_SDRAM_COMBO 2 /* not tested */ -#define CFG_2430SDRAM_DDR 3 -//#define CFG_SDRAM_STACKED 4 /* not tested */ - -/* The actual register values are defined in u-boot- mem.h */ -/* SDRAM Bank Allocation method */ -//#define SDRC_B_R_C 1 -//#define SDRC_B1_R_B0_C 1 -#define SDRC_R_B_C 1 - -/* Boot type */ -//#define CFG_NAND 1 -#define CFG_ONENAND 1 - -# define NAND_BASE 0x0C000000 /* NAND flash */ -# define ONENAND_BASE 0x20000000 /* OneNand flash */ - -#ifdef CFG_NAND -#define NAND_LEGACY -#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M -#define OMAP24XX_GPMC_CS0_MAP NAND_BASE -#else -#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_128M -#define OMAP24XX_GPMC_CS0_MAP ONENAND_BASE -#define ONENAND_ADDR ONENAND_BASE /* physical address to access OneNAND at CS0*/ -#endif - -/* Another dependency on u-boot */ -#define sdelay delay - -#include /* get chip and board defs */ - -#define V_SCLK 13000000 -/* input clock of PLL */ -/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ -#define CONFIG_SYS_CLK_FREQ V_SCLK - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 OMAP2430_UART1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on 2430SDP */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80008000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -#ifdef CFG_NAND - -/*----------------------------------------------------------------------- - * Board NAND Info. - */ -#define CFG_NAND_K9K1216 /* Samsung 16-bit 64MB chip */ - -/* NAND is partitioned: - * 0x0000000 - 0x0010000 Booting Image - * 0x0010000 - 0x0050000 U-Boot Image - * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care) - * 0x0080000 - 0x00B0000 Kernel Image - * 0x00B0000 - 0x4000000 depends on application - */ -#define NAND_UBOOT_START 0x0040000 -#define NAND_UBOOT_END 0x0080000 -#define NAND_BLOCK_SIZE 0x4000 - -#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50) -#define GPMC_NAND_COMMAND_0 (OMAP24XX_GPMC_BASE+0x7C) -#define GPMC_NAND_ADDRESS_0 (OMAP24XX_GPMC_BASE+0x80) -#define GPMC_NAND_DATA_0 (OMAP24XX_GPMC_BASE+0x84) - -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0) -#define READ_NAND(adr) (*(volatile u16 *)GPMC_NAND_DATA_0) -#define NAND_WAIT_READY() -#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) -#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) - -#define NAND_CTL_CLRALE(adr) -#define NAND_CTL_SETALE(adr) -#define NAND_CTL_CLRCLE(adr) -#define NAND_CTL_SETCLE(adr) -#define NAND_DISABLE_CE() -#define NAND_ENABLE_CE() - -#else -/*----------------------------------------------------------------------- - * Board oneNAND Info. - */ -#define CFG_SYNC_BURST_READ 1 - -/* OneNAND is partitioned: - * 0x0000000 - 0x0080000 X-Loader - * 0x0080000 - 0x00c0000 U-boot Image - * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) - * 0x00e0000 - 0x0120000 Kernel Image - * 0x0120000 - 0x4000000 depends on application - */ - -#define ONENAND_START_BLOCK 4 -#define ONENAND_END_BLOCK 6 -#define ONENAND_PAGE_SIZE 2048 /* 2KB */ -#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ - -#endif // oneNAND -#endif /* __CONFIG_H */ -- 2.39.2