From fe41a5e1b991d8b38f1abfa91ec0630576ad574f Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Tue, 18 Feb 2025 16:34:56 +0800 Subject: [PATCH] arm: dts: agilex5: Enable XGMAC Enable XGMAC for SoCFPGA Agilex5 devkit. Link: https://lore.kernel.org/all/20241204064755.10226-2-mun.yew.tham@intel.com/ Signed-off-by: Tien Fong Chee --- .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 9eb21d65428..540b2662283 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -3,6 +3,7 @@ * U-Boot additions * * Copyright (C) 2024 Intel Corporation + * Copyright (C) 2025 Altera Corporation */ #include "socfpga_agilex5-u-boot.dtsi" @@ -122,3 +123,36 @@ bootph-all; }; +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; -- 2.39.5