From fc20eeff6c03fcdbb2b5ac21472778b573850e77 Mon Sep 17 00:00:00 2001
From: Mark Zhang <markz@nvidia.com>
Date: Wed, 7 Aug 2013 19:25:08 +0800
Subject: [PATCH] clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2

pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
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